Semiconductor device structure with bottle-shaped silicon vias and method of making the same

Abstract

The present disclosure provides a semiconductor element structure and a method of fabricating the same. The semiconductor element structure includes a silicon layer disposed on a first semiconductor die, and a first mask layer disposed on the silicon layer. The semiconductor element structure also includes a second semiconductor die disposed on the first mask layer, and a silicon via penetrating through the silicon layer and the first mask layer. A lower surface of the silicon via is greater than an upper surface of the silicon via, and the upper surface of the silicon via is greater than a cross-section of the silicon via, the cross-section being between the lower surface and the upper surface of the silicon via and being parallel to the lower surface and the upper surface of the silicon via.

Description

[0001] Cross-referencing

[0002] This disclosure asserts priority and benefits to U.S. Official Application No. 17 / 093,974, filed November 10, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device structure and a method for fabricating the same. In particular, it relates to a semiconductor device structure having a bottle-shaped through-silicon via and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various forms of semiconductor devices.

[0005] However, the manufacturing and integration of these semiconductor devices involves many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in manufacturing and integrating semiconductor devices can lead to various defects. Therefore, there is a need for continuous improvement of the manufacturing processes for these semiconductor devices to address these defects and enhance their performance.

[0006] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes: a silicon layer disposed on a first semiconductor die; and a first masking layer disposed on the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed on the first masking layer; and a silicon via (SVR) passing through the silicon layer and the first masking layer. A lower surface of the SVR is larger than an upper surface of the SVR, and the upper surface of the SVR is larger than a cross-section of the SVR located between the lower and upper surfaces of the SVR, and the cross-section is parallel to the lower and upper surfaces of the SVR.

[0008] In some embodiments, the through-silicon via directly contacts a first conductive pad in the first semiconductor die and a second conductive pad in the second semiconductor die. In some embodiments, the semiconductor device structure further includes a third conductive pad disposed in the first semiconductor die and adjacent to the first conductive pad; and a fourth conductive pad disposed in the second semiconductor die and adjacent to the second conductive pad, wherein a lateral distance between the third conductive pad and the first conductive pad in the first semiconductor die is greater than a lateral distance between the fourth conductive pad and the second conductive pad in the second semiconductor die. In some embodiments, the semiconductor device structure further includes a second masking layer disposed between the first masking layer and the second semiconductor die, wherein the through-silicon via passes through the second masking layer, and wherein the first masking layer and the second masking layer comprise different materials.

[0009] In some embodiments, one sidewall of the second masking layer is inclined relative to one sidewall of the first masking layer. In some embodiments, the semiconductor device structure further includes a protective layer covering the sidewall of the second masking layer, the sidewall of the first masking layer, and an upper sidewall of the silicon layer, wherein the upper sidewall of the silicon layer is substantially aligned with the sidewall of the first masking layer. In some embodiments, the silicon via includes a conductive layer; a barrier layer covering each sidewall and a lower surface of the conductive layer, wherein the barrier layer directly contacts the first semiconductor die; and a pad layer covering each sidewall of the barrier layer.

[0010] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a silicon layer disposed on a first semiconductor die; and a first masking layer disposed on the silicon layer. The semiconductor device structure also includes a second masking layer disposed on the first masking layer; and a second semiconductor die disposed on the second masking layer. The semiconductor device structure further includes a through-silicon via (TSV) passing through the silicon layer, the first masking layer, and the second masking layer to electrically connect the first semiconductor die and the second semiconductor die. The TSV has a bottle-shaped portion surrounded by the first masking layer and an upper portion of the silicon layer, and the interface area between the TSV and the first semiconductor die is larger than the interface area between the TSV and the second semiconductor die.

[0011] In some embodiments, the first semiconductor die has a first critical dimension, and the second semiconductor die has a second critical dimension, wherein the first critical dimension is larger than the second critical dimension. In some embodiments, the silicon via further includes an upper portion surrounded by the second masking layer and a lower portion surrounded by a lower portion of the silicon layer; wherein the bottle-shaped portion of the silicon via is sandwiched between the upper portion and the lower portion, and the upper portion of the silicon via has a tapered profile that tapers towards the bottle-shaped portion of the silicon via.

[0012] In some embodiments, the lower portion of the silicon via has a plurality of rounded and convex corners. In some embodiments, the bottle-shaped portion of the silicon via is separated from the first masking layer, the second masking layer, and the upper portion of the silicon layer by a protective layer. In some embodiments, the lower portion of the silicon via directly contacts the lower portion of the silicon layer. In some embodiments, the protective layer comprises aluminum oxide.

[0013] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes: forming a silicon layer on a first semiconductor die; and forming a first masking layer on the silicon layer. The method also includes forming a first opening through the first masking layer, and forming a second opening through the silicon layer; and depositing a protective layer on the first masking layer. The protective layer extends to cover a sidewall of the first masking layer and an upper sidewall of the silicon layer. The method further includes using the protective layer as a mask to etch the silicon layer, thereby undercutting an upper portion of the silicon layer to form an enlarged second opening. Furthermore, the method includes filling the first opening and the enlarged second opening with a silicon via; and forming a second semiconductor die on the silicon via.

[0014] In some embodiments, the fabrication method further includes forming a second masking layer on the first masking layer; and forming a third opening to pass through the second masking layer before the formation of the first opening through the first masking layer. In some embodiments, during the formation of the second opening through the silicon layer, the second masking layer is etched to form an enlarged third opening, and the enlarged third opening has a tapered profile that tapers towards the first opening.

[0015] In some embodiments, the protective layer is fabricated using a non-conformal deposition process. In some embodiments, the fabrication method further includes removing the protective layer prior to the formation of the silicon via. In some embodiments, the upper portion of the silicon layer covers the lower portion of the silicon via.

[0016] Some embodiments of this disclosure provide a semiconductor device structure and a method for fabricating the same. In some embodiments, the semiconductor device structure has a through-silicon via (TSV). The lower surface of the TSV is larger than the upper surface of the TSV, and the upper surface of the TSV is larger than a cross-section of the TSV located between the upper and lower surfaces of the TSV, and the cross-section is parallel to the upper and lower surfaces of the TSV. Therefore, the TSV can be used to electrically connect two semiconductor dies (or semiconductor wafers) that are vertically aligned and have different design rules. As a result, functional density (i.e., the number of interconnected devices per unit chip area) can be increased, and several benefits can be provided, such as improved manufacturing efficiency, reduced costs, and improved performance.

[0017] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0018] A more complete understanding of the disclosure can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims, wherein the same element symbols in the drawings refer to the same elements.

[0019] Figure 1 A cross-sectional schematic diagram illustrating some embodiments of the present disclosure is shown.

[0020] Figure 2 Examples of some embodiments of this disclosure Figure 1 An enlarged schematic diagram.

[0021] Figure 3 A cross-sectional schematic diagram illustrating an improved semiconductor device structure according to some embodiments of the present disclosure is shown.

[0022] Figure 4 Examples of some embodiments of this disclosure Figure 3 An enlarged schematic diagram.

[0023] Figure 5 A schematic flowchart illustrating a method for fabricating a semiconductor device structure according to some embodiments of this disclosure is shown.

[0024] Figure 6The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein a silicon layer is formed on a first semiconductor die during the formation of the semiconductor device structure.

[0025] Figure 7 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein, during the formation of the semiconductor device structure, a first masking layer and a second masking layer are sequentially formed on the silicon layer.

[0026] Figure 8 A cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure is shown, wherein an opening is formed in the second masking layer during the formation of the semiconductor device structure.

[0027] Figure 9 A cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure is shown, wherein an opening is formed in the first masking layer during the formation of the semiconductor device structure.

[0028] Figure 10 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein an opening is formed in the silicon layer during the formation of the semiconductor device structure.

[0029] Figure 11 A cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure is shown, wherein a protective layer is deposited during the formation of the semiconductor device structure.

[0030] Figure 12 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage involves etching the silicon layer by using the protective layer as a mask during the formation of the semiconductor device structure.

[0031] Figure 13 A cross-sectional schematic diagram of an intermediate stage exemplifies some embodiments of the present disclosure, wherein the protective layer is removed during the formation of the semiconductor device structure.

[0032] Figure 14 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein, during the formation of the semiconductor device structure, a pad material is formed in each opening of the first masking layer, the second masking layer, and the silicon layer.

[0033] Figure 15 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage involves etching the pad material to form a pad layer during the formation of the semiconductor device structure.

[0034] Figure 16The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein a barrier material is formed on the pad layer during the formation of the semiconductor device structure.

[0035] Figure 17 A cross-sectional schematic diagram of an intermediate stage is shown, exemplifying some embodiments of the present disclosure, wherein a conductive material is formed on the barrier material during the formation of the semiconductor element structure.

[0036] Figure 18 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage, during the formation of a semiconductor device structure, planarizes the conductive material and the barrier material to form a through silicon via.

[0037] Figure 19 The illustration shows a cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure, wherein a pad material is formed on the protective layer during the formation of an improved semiconductor device structure.

[0038] Figure 20 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage involves etching the pad material to form a pad layer during the formation of an improved semiconductor device structure.

[0039] Figure 21 The following is a cross-sectional schematic diagram illustrating an intermediate stage of some embodiments of the present disclosure, wherein a barrier material is formed on the pad layer during the formation of an improved semiconductor device structure.

[0040] Figure 22 The illustration shows a cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure, wherein a conductive material is formed on the barrier material during the formation of an improved semiconductor device structure.

[0041] Figure 23 The following is a cross-sectional schematic diagram of an intermediate stage of some embodiments of the present disclosure, wherein the intermediate stage, during the formation of an improved semiconductor device structure, planarizes the conductive material and the barrier material to form a through-silicon via.

[0042] Explanation of reference numerals in the attached figures:

[0043] 10: Preparation method

[0044] 100: Semiconductor Component Structure

[0045] 101: Semiconductor substrate

[0046] 103: Dielectric layer

[0047] 105a: Conductive pad

[0048] 105b: Conductive pad

[0049] 105c: Conductive pad

[0050] 110: First semiconductor die

[0051] 111: Silicon layer

[0052] 111L: Lower part

[0053] 111U: Upper part

[0054] 113: First masking layer

[0055] 115: Second masking layer

[0056] 117: Patterned Masking

[0057] 120: Opening

[0058] 130: Opening

[0059] 130': Opening

[0060] 140: Opening

[0061] 150: Opening

[0062] 161: Protective layer

[0063] 161': Protective layer

[0064] 163: Padding Material

[0065] 163': Padding layer

[0066] 165: Barrier Materials

[0067] 165': Barrier layer

[0068] 167: Conductive materials

[0069] 167': Conductive layer

[0070] 169: Through-silicon vias

[0071] 169a: Upper part

[0072] 169b: Bottleneck Shape Section

[0073] 169B: Lower surface

[0074] 169c: lower part

[0075] 169T: Upper surface

[0076] 171: Semiconductor substrate

[0077] 173: Dielectric layer

[0078] 175a: Conductive pad

[0079] 175b: Conductive pad

[0080] 175c: Conductive pad

[0081] 175d: Conductive pad

[0082] 175e: Conductive pad

[0083] 180: Second semiconductor die

[0084] 200: Semiconductor Component Structure

[0085] 263: Padding material

[0086] 263': Padding layer

[0087] 265: Barrier Materials

[0088] 265': Barrier layer

[0089] 267: Conductive materials

[0090] 267': Conductive layer

[0091] 269: Through-silicon vias

[0092] 269a: Upper part

[0093] 269b: Bottleneck Shape Section

[0094] 269B: Lower surface

[0095] 269c: lower part

[0096] 269T: Upper surface

[0097] C: Upper corner

[0098] CS: Profile

[0099] D1: Lateral distance

[0100] D2: Lateral distance

[0101] S11: Steps

[0102] S13: Steps

[0103] S15: Steps

[0104] S17: Steps

[0105] S19: Steps

[0106] S21: Steps

[0107] S23: Steps

[0108] S25: Steps

[0109] S27: Steps

[0110] S29: Steps

[0111] SW1: Sidewall

[0112] SW2: Sidewall

[0113] USW: Upper sidewall

[0114] W1: Width

[0115] W2: Width

[0116] W3: Bottom Width

[0117] W4: Top width

[0118] W5: Bottom Width

[0119] W6: Top width

[0120] θ: Angle Detailed Implementation

[0121] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0122] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0123] Figure 1A cross-sectional schematic diagram illustrating some embodiments of the present disclosure is shown. For example... Figure 1 As shown, the semiconductor device structure 100 includes a first semiconductor die 110; a silicon layer 111 disposed on the first semiconductor die 100; a first mask layer 113 disposed on the silicon layer 111; a second mask layer 115 disposed on the first mask layer 113; and a second semiconductor die 180 disposed on the second mask layer 115.

[0124] In some embodiments, the first semiconductor die 110 has a semiconductor substrate 101; a dielectric layer 103 disposed on the semiconductor substrate 101; and a plurality of conductive pads 105a, 105b, and 105c disposed on the dielectric layer 103. In some embodiments, the conductive pads 105a, 105b, and 105c are disposed facing the silicon layer 111. Similar to the first semiconductor die 110, the second semiconductor die 180 has a semiconductor substrate 171; a dielectric layer 173; and a plurality of conductive pads 175a, 175b, 175c, 175d, and 175e disposed on the dielectric layer 173. In some embodiments, the conductive pads 175a, 175b, 175c, 175d, and 175e are disposed facing the second masking layer 115.

[0125] Please refer to the following: Figure 1 According to some embodiments, the semiconductor device structure 100 also includes a through-silicon via 169 that passes through the silicon layer 111, the first masking layer 113, and the second masking layer 115. In some embodiments, the through-silicon via 169 electrically connects a conductive pad 105c in the first semiconductor die 110 to a conductive pad 175d in the second semiconductor die 180. In some embodiments, the through-silicon via 169 is disposed in a keep-out zone, which defines an area in which no active element is placed.

[0126] Specifically, the through-silicon via 169 includes a conductive layer 167'; a barrier layer 165' disposed around the conductive layer 167'; and a pad layer 163' disposed around the barrier layer 165'. In some embodiments, the barrier layer 165' covers the lower surface and sidewalls of the conductive layer 167', while the pad layer 163' covers the sidewalls of the barrier layer 165'. In some embodiments, the barrier layer 165' and the pad layer 163' directly contact the conductive pad 105c, while the conductive layer 167' is separated from the conductive pad 105c by the barrier layer 165'.

[0127] Furthermore, such as Figure 1As shown, according to some embodiments, the silicon via 169 has a bottle-shaped profile. Furthermore, according to some embodiments, the sidewalls SW2 of the second masking layer 115 are inclined relative to the sidewalls SW1 of the first masking layer 113, and the sidewalls SW1 of the first masking layer 113 are substantially aligned with the upper sidewalls USW of the silicon layer 111. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0128] Furthermore, according to some embodiments, the critical size of the first semiconductor die 110 is larger than the critical size of the second semiconductor die 180. In some embodiments, the pattern density of the second semiconductor die 180 is greater than the pattern density of the first semiconductor die 110. In some embodiments, the conductive pad 105c directly contacting the through-silicon via 169 has a width W1, and the conductive pad 175d directly contacting the through-silicon via 169 has a width W2, where width W1 is greater than width W2. In some embodiments, a lateral distance between two adjacent conductive pads 105 in the first semiconductor die 110 is greater than a lateral distance between two adjacent conductive pads 175 in the second semiconductor die 180. For example, lateral distance D1 is greater than lateral distance D2. Because the through-silicon via 169 has a bottle-shaped profile, the through-silicon via 169 can be used to electrically connect the first semiconductor die 110 and the second semiconductor die 180 with different design rules (e.g., different pattern densities or different critical sizes). For example, a conductive pad 105c with a larger width W1 contacts a wider lower portion of a silicon via 169, while a conductive pad 175d with a smaller width W2 contacts an upper portion of a silicon via 169.

[0129] Figure 2 Examples of some embodiments of this disclosure Figure 1 An enlarged schematic diagram. Figure 2 An example of a silicon via 169 and its surroundings is shown. In some embodiments, the silicon via 169 includes an upper portion 169a, a lower portion 169c, and a bottleneck-shaped portion 169b, the bottleneck-shaped portion 169b being sandwiched between the upper portion 169a and the lower portion 169c. Dashed lines I-I' represent the boundary between the upper portion 169a and the bottleneck-shaped portion 169b, and dashed lines II-II' represent the boundary between the bottleneck-shaped portion 169b and the lower portion 169c. As described above, according to some embodiments, the silicon via 169 has a lower width W3 (i.e., the lowest width of the lower portion 169c) and an upper width W4 (i.e., the highest width of the upper portion 169a), the lower width W3 being greater than the upper width W4. Please refer to... Figure 1 and Figure 2The lower portion 169c of the through-silicon via 169 contacts a conductive pad 105c with a larger width W1, and the upper portion 169a of the through-silicon via 169 contacts a conductive pad 175d with a smaller width W2. Therefore, the through-silicon via 169 can be used to electrically connect a first semiconductor die 110 and a second semiconductor die 180 with different design rules.

[0130] In some embodiments, the upper portion 169a of the through-silicon via 169 is surrounded by a second masking layer 115, and the upper portion 169a of the through-silicon via 169 has a tapered profile that gradually tapers toward the bottleneck shape portion 169b of the through-silicon via 169. In other words, the widths of the upper portion 169a of the through-silicon via 169 gradually increase in a bottom-to-top direction. In some embodiments, the bottleneck shape portion 169b of the through-silicon via 169 is surrounded by a first masking layer 113 and an upper portion 111U of the silicon layer 111, and the widths of the bottleneck shape portion 169b of the through-silicon via 169 are substantially the same.

[0131] Furthermore, the lower portion 169c of the through-silicon via 169 is surrounded by the lower portion 111L of the silicon layer 111. In some embodiments, the lower portion 169c of the through-silicon via 169 has a plurality of rounded and convex upper corners C. In some embodiments, the lower portion 169c of the through-silicon via 169 is partially covered by the silicon layer 111. Additionally, the through-silicon via 169 has an upper surface 169T (i.e., the interface between the through-silicon via 169 and the conductive pad 175d in the second semiconductor die 180) and a lower surface 169B (i.e., the interface between the through-silicon via 169 and the conductive pad 105c in the first semiconductor die 110). In some embodiments, the lower surface 169B is larger than the upper surface 169T, and the upper surface 169T is larger than a cross-section of the through-silicon via 169, which lies between the upper surface 169T and the lower surface 169B and is parallel to the upper surface 169T and the lower surface 169B, such as the cross-section CS of the bottleneck-shaped portion 169B. That is, according to some embodiments, the lower width W3 of the through silicon via 169 is greater than the upper width W4 of the through silicon via 169.

[0132] Figure 3 A cross-sectional schematic diagram of an improved semiconductor device structure 200, illustrating some embodiments of the present disclosure, is shown, whereby semiconductor device structure 200 is another embodiment of semiconductor device structure 100. For the sake of consistency and clarity, while... Figure 1 and Figure 3 Similar components are labeled with the same component number.

[0133] Similar to semiconductor device structure 100, semiconductor device structure 200 has a through-silicon via 269 disposed in an exclusion region. The through-silicon via 269 has a conductive layer 267'; a barrier layer 265' disposed around the conductive layer 267'; and a pad layer 263' disposed around the barrier layer 265'. A difference between semiconductor device structures 100 and 200 also includes a protective layer 161'. Figure 3 As shown, according to some embodiments, each sidewall SW2 of the second masking layer 115, each sidewall SW1 of the first masking layer 113, and each upper sidewall USW of the silicon layer 111 are covered by a protective layer 161'.

[0134] Figure 4 Examples of some embodiments of this disclosure Figure 3 An enlarged schematic diagram. Figure 4 The image illustrates a silicon via 269, a protective layer 161', and its surroundings. In some embodiments, the silicon via 269 has an upper portion 269a, a lower portion 269c, and a bottleneck-shaped portion 269b, with the bottleneck-shaped portion 269b sandwiched between the upper portion 269a and the lower portion 269c. Dashed lines I-I' indicate the boundary between the upper portion 269a and the bottleneck-shaped portion 269b, while dashed lines II-II' indicate the boundary between the bottleneck-shaped portion 269b and the lower portion 269c.

[0135] In some embodiments, the upper portion 269a of the through-silicon via 269 is surrounded by a second masking layer 115, and the upper portion 269a of the through-silicon via 269 has a tapered profile that gradually tapers toward the bottleneck shape portion 269b of the through-silicon via 269. In other words, the widths of the upper portion 269a of the through-silicon via 269 gradually increase in a bottom-to-top direction. In some embodiments, the bottleneck shape portion 269b of the through-silicon via 269 is surrounded by a first masking layer 113 and an upper portion 111U of the silicon layer 111, and the widths of the bottleneck shape portion 269b of the through-silicon via 269 are substantially the same.

[0136] Furthermore, the lower portion 269c of the through-silicon via 269 is surrounded by the lower portion 111L of the silicon layer 111. In some embodiments, the lower portion 269c of the through-silicon via 269 has a plurality of rounded and convex corners C. In some embodiments, the lower portion 269c of the through-silicon via 269 is partially covered by the silicon layer 111. Additionally, the through-silicon via 269 has an upper surface 269T (i.e., the interface between the through-silicon via 269 and the conductive pad 175d in the second semiconductor die 180) and a lower surface 269B (i.e., the interface between the through-silicon via 269 and the conductive pad 105c in the first semiconductor die 110). In some embodiments, the lower surface 269B is larger than the upper surface 269T, and the upper surface 269T is larger than a cross-section of the through-silicon via 269 located between the upper surface 269T and the lower surface 269B, parallel to the upper surface 269T and the lower surface 269B, such as the cross-section CS of the bottleneck-shaped portion 269b. In some embodiments, the silicon via 269 has a lower width W5 (i.e., the lowest width of the lower portion 269c) and an upper width W6 (i.e., the highest width of the upper portion 269a), and the lower width W5 is greater than the upper width W4. Please refer to... Figure 3 and Figure 4 The lower portion 269c of the silicon through-hole 269 contacts a conductive pad 105c with a larger width W1, while the upper portion 269a of the silicon through-hole 269 contacts a conductive pad 175d with a smaller width W2. Therefore, the silicon through-hole 269 can be used to electrically connect a first semiconductor die 110 and a second semiconductor die 180 with different design specifications.

[0137] It should be understood that, according to some embodiments, the first masking layer 113, the second masking layer 115, and the upper portion 111U of the silicon layer 111 are separated from the through-silicon via 269 by a protective layer 161'. In some embodiments, the upper portion 269a and the bottleneck-shaped portion 269b of the through-silicon via 269 are surrounded by the protective layer 161'. In some embodiments, the lower portion 269c of the through-silicon via 269 directly contacts the lower portion 111L of the silicon layer 111.

[0138] Figure 5 The following is a schematic flowchart illustrating a method 10 for fabricating a semiconductor device structure (including semiconductor device structure 100 and modified semiconductor device structure 200) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27 and S29. Figure 5 These steps S11 to S29 are described in detail with reference to the following figures.

[0139] Figures 6 to 18 The illustrations show cross-sectional schematic diagrams of various intermediate stages during the formation of the semiconductor device structure 100, according to some embodiments of this disclosure. Figure 6As shown, according to some embodiments, a first semiconductor die 110 is provided having a semiconductor substrate 101, a dielectric layer 103, and conductive pads 105a, 105b, 105c, and a silicon layer 111 is formed on the first semiconductor die 110. Some steps are shown in... Figure 5 Step S11 in preparation method 10 shown.

[0140] The first semiconductor die 110 may be part of an integrated circuit (IC) chip having various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0141] Depending on the IC manufacturing stage, the first semiconductor die 110 may include various material layers (e.g., dielectric layers, semiconductor layers, and / or conductive layers) configured to form IC features (e.g., doped regions, insulating regions, gate features, source / drain features, interconnect features, other features, or combinations thereof). For clarity, the first semiconductor die 110 has been simplified. It should be understood that additional features may be added to the first semiconductor die 110, and some of the features described below may be replaced, modified, or excluded in other embodiments. In some embodiments, a silicon layer 111 is epitaxially grown on the first semiconductor die 110.

[0142] Next, as Figure 7 As shown, according to some embodiments, a first masking layer 113 is formed on a silicon layer 111, and a second masking layer 115 is formed on the first masking layer 113. Certain steps are shown in... Figure 5Step S13 of the fabrication method 10 shown. In some embodiments, the first mask layer 113 and the second mask layer 115 comprise dielectric materials, such as silicon oxide, silicon nitride, and silicon oxynitride, and their fabrication techniques include multiple deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin coating. Furthermore, according to some embodiments, a patterned mask 117 is formed on the second mask layer 115. In some embodiments, the patterned mask 117 has an opening 120 that exposes a portion of the second mask layer 115.

[0143] Next, as Figure 8 As shown, according to some embodiments, a second mask layer 115 is etched using a patterned mask 117 as a mask to form an opening 130 through the second mask layer 115. Individual steps are shown in... Figure 5 Step S15 of the fabrication method 10 shown. In some embodiments, a portion of the first masking layer 113 is exposed through an opening 130 in the second masking layer 115. The etching process may be a dry etching process, a wet etching process, or a combination thereof. After the etching process, the patterned masking layer 117 can be removed.

[0144] Then, as Figure 9 As shown, according to some embodiments, a first masking layer 113 is etched using a second masking layer 115 as a mask to form an opening 140 through the first masking layer 113. Individual steps are shown in... Figure 5 Step S17 of the fabrication method 10 shown. In some embodiments, a portion of the silicon layer 111 is exposed through an opening 140 in the first masking layer 113. The etching process may be a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the sidewalls of the opening 140 in the first masking layer 113 are substantially aligned with the sidewalls of the opening 130 in the second masking layer 115.

[0145] like Figure 10 As shown, according to some embodiments, after the openings 130 and 140 are formed, the silicon layer 111 is etched using a first mask layer 113 as a mask to form an opening 150 passing through the silicon layer 111. Individual steps are shown in... Figure 5 Step S19 in the preparation method 10 shown. The etching process can be a dry etching process, a wet etching process, or a combination thereof.

[0146] In some embodiments, the conductive pad 105c is exposed through the opening 150. In some embodiments, the second masking layer 115 comprises a material that has a high etch selectivity compared to the material of the first masking layer 113. Therefore, during the etching process for forming the opening 150 located in the silicon layer 111, the second masking layer 115 is etched to form an enlarged opening 130'.

[0147] In some embodiments, the enlarged opening 130' has a tapered profile that tapers towards the opening 140 located in the first masking layer 113. In some embodiments, the second masking layer 115 has a plurality of sloping sidewalls relative to the sidewalls of the first masking layer 113, and an angle θ between the sloping sidewalls of the second masking layer 115 and the lower surface. In some embodiments, the angle θ is in the range of approximately 46 degrees to approximately 60 degrees. The tapered sidewalls of the second masking layer 115 can provide improved step coverage to the subsequently formed protective layer 161.

[0148] Next, as Figure 11 As shown, according to some embodiments, a protective layer 161 is deposited on the second masking layer 115 and covers each sidewall of the second masking layer 115, each sidewall of the first masking layer 113, and each upper sidewall of the silicon layer 111 (i.e., each sidewall of the upper portion 111U of the silicon layer 111). Individual steps are shown in... Figure 5 Step S21 in the fabrication method 10 shown. It should be understood that the lower sidewalls of the silicon layer 111 (i.e., the lower portion 111L of the silicon layer 111) are not covered by the protective layer 161.

[0149] Figure 11 The dashed lines are used to illustrate the boundary between the upper portion 111U and the lower portion 111L of the silicon layer 111. In some embodiments, the protective layer 161 is fabricated using a non-conformal deposition process, such as a non-conformal liner atomic layer deposition (NOLA) process. In some embodiments, the protective layer 161 comprises an oxide material, such as aluminum oxide.

[0150] Then, as Figure 12 As shown, according to some embodiments, the silicon layer 111 is etched by using a protective layer 161 as a mask. Individual steps are shown in... Figure 5 Step S23 in the fabrication method 10 shown. In some embodiments, the lower portion 111L of the silicon layer 111 is etched laterally, while the upper portion 111U of the silicon layer 111 remains intact because it is shielded by the protective layer 161.

[0151] In some embodiments, the upper portion 111U of the silicon layer 111 is under-cut by an etching process used to form the enlarged opening 150'. In some embodiments, the fabrication technique for the enlarged opening 150' may include an isotropic etching process. The isotropic etching process may be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, an etching solution comprising nitric acid (HNO3) and hydrofluoric acid (HF) is used to form the enlarged opening 150'. In some embodiments, the etching solution further comprises phosphoric acid (H3PO4). In other embodiments, fluorine-based plasma is used to form the enlarged opening 150'.

[0152] like Figure 13 As shown, according to some embodiments, after the enlarged opening 150' is formed, the protective layer 161 is removed. Individual steps are shown in... Figure 5 Step S25 of the preparation method 10 shown. The protective layer 161 can be removed by a wet etching process, a dry etching process, or a combination thereof. In some embodiments, an etching solution containing phosphoric acid (H3PO4) can be used to remove the protective layer 161.

[0153] Next, as Figure 14 As shown, according to some embodiments, a pad material 163 is formed on the second masking layer 115 and covers the sidewalls of the openings 130', 140', 150', and the lower surface. In other words, the inclined sidewalls of the second masking layer 115, the sidewalls of the first masking layer 113, the sidewalls of the silicon layer 111, and the exposed surface of the conductive pad 105c are covered by the pad material 163.

[0154] The liner material 163 is conformally deposited in Figure 13 Structurally, the pad material 163 serves to separate the subsequently formed plurality of conductive layers from the silicon layer 111. In some embodiments, the pad material 163 comprises silicon oxide, tetraethylorthosilicate (TEOS) oxide, silicon nitride, polyimide, other applicable dielectric materials, or combinations thereof. Furthermore, the fabrication technique of the pad material 163 may include a thermal oxidation process, a CVD process, a PVD process, or other applicable deposition processes.

[0155] Then, as Figure 15As shown, according to some embodiments, an anisotropic etching process is performed on the pad material 163 to vertically remove the same amount of pad material 163 at all locations, leaving a pad layer 163' on each sidewall of the openings 130', 140, and 150. The anisotropic etching process on the pad material 163 can be a dry etching process. According to some embodiments, after the anisotropic etching process is performed, the conductive pad 105c is exposed through the openings 150', 140, and 130'.

[0156] Next, as Figure 16 As shown, according to some embodiments, a barrier material 165 is formed on the second masking layer 115 and the pad layer 163'. In some embodiments, the exposed surface of the conductive pad 105c is not covered by the barrier material 165. The barrier material 165 acts as a diffusion barrier to prevent metal diffusion, and also serves as an adhesive layer between the pad layer 163' and the subsequently formed conductive material. In some embodiments, the barrier material 165 comprises TaN, Ta, Ti, TiN, TiSiN, WN, CoW, or combinations thereof. The fabrication technique of the barrier material 165 may include a CVD process, a PVD process, a sputtering process, or other applicable processes.

[0157] Then, as Figure 17 As shown, according to some embodiments, a conductive material 167 is formed on the barrier material 165. In some embodiments, the remaining portions of the openings 130', 140, 150' are filled with the conductive material 167. Prior to the formation of the conductive material 167, a seed layer (not shown) may be formed on the barrier material 165.

[0158] The seed layer may be a copper seed layer, and its fabrication technology may include a CVD process, a PVD process, a sputtering process, a plating process, or other applicable processes. In some embodiments, the conductive material 167 comprises a low-resistivity conductive material, such as copper (Cu). In some other embodiments, the conductive material 167 comprises tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), combinations thereof, or other applicable conductive materials. The fabrication technology of the conductive material 167 may include a CVD process, a PVD process, a sputtering process, a plating process, or other applicable processes.

[0159] Please refer to Figure 18According to some embodiments, after the conductive material 167 is formed, a planarization process is performed on the conductive material 167 and the barrier material 165 to form a silicon through-hole 169, and the silicon through-hole 169 includes a pad layer 163', a barrier layer 165', and a conductive layer 167'. The bottle carbonization process may include a chemical mechanical polishing (CMP) process, which removes excess portions of the conductive material 167 and the barrier material 165 on the second masking layer 115. Individual steps are shown in... Figure 5 Step S27 in preparation method 10 shown.

[0160] Next, as Figure 1 As shown, according to some embodiments, a second semiconductor die 180 is formed on a second masking layer 115. Individual steps are shown in... Figure 5 Step S29 of the fabrication method 10 shown. In some embodiments, the second semiconductor die 180 is bonded to... Figure 17 The structure is configured such that conductive pads 175a, 175b, 175c, 175d, and 175e face the silicon via 169. After the second semiconductor die 180 is formed, a semiconductor device structure 100 is obtained.

[0161] Similar to the first semiconductor die 110, the second semiconductor die 180 may be part of an IC chip, comprising various passive and active microelectronic components, and the second semiconductor die 180 may include various material layers configured to form multiple IC features. In some embodiments, a through-silicon via 169 electrically connects the conductive pad 105c of the first semiconductor die 110 to the conductive pad 175d of the second semiconductor die 180. Because the second semiconductor die 180 is formed after the through-silicon via 169, the risk of damage to the conductive pads 175a, 175b, 175c, 175d, and 175e in the second semiconductor die 180 can be reduced during the process used to form the through-silicon via 169.

[0162] Figures 19 to 23 The diagram illustrates cross-sectional views of various intermediate stages during the formation of a semiconductor device structure 200, representing some embodiments of this disclosure. Figure 19 As shown, according to some embodiments, after etching the silicon layer 111 by using the protective layer 161 as a mask (i.e., Figure 12 In the next step, a liner material 263 is formed on the protective layer 161. Some materials and processes used to form the liner material 263 are similar to or identical to those used to form... Figure 14 The materials and processes of the padding material 163 are described, and their detailed descriptions will not be repeated in this document.

[0163] Next, as Figure 20As shown, according to some embodiments, an anisotropic etching process is performed on the pad material 263 to vertically remove the same amount of pad material 263 at all locations, leaving a pad layer 263' on each sidewall of the openings 130', 140, and 150'. The anisotropic etching process performed on the pad material 263 can be a dry etching process. According to some embodiments, after the anisotropic etching process is performed, the conductive pad 105c is exposed through the openings 150', 140, and 130'.

[0164] Next, as Figure 21 As shown, according to some embodiments, a barrier material 265 is formed on the protective layer 161 and the padding layer 263'. Some materials and processes used to form the barrier material 265 are similar to or the same as those used to form... Figure 16 The details of the materials and processes used in the barrier material 165 will not be repeated here.

[0165] Then, as Figure 22 As shown, according to some embodiments, a conductive material 267 is formed on a barrier material 265. In some embodiments, the remaining portions of the openings 130', 140, 150' are filled with the conductive material 267. Prior to the formation of the conductive material 267, a seed layer (not shown) may be formed on the barrier material 265. Some materials and processes used to form the conductive material 267 are similar to or the same as those used to form... Figure 17 The materials and processes of the conductive material 167 are described in detail, and will not be repeated here.

[0166] like Figure 23 As shown, according to some embodiments, after the conductive material 267 is formed, a planarization process is performed on the conductive material 267, the barrier material 265, and the protective layer 161 to form a residual portion of the through-silicon via 269 and the protective layer 161'. The through-silicon via 269 includes a pad layer 263', a barrier layer 265', and a conductive layer 267'. The planarization process may include a CMP process that removes the excess portions of the conductive material 267, the barrier material 265, and the protective layer 161 on the second masking layer 115.

[0167] Next, as Figure 3 As shown, according to some embodiments, a second semiconductor die 180 is formed on the second masking layer 115. In some embodiments, the second semiconductor die 180 is bonded to... Figure 23 The structure is configured such that conductive pads 175a, 175b, 175c, 175d, and 175e face the silicon via 269. In some embodiments, the protective layer 161' directly contacts the second semiconductor die 180. After the second semiconductor die 180 is formed, a semiconductor device structure 200 is obtained.

[0168] In some embodiments, the through-silicon via 269 electrically connects the conductive pad 105c of the first semiconductor die 110 to the conductive pad 175d of the second semiconductor die 180. Since the second semiconductor die 180 is formed after the through-silicon via 169, the risk of damage to the conductive pads 175a, 175b, 175c, 175d, and 175e in the second semiconductor die 180 can be reduced during the process used to form the through-silicon via 169.

[0169] This disclosure provides some embodiments of semiconductor device structures 100 and 200. In some embodiments, through-silicon vias 169 and 269 are formed through a silicon layer 111, a first masking layer 113, and a second masking layer 115 to electrically connect a first semiconductor die 110 and a second semiconductor die 180 in a vertical direction. The through-silicon vias 169 and 269 have a bottle-shaped profile. For example, the lower surface 169B of the through-silicon via 169 is larger than the upper surface 169T of the through-silicon via 169, and the upper surface 169T of the through-silicon via 169 is larger than a cross-section (e.g., cross-section CS) of the through-silicon via 169, which lies between the upper surface 169T and the lower surface 169B of the through-silicon via 169, and is parallel to the upper surface 169T and the lower surface 169B of the through-silicon via 169. Therefore, silicon through-holes 169 and 269 can be used to electrically connect a first semiconductor die 110 and a second semiconductor die 180 with different design rules (e.g., different pattern densities or different critical sizes). As a result, functional density (i.e., the number of interconnected devices per unit chip area) can be increased, providing several benefits such as improved manufacturing efficiency, reduced costs, and improved performance.

[0170] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a silicon layer disposed on a first semiconductor die; and a first masking layer disposed on the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed on the first masking layer; and a silicon via (SVR) passing through the silicon layer and the first masking layer. A lower surface of the SVR is larger than an upper surface of the SVR, and the upper surface of the SVR is larger than a cross-section of the SVR located between the lower and upper surfaces of the SVR, and the cross-section is parallel to the lower and upper surfaces of the SVR.

[0171] Another embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a silicon layer disposed on a first semiconductor die; and a first masking layer disposed on the silicon layer. The semiconductor device structure also includes a second masking layer disposed on the first masking layer; and a second semiconductor die disposed on the second masking layer. The semiconductor device structure further includes a through-silicon via (TSV) passing through the silicon layer, the first masking layer, and the second masking layer to electrically connect the first semiconductor die and the second semiconductor die. The TSV has a bottle-shaped portion surrounded by the first masking layer and an upper portion of the silicon layer, and the interface area between the TSV and the first semiconductor die is larger than the interface area between the TSV and the second semiconductor die.

[0172] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a silicon layer on a first semiconductor die; and forming a first masking layer on the silicon layer. The method also includes forming a first opening through the first masking layer, and forming a second opening through the silicon layer; and depositing a protective layer on the first masking layer. The protective layer extends to cover a sidewall of the first masking layer and an upper sidewall of the silicon layer. The method further includes using the protective layer as a mask to etch the silicon layer, thereby undercutting an upper portion of the layer to form an enlarged second opening. Furthermore, the method includes filling the first opening and the enlarged second opening with a silicon via; and forming a second semiconductor die on the silicon via.

[0173] The silicon in these embodiments of the present disclosure has several advantageous features. By forming a silicon through-hole with a bottle-shaped profile, the silicon through-hole can be used to electrically connect two semiconductor dies (or semiconductor wafers) with different design rules in the vertical direction. This can improve production efficiency, reduce costs, and improve performance.

[0174] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0175] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor device structure, comprising: A silicon layer is disposed on a first semiconductor die; A first masking layer is disposed on the silicon layer; A second semiconductor die is disposed on the first masking layer; as well as A silicon via (SVR) passes through the silicon layer and the first masking layer, wherein a lower surface of the SVR is larger than an upper surface of the SVR, and the upper surface of the SVR is larger than a cross-section of the SVR located between the lower and upper surfaces of the SVR, and the cross-section is parallel to the lower and upper surfaces of the SVR. The silicon via directly contacts a first conductive pad in the first semiconductor die and a second conductive pad in the second semiconductor die.

2. The semiconductor device structure as described in claim 1, further comprising: A third conductive pad is disposed in the first semiconductor die and adjacent to the first conductive pad; as well as A fourth conductive pad is disposed in the second semiconductor die and adjacent to the second conductive pad, wherein the lateral distance between the third conductive pad and the first conductive pad in the first semiconductor die is greater than the lateral distance between the fourth conductive pad and the second conductive pad in the second semiconductor die.

3. The semiconductor device structure as described in claim 1, further comprising a second masking layer disposed between the first masking layer and the second semiconductor die, wherein, The silicon via passes through the second masking layer, and the first masking layer and the second masking layer contain different materials.

4. The semiconductor device structure of claim 3, wherein one sidewall of the second masking layer is inclined relative to one sidewall of the first masking layer.

5. The semiconductor device structure of claim 4, further comprising a protective layer covering the sidewall of the second masking layer, the sidewall of the first masking layer, and an upper sidewall of the silicon layer, wherein, The upper sidewall of the silicon layer is generally aligned with the sidewall of the first masking layer.

6. The semiconductor device structure of claim 1, wherein the through-silicon via comprises: A conductive layer; A barrier layer covers each sidewall and a lower surface of the conductive layer, wherein the barrier layer directly contacts the first semiconductor die; as well as A liner layer covers each sidewall of the barrier layer.

7. A semiconductor device structure, comprising: A silicon layer is disposed on a first semiconductor die; A first masking layer is disposed on the silicon layer; A second masking layer is disposed on the first masking layer; A second semiconductor die is disposed on the second masking layer; as well as A silicon via (SVR) passes through the silicon layer, the first masking layer, and the second masking layer to electrically connect the first semiconductor die and the second semiconductor die. The SVR has a bottle-shaped portion surrounded by the first masking layer and an upper portion of the silicon layer. The interface area between the SVR and the first semiconductor die is larger than the interface area between the SVR and the second semiconductor die. The silicon via directly contacts a first conductive pad in the first semiconductor die and a second conductive pad in the second semiconductor die.

8. The semiconductor device structure of claim 7, wherein the first semiconductor die has a first critical size and the second semiconductor die has a second critical size, and the first critical size is greater than the second critical size.

9. The semiconductor device structure of claim 7, wherein the through-silicon via further comprises: The upper part is surrounded by the second masking layer; as well as The lower part is surrounded by the lower part of the silicon layer; The bottle-shaped portion of the silicon perforation is sandwiched between the upper and lower portions of the silicon perforation, and the upper portion of the silicon perforation has a tapered profile that gradually tapers toward the bottle-shaped portion of the silicon perforation.

10. The semiconductor device structure of claim 9, wherein the lower portion of the silicon via has a plurality of rounded and convex corners.

11. The semiconductor device structure of claim 9, wherein the bottle-shaped portion and the upper portion of the silicon via are separated from the first masking layer, the second masking layer and the upper portion of the silicon layer by a protective layer.

12. The semiconductor device structure of claim 11, wherein the lower portion of the silicon via directly contacts the lower portion of the silicon layer.

13. The semiconductor device structure of claim 11, wherein the protective layer comprises aluminum oxide.

14. A method for fabricating a semiconductor device, comprising: A silicon layer is formed on a first semiconductor die; A first masking layer is formed on the silicon layer; A first opening is formed to pass through the first mask layer, and a second opening is formed to pass through the silicon layer; A protective layer is deposited on the first masking layer, wherein the protective layer extends to cover one sidewall of the first masking layer and one upper sidewall of the silicon layer; By using the protective layer as a mask to etch the silicon layer, and then undercutting the upper part of the silicon layer, an enlarged second opening is formed; The first opening and the enlarged second opening are filled with a silicon through-hole; and A second semiconductor grain is formed on the silicon via. The silicon via directly contacts a first conductive pad in the first semiconductor die and a second conductive pad in the second semiconductor die.

15. The method for fabricating a semiconductor device as described in claim 14, further comprising: A second masking layer is formed on top of the first masking layer; as well as Before the first opening through the first mask is formed, a third opening is formed to pass through the second mask layer.

16. The method of fabricating a semiconductor element as claimed in claim 15, wherein during the formation of the second opening through the silicon layer, the second mask layer is etched to form an enlarged third opening, and the enlarged third opening has a tapered profile that tapers towards the first opening.

17. The method for fabricating a semiconductor device as described in claim 14, wherein the fabrication technique of the protective layer includes a non-conformal deposition process.

18. The method for fabricating a semiconductor element as claimed in claim 14, further comprising removing the protective layer prior to the formation of the silicon through-hole.

19. The method for fabricating a semiconductor element as claimed in claim 14, wherein the upper portion of the silicon layer covers the lower portion of the silicon via.

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