Integrated circuit and method of manufacturing the same

Abstract

Embodiments of the present application relate to an integrated circuit and a method of manufacturing the same. The integrated circuit includes a first circuit having m first cells coupled in parallel, any first cell including one or more first transistors coupled in series, and a second circuit having n second cells coupled in parallel, any second cell including one or more second transistors coupled in series. Gate terminals of the first circuit are coupled to gate terminals of the second circuit. m and n are different positive integers.

Description

Technical Field

[0001] This application relates to an integrated circuit and a method for manufacturing the same. Background Technology

[0002] Integrated circuit design in deep submicron processes (e.g., 16nm, 7nm, 5nm and above) faces several challenges and limitations. For example, specific bottlenecks emerge in the fabrication of circuits containing microelectronic components such as deep submicron transistors, amplifiers, and current mirrors. These challenges and limitations will become even more critical for advanced IC manufacturing processes as process scale continues to advance. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an integrated circuit is provided, comprising: a first circuit including m parallel-coupled first units, each first unit including one or more series-coupled first transistors; and a second circuit including n parallel-coupled second units, each second unit including one or more series-coupled second transistors; wherein the gate terminal of the first circuit is coupled to the gate terminal of the second circuit, and m and n are different positive integers.

[0004] According to another aspect of the embodiments of this application, an integrated circuit is provided, comprising: a first stacked gate circuit including a plurality of first transistors having gate terminals, the gate terminals of the first transistors being coupled to each other; and a second stacked gate circuit coupled to the first stacked gate circuit, the second stacked gate circuit including a plurality of second transistors having gate terminals, the gate terminals of the second transistors being coupled to each other; wherein the threshold voltage of the first transistors is greater than the threshold voltage of the second transistors.

[0005] According to another aspect of the embodiments of this application, a method for manufacturing an integrated circuit is provided, comprising: arranging a plurality of first transistors into m first units by series coupling one or more first transistors into any one of the first units; coupling the first units in parallel into a first circuit; arranging a plurality of second transistors into n second units by series coupling one or more second transistors into any one of the second units, wherein m and n are different positive integers; coupling the second units in parallel into a second circuit; and coupling the second circuit to the first circuit. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0007] Figure 1This is a schematic diagram illustrating an integrated circuit according to some embodiments of the present disclosure.

[0008] Figure 2A and Figure 2B These are schematic diagrams illustrating equivalent stacked gate transistors using n-channel metal-oxide-semiconductor field-effect transistor (n-MOSFET or NMOS) components and equivalent stacked gate transistors using p-channel metal-oxide-semiconductor field-effect transistor (p-MOSFET or PMOS) components, respectively, according to some embodiments of the present disclosure.

[0009] Figure 3 This is a schematic diagram illustrating the relationship between the percentage of current mismatch exceeding one standard deviation and the number of stacked transistor stages according to some embodiments of the present disclosure.

[0010] Figure 4 This is a schematic diagram illustrating an equivalent stacked gate transistor using an n-MOSFET component according to some embodiments of the present disclosure.

[0011] Figure 5A This is a schematic diagram illustrating an integrated circuit according to some embodiments of the present disclosure.

[0012] Figure 5B This illustrates some embodiments according to the present disclosure. Figure 5A A schematic diagram of the equivalent circuit of an integrated circuit in the image.

[0013] Figure 5C This is a schematic diagram illustrating an integrated circuit according to some embodiments of the present disclosure.

[0014] Figure 5D This illustrates some embodiments according to the present disclosure. Figure 5C A schematic diagram of the equivalent circuit of an integrated circuit in the image.

[0015] Figure 6 This is a schematic diagram illustrating a stacked gate circuit according to some embodiments of the present disclosure.

[0016] Figure 7 and Figure 8 This is a diagram illustrating two different exemplary arrangements of a stacked gate circuit according to some embodiments of the present disclosure.

[0017] Figure 9 This is a diagram illustrating a stacked gate circuit according to some embodiments of the present disclosure.

[0018] Figure 10 and Figure 11 This is a diagram illustrating two exemplary arrangements of a stacked gate circuit according to some embodiments of the present disclosure.

[0019] Figure 12AThis is a schematic diagram illustrating an integrated circuit using NMOS according to some embodiments of the present disclosure.

[0020] Figure 12B This illustrates some embodiments according to the present disclosure. Figure 12A A schematic diagram of the equivalent circuit of an integrated circuit in the image.

[0021] Figure 12C This is a schematic diagram illustrating an integrated circuit using NMOS according to some embodiments of the present disclosure.

[0022] Figure 12D This illustrates some embodiments according to the present disclosure. Figure 12C A schematic diagram of the equivalent circuit of an integrated circuit in the image.

[0023] Figure 13 This is a schematic diagram illustrating a stacked gate circuit using NMOS according to some embodiments of the present disclosure.

[0024] Figure 14 This is a flowchart illustrating a method for manufacturing an integrated circuit according to some embodiments of the present disclosure.

[0025] Figure 15 This is a flowchart illustrating a method for manufacturing an integrated circuit according to some embodiments of the present disclosure. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. These are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely exemplary and is in no way intended to limit the scope or meaning of the invention or any typical terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0028] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0029] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0030] In this document, the term “coupling” may also be referred to as “electrical coupling”, and the term “connection” may be referred to as “electrical connection”. “Coupling” and “connection” may also be used to indicate that two or more elements cooperate or interact with each other.

[0031] As integrated circuit (IC) manufacturing processes scale down (e.g., 32nm, 20nm, 16nm, 7nm, 5nm, or higher), the parameters of electronic components (e.g., transistors) are limited in size. Therefore, metal-oxide-semiconductor field-effect transistors (MOSFETs) with long channel lengths are no longer feasible in advanced processes. However, in some analog circuit designs, MOSFETs with long channel lengths are still needed to improve MOSFET performance / characteristics, such as improving output resistance (Rout) or current mismatch performance within current mirror circuits.

[0032] In some embodiments of this disclosure, multi-stage transistors (e.g., MOSFETs) with short channel lengths can be stacked together to form an equivalent transistor with a long channel length. Reference Figure 1 This is a schematic diagram illustrating an integrated circuit 100 according to some embodiments of the present disclosure. For example... Figure 1 As shown, integrated circuit 100 is a current mirror circuit that includes two or more current mirror branches. A reference current can be determined by an active device (e.g., a current source) in one of the current mirror branches. The current mirror circuit is used to generate a current of the same magnitude mirrored from the reference current in the other mirror branches.

[0033] For example, Figure 1The integrated circuit 100 shown includes three current mirror branches 110, 120, and 130. Current mirror branch 110 includes multiple transistors T1_1-T1_40. Current mirror branch 120 includes multiple transistors T2_1-T2_40. Current mirror branch 130 includes multiple transistors T3_1-T3_40.

[0034] like Figure 1 As shown, the reference current Iref is determined by the current source 132 on the current mirror branch 130. The integrated circuit 100 is configured to copy or mirror the current from the current mirror branch 130 to the current mirror branches 110 and 120 to generate a first current Idl through the current mirror branch 110 and a second current Id2 through the current mirror branch 120, thereby driving the loads 112 and 122 connected to the current mirror branches 110 and 120, respectively.

[0035] Ideally, both the first current Idl and the second current Id2 should be equal to the reference current Iref. However, due to process variations, the characteristics (e.g., channel length, device size, threshold voltage, etc.) of the transistors in different current mirror branches 110, 120, and 130 are not entirely identical. Therefore, there is a current mismatch between the reference current Iref in current mirror branch 130, the first current Idl in current mirror branch 110, and the second current Id2 in current mirror branch 120.

[0036] In particular, in analog circuit operation, a portion of the current mismatch in the current mirror is due to unequal threshold voltages. In some cases, it may be necessary to implement a transistor with a long channel length in the current mirror branch to reduce current mismatch. However, transistors with long channel lengths are not suitable for advanced processes (e.g., 32nm, 20nm, 16nm, 7nm, 5nm or higher).

[0037] In some embodiments of this disclosure, the current mirror branch 110 includes transistors T1_1-T1_40. Transistors T1_1-T1_40 are connected in series between the first terminal and the second terminal, and their respective gates are connected together. For example... Figure 1 As shown, the first transistors T1_1-T1_40 can be p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs or PMOS), the first terminal is the positive power supply voltage terminal Vdd, and the second terminal is the system ground terminal GND, but the present invention is not limited thereto. In some embodiments, the first transistors T1_1-T1_40 can be n-channel metal-oxide-semiconductor field-effect transistors (n-MOSFETs or NMOS).

[0038] exist Figure 1In the embodiments, each of the current mirror branches 110, 120, and 130 includes 40 stages of transistors (e.g., transistors T1_1-T1_40 in current mirror branch 110, transistors T2_1-T2_40 in current mirror branch 120, and transistors T3_1-T3_40 in current mirror branch 130), but this disclosure is not limited thereto. For example, in current mirror branch 110, one end of the first-stage transistor T1_1 (e.g., the source terminal) is connected to the positive power supply voltage terminal Vdd, and the other end of transistor T1_1 (e.g., the drain terminal) is connected to one end of the second-stage transistor T1_2 (e.g., the source terminal). The other end of the second-stage transistor T1_2 (e.g., the drain terminal) is connected to one end of the third-stage transistor T1_3 (e.g., the source terminal), and so on. At least one end (e.g., the source terminal) of the 40th-level transistor T1_40 is connected to one end (e.g., the drain terminal) of the 39th-level transistor T1_39, and the other end (e.g., the drain terminal) of the 40th-level transistor T1_40 is connected to the system ground terminal GND. Furthermore, the control terminals (e.g., the gate terminals) of transistors T1_1-T1_40 can be controlled by a bias voltage Vbias. Based on the connections between transistors T1_1-T1_40, the gate stacked transistors T1_1-T1_40 can form an equivalent single transistor. In some embodiments, transistors T1_1-T1_40 with shorter channel lengths (e.g., approximately 0.1 μm each) are equivalent to a single transistor with a longer channel length (e.g., approximately 4 μm).

[0039] Similarly, current mirror branch 120 includes 40 stages of transistors T2_1-T2_40. Transistors T2_1-T2_40 are connected in series between the positive power supply voltage terminal Vdd and the system ground terminal GND. The gates of transistors T2_1-T2_40 are connected together and controlled by a bias voltage Vbias. Current mirror branch 130 also includes 40 stages of transistors T3_1-T3_40. The details of the gate stacking structure of current mirror branch 130 are similar to those of current mirror branches 110 and 120, and will not be repeated here for simplicity. Based on the connections between transistors T2_1-T2_40 and T3_1-T3_40, transistors T2_1-T2_40 are equivalent to a single transistor in current mirror branch 120, and transistors T3_1-T3_40 are equivalent to a single transistor in current mirror branch 130. In some embodiments, transistors T2_1-T2_40 or T3_1-T3_40 with shorter channel lengths are equivalent to a single transistor with a longer channel length in the corresponding current mirror branch. However, each current mirror branch 110, 120, or 130 is not limited to including 40 stages of transistors. In some embodiments, each current mirror branch includes N stages of transistors, where N is a positive integer. Furthermore, in some embodiments, depending on the number of loads, the integrated circuit 100 may include two or more current mirror branches, and is not limited to including three current mirror branches 110, 120, and 130.

[0040] refer to Figure 2A and Figure 2B This is a schematic diagram illustrating, respectively, an equivalent stacked gate transistor 200a using an n-MOSFET component and an equivalent stacked gate transistor 200b using a p-MOSFET component according to some embodiments of the present disclosure. Figure 2A As shown, the gate terminal of the stacked gate transistor 200a is coupled to the gate terminal of the n-MOSFET devices 210a-210n, the drain terminal of the stacked gate transistor 200a is coupled to the drain terminal of the first-stage n-MOSFET device 210a, and the source terminal of the stacked gate transistor 200a is coupled to the source terminal of the Nth-stage n-MOSFET device 210n. The n-MOSFET devices 210a-210n are series-coupled. Figure 2B As shown, the gate terminal of the stacked gate transistor 200b is coupled to the gate terminals of the p-MOSFET devices 220a-220n, the source terminal of the stacked gate transistor 200a is coupled to the source terminal of the first-stage p-MOSFET device 220a, and the drain terminal of the stacked gate transistor 200a is coupled to the drain terminal of the Nth-stage p-MOSFET device 220n. The p-MOSFET devices 220a-220n are connected in series.

[0041] refer to Figure 3This is a schematic diagram illustrating simulation results showing the relationship between the percentage of current mismatch exceeding one standard deviation and the number of stages of stacked transistors according to some embodiments of the present disclosure. For current mirror circuits with different numbers of stages, it can be performed at a bias current (e.g., about 20 µA). Figure 3 The simulation shown. (As illustrated) Figure 3 As shown, the mismatch of the current mirror is related to the number of current mirror stages. As the number of stacked gates increases, the mismatch of the current mirror circuit decreases accordingly.

[0042] By stacking multiple transistors (e.g., Figure 2A n-MOSFET devices 210a-210n or Figure 2B The p-MOSFET devices (220a-220n) in the series each have a specific channel length allowed in advanced processes, enabling the realization of equivalent transistors with long channel lengths (e.g., Figure 2A Transistor 200a or Figure 2B Transistor 200b in the circuit is used to meet the desired performance or characteristics of the circuit (e.g., current mismatch). See again... Figure 1 Based on the gate stack structure, the current mirror branches 110, 120 and 130 each include an equivalent transistor with a long channel length, which can reduce the mismatch between the reference current Iref, the first current Id1 and the second current Id2.

[0043] refer to Figure 4 This is a schematic diagram illustrating an equivalent stacked gate transistor 400 using n-MOSFET components according to some embodiments of the present disclosure. Figure 4As shown, in some embodiments, the equivalent stacked gate transistor 400 may include multiple units 410, 420, 430, and 440 of a stacked gate circuit coupled in parallel. For example, unit 410 includes transistors 411, 413, 415, 417, and 419 coupled in series. Unit 420 includes transistors 421, 423, 425, 427, and 429 coupled in series. Unit 430 includes transistors 431, 433, 435, 437, and 439 coupled in series. Unit 440 includes transistors 441, 443, 445, 447, and 449 coupled in series. The gate terminals of transistors 411-419, 421-429, 431-439, and 441-449 are coupled together to a control terminal G (e.g., a gate terminal) of the stacked gate transistor 400 to receive a bias voltage. The drain terminals of the first-stage transistors 411, 421, 431, and 441 in units 410, 420, 430, and 440 are coupled together to the drain terminal D of the stacked gate transistor 400. The source terminals of the last-stage transistors 419, 429, 439, and 449 in units 410, 420, 430, and 440 are coupled together to the source terminal S of the stacked gate transistor 400. In some embodiments, the transistor 400 formed by four transistor units connected in parallel is referred to as a "plural" stacked gate circuit with a value of 4.

[0044] In some embodiments, each of units 410, 420, 430, or 440 is not limited to including, for example, Figure 4 The diagram shows a five-stage series transistor. In some embodiments, each unit may include one or more stages of transistors. Furthermore, in some embodiments, the stacked gate transistor 400 may include one or more units, depending on the value of its "multiple" and is not limited to including four units 410, 420, 430, and 440.

[0045] refer to Figure 5A and Figure 5B . Figure 5A This is a schematic diagram illustrating an integrated circuit 500a according to some embodiments of the present disclosure. For example... Figure 5A As shown, integrated circuit 500a has two branches 510a and 520a. Transistors MA1-MAN in branch 510a and transistors MB1-MBN in branch 520a have the same multiple values ​​(e.g., multiple values ​​of 4). In some embodiments, transistors MA1-MA4 and MB1-MB4 in region 530a adjacent to the source side (e.g., the side near the positive power supply voltage terminal Vdd) operate as source negative feedback resistors in the linear region. Figure 5B This illustrates some embodiments according to the present disclosure. Figure 5A A schematic diagram of the equivalent circuit 500b of integrated circuit 500a in the diagram. (See attached diagram.) Figure 5BAs shown, transistors MA1-MA4 and MB1-MB4 can be represented by their corresponding equivalent resistors.

[0046] In some embodiments, since transistors MA1-MA4 and MB1-MB4 operating in the linear region have little effect on the current mismatch between currents Id1 and Id2, the "multiple" values ​​of transistors MA1-MA4 and MB1-MB4 in region 530a can be reduced. By reducing the number of parallel transistors MA1-MAN and MB1-MBN cells, the area of ​​integrated circuit 500a can be reduced without sacrificing current mismatch performance.

[0047] refer to Figure 5C and Figure 5D . Figure 5C This is a schematic diagram illustrating an integrated circuit 500c according to some embodiments of the present disclosure. Figure 5D This illustrates some embodiments according to the present disclosure. Figure 5C A schematic diagram of the equivalent circuit 500d of integrated circuit 500c in the diagram. (And...) Figure 5A Compared to the 500a integrated circuit in the middle, such as Figure 5C As shown, each branch in integrated circuit 500c includes two regions 530c and 540c. Region 530c is adjacent to the source side (e.g., the side near the positive power supply voltage terminal Vdd), and region 540c is adjacent to the drain side (e.g., the side near the system ground).

[0048] like Figure 5C As shown, the transistors in region 530c (e.g., MA1, MA2, MB1, and MB2) have a first plurality of values ​​(e.g., a plurality of values ​​of 2), and the transistors in region 540c have a second plurality of values ​​larger than the first plurality of values ​​(e.g., a plurality of values ​​of 4). Figure 5D As shown, since the transistors in region 530c operate in the linear region as source negative feedback resistors, transistors MA1, MA2, MB1, and MB2 can be represented by their respective equivalent resistors.

[0049] Generally speaking, Figure 5B Equivalent circuit 500b and Figure 5D The total resistance of the equivalent circuit 500d is similar. In other words, in integrated circuit 500c, although the values ​​of multiple transistors in region 530c are reduced to 2, the resulting source negative feedback resistance is similar to that of integrated circuit 500a with multiple values ​​of 4. Therefore, integrated circuit 500c can achieve similar current mismatch performance with a smaller circuit area.

[0050] refer to Figure 6 This is a schematic diagram illustrating a stacked gate circuit 600 using PMOS according to some embodiments of the present disclosure. Figure 6 As shown, the stacked gate circuit 600 includes a first-stage circuit 610 and a second-stage circuit 620.

[0051] The second-stage circuit 620 is coupled to the first-stage circuit 610. Specifically, the gate terminal of the first-stage circuit 610 is coupled to the gate terminal of the second-stage circuit 620 to form the control terminal G of the stacked gate circuit 600. The drain terminal of the first-stage circuit 610 is coupled to the source terminal of the second-stage circuit 620. The source terminal of the first-stage circuit 610 can be configured as the source terminal S of the stacked gate circuit 600. The drain terminal of the second-stage circuit 620 can be configured as the drain terminal D of the stacked gate circuit 600.

[0052] In some embodiments, the first-stage circuit 610 includes m parallel-coupled units, each unit including one or more transistors coupled in series. For example, the first-stage circuit 610 may include 24 units (e.g., multiple values ​​of 24) and 16 stages of transistors, their respective gates coupled together. The second-stage circuit 620 includes n parallel-coupled units, each unit including one or more transistors coupled in series. Again, for example, the second-stage circuit 620 may include 42 units (e.g., multiple values ​​of 42) and 24 stages of transistors, their respective gates coupled together. As mentioned above, m and n are different positive integers. In some embodiments, m can be any positive integer less than n to reduce the circuit area of ​​the first-stage circuit 610.

[0053] By arranging different numbers of transistor cells (e.g., different multiple values) in different stages of the stacked gate circuit 600, the total area required for the circuit can be reduced without degrading circuit performance. Therefore, similar current mismatch characteristics can be achieved in relatively small integrated circuits. In some embodiments, simulations show that replacing a 43-stage circuit with multiple values ​​of 42 in all stages with a stacked gate circuit 600 (24 stages with drain terminals of adjacent circuits (multiple values ​​of 42) and 16 stages with source terminals of adjacent circuits (multiple values ​​of 24)) achieves an area reduction of approximately 23% without performance degradation. Both the original 43-stage circuit and the proposed stacked gate circuit 600 achieve approximately 0.17% current mismatch between different current branches.

[0054] In some embodiments, different arrangements of multiple values ​​at different levels can be selected to optimize the performance of various types of analog circuit applications.

[0055] Figure 7 and Figure 8 These are diagrams illustrating two different exemplary arrangements of stacked gate circuits 700 and 800 according to some embodiments of the present disclosure. Figure 7As shown, the stacked gate circuit 700 includes N series-coupled transistors M71-M7n, with the gate terminals of transistors M71-M7n together coupled to a control terminal (e.g., a gate terminal) of the stacked gate circuit 700. The number of cells (e.g., multiple values) in each stage of the circuit is greater than the number of cells (e.g., multiple values) in the preceding stage of the circuit coupled to the current stage. In some embodiments, the first stage (e.g., transistor M71) coupled to the source terminal of the stacked gate circuit 700 may have the smallest number of values, while the last stage (e.g., transistor M7n) coupled to the drain terminal of the stacked gate circuit 700 may have the largest number of values.

[0056] Similarly, such as Figure 8 As shown, the stacked gate circuit 800 includes N series-coupled transistors M81-M8n, with the gate terminals of transistors M81-M8n coupled together to a control terminal (e.g., a gate terminal) of the stacked gate circuit 800. Compared to the stacked gate circuit 700, in the stacked gate circuit 800, adjacent stages of transistors M81-M8n are combined together and share the same multiple values. For example, the first two stages (e.g., transistors M81 and M82) have the same multiple values ​​2, the next two stages (e.g., transistors M83 and M84) have the same multiple values ​​6, and so on.

[0057] In the stacked gate circuit 800, the number of cells in each stage of the circuit is greater than or equal to the number of cells in the previous stage of the circuit coupled to the current stage (e.g., multiple values). For example, the drain terminal of the first stage circuit (e.g., transistor M82) is coupled to the source terminal of the second stage circuit (e.g., transistor M83), and the source terminal of the first stage circuit (e.g., transistor M82) is coupled to the drain terminal of the third stage circuit (e.g., transistor M81). The gate terminals of the first, second, and third stage circuits are coupled together.

[0058] The first-level circuit (e.g., transistor M82) and the third-level circuit (e.g., transistor M81) each consist of m units (e.g., 2 units) coupled in parallel. Each of the m units includes one or more transistors coupled in series. The second-level circuit (e.g., transistor M83) consists of n units (e.g., 6 units) coupled in parallel, where m and n are different positive integers. Each of the n units includes one or more transistors coupled in series.

[0059] In some embodiments, the first set of stages coupled to the source end of the stacked gate circuit 800 (e.g., transistors M81 and M82) may have a minimum number of values, while the last set of stages coupled to the drain end of the stacked gate circuit 800 (e.g., transistors M8(n-1) and M8n) may have a maximum number of values. Figure 8In some embodiments, each group includes two stages of transistors having the same plurality of values, but this disclosure is not limited thereto. For example, in some other embodiments, any number of stages may be grouped into groups having the same plurality of values, depending on the actual needs of the circuit application.

[0060] Figure 8 The illustrated embodiment can be represented by the following expression:

[0061] Nx=N(x-1)>N(x-2)=N(x-3)…>N2=N1

[0062] In the above formula, Nx represents the number of units at level x.

[0063] It should be understood that other combinations are also possible, as long as the number of units in each stage of the circuit is greater than or equal to the number of units in the previous stage of the circuit coupled to the current stage (e.g., multiple values), which can be represented by the following expression:

[0064] Nx≥N(x-1)≥…>N3≥N2≥N1

[0065] For example, in some embodiments, the number of cells can be the same for multiple stages adjacent to the source side of the circuit, while the number of cells can be different values ​​in strictly ascending order for multiple stages adjacent to the drain side of the circuit. This can be expressed by the following expression:

[0066] Nx > N(x-1) > N(x-2)

[0067] N3 = N2 = N1

[0068] For example, in some embodiments, the number of cells can be different values ​​in strictly ascending order for multiple stages adjacent to the source side of the circuit, while the number of cells can be the same for multiple stages adjacent to the drain side of the circuit. This can be expressed by the following expression:

[0069] Nx = N(x-1) = N(x-2)

[0070] N3>N2>N1

[0071] refer to Figure 9 This is a schematic diagram illustrating a stacked gate circuit 900 according to some embodiments of the present disclosure. Figure 9 As shown, similar to Figure 7 The stacked gate circuit 700 and Figure 8The stacked gate circuit 800 and stacked gate circuit 900 also include N-stage transistors M91-M9n coupled in series, with the gate terminals of transistors M91-M9n together coupled to a control terminal (e.g., a gate terminal) of the stacked gate circuit 900. The source node of the stacked gate circuit 900 is connected to the source terminal of transistor M91. The drain node of the stacked gate circuit 900 is connected to the drain terminal of transistor M9N.

[0072] In some embodiments, transistors M91-M9n of different stages may have different threshold voltages. For example, transistors M91-M94 having a first threshold voltage in region 910 adjacent to the source side (e.g., the side near the positive power supply voltage terminal) may form a first-stage circuit 940. The remaining transistors having a second threshold voltage, different from the first threshold voltage, in another region 920 adjacent to the drain side (e.g., the side near system ground) may form a second-stage circuit 950. Figure 9 As shown, the drain terminal of the first-stage circuit 940 is coupled to the source terminal of the second-stage circuit 950 at node 930.

[0073] In some embodiments, the first threshold voltage of transistors M91-M94 in region 910 is greater than the second threshold voltage of the remaining transistors in region 920. By arranging transistors M91-M94 with relatively high threshold voltages close to the source side, the output impedance of the stacked gate circuit 900 can be increased. On the other hand, by arranging the remaining transistors with relatively low threshold voltages close to the drain side in the second-stage circuit 950, the transconductance (Gm) of the stacked gate circuit 900 can be increased.

[0074] In some embodiments, as described above, transistors M91-M94 in the first-stage circuit 940 near the source terminals of the stacked gate circuit 900 can operate as source negative feedback resistors in the linear region. By implementing transistors M91-M94 with transistors having higher threshold voltages, the resistance of transistors M91-M94 on the source side can be increased, and an increase in gain can be achieved within the same device size. With the increase in gain, the number of stages and the footprint of the stacked gate circuit can be reduced without degrading circuit performance.

[0075] For example, in some embodiments, simulations show that replacing a 12-stage circuit with high transistor threshold voltages with a 10-stage circuit with high transistor threshold voltages and a 2-stage circuit with low transistor threshold voltages can result in a gain of approximately +6.2 dB. All stages in the simulations have the same multiple values ​​(e.g., 14). In some embodiments, different arrangements of transistors with different threshold voltages in different stages can be selected to optimize performance for various types of analog circuit applications. Figure 9The stacked gate circuit 900 shown and the simulation results discussed above are merely examples and are not intended to limit this disclosure. Alternatively, depending on the needs of various circuit applications, two or more transistors with different threshold voltages can be arranged in different stages of the stacked gate circuit 900.

[0076] Figure 10 and Figure 11 These are diagrams illustrating two different exemplary arrangements of stacked gate circuits 1000 and 1100 according to some embodiments of the present disclosure. Figure 10 As shown, the stacked gate circuit 1000 includes N series-coupled transistors M101-M10n, with the gate terminals of transistors M101-M10n together coupled to a control node (e.g., a gate terminal) of the stacked gate circuit 1000. The source node of the stacked gate circuit 1000 is connected to the source terminal of transistor M101. The drain node of the stacked gate circuit 1000 is connected to the drain terminal of transistor M10n. Each stage of the circuit may include one or more parallel-coupled transistor units. The threshold voltage in each stage of the circuit is lower than the threshold voltage in the previous stage coupled to the current stage. In some embodiments, the first stage (e.g., transistor M101) coupled to the source node of the stacked gate circuit 1000 may have the highest threshold voltage Vth1, and the last stage (e.g., transistor M10n) coupled to the drain node of the stacked gate circuit 1000 may have the lowest threshold voltage Vth1.

[0077] Similarly, such as Figure 11 As shown, the stacked gate circuit 1100 includes N series-coupled transistors M111-M11n, with the gate terminals of transistors M111-M11n coupled together to a control terminal (e.g., a gate terminal) of the stacked gate circuit 1100. The source node of the stacked gate circuit 1100 is connected to the source terminal of transistor M111. The drain node of the stacked gate circuit 1100 is connected to the drain terminal of transistor M11N. Compared to the stacked gate circuit 1000, in the stacked gate circuit 1100, two or more adjacent stages of transistors M111-M11n can be combined and implemented by transistors having the same threshold voltage. For example, the first two stages (e.g., transistors M111 and M112) can be implemented by transistors having a first threshold voltage Vth1, the next two stages (e.g., transistors M113 and M114) can be implemented by transistors having a second threshold voltage Vth2 that is smaller than the first threshold voltage Vth1, and so on.

[0078] In the stacked gate circuit 1100, the threshold voltage in each stage is lower than or equal to the threshold voltage in the previous stage coupled to the current stage. For example, the drain terminal of the first stage circuit (e.g., transistor M112) is coupled to the source terminal of the second stage circuit (e.g., transistor M113), and the source terminal of the first stage circuit (e.g., transistor M112) is coupled to the drain terminal of the third stage circuit (e.g., transistor M111). The gate terminals of the first, second, and third stage circuits are coupled together.

[0079] The threshold voltage Vth2 of transistor M112 is equal to the threshold voltage Vth1 of transistor M111 in the preceding stage circuit coupled to the current stage circuit (e.g., transistor M112). On the other hand, the threshold voltage Vth3 of transistor M113 is less than the threshold voltage Vth2 of transistor M112 in the preceding stage circuit coupled to the current stage circuit (e.g., transistor M113).

[0080] In some embodiments, the first set of stages coupled to the source terminal of the stacked gate circuit 800 (e.g., transistors M111 and 112) may have the highest voltage threshold, and the last set of stages coupled to the drain terminal of the stacked gate circuit 1100 (e.g., transistors M11(n-1) and M11n) may have the lowest voltage threshold. Figure 11 In some embodiments, each group comprises two stages of transistors having the same voltage threshold, but this disclosure is not limited thereto. For example, in some other embodiments, any number of stages can be grouped together to have the same voltage threshold, depending on the actual needs of the circuit application.

[0081] Figure 11 The illustrated embodiment can be represented by the following expression:

[0082] Vth(n) = Vth(n-1) <Vth(n-2)=Vth(n-3)…<Vth2=Vth1

[0083] In the above formula, Vth(n) represents the threshold voltage of the Nth stage transistor.

[0084] It should be understood that other combinations are also possible, as long as the threshold voltage in each stage of the circuit is less than or equal to the threshold voltage in the previous stage coupled to the current stage. This can be expressed by the following expression:

[0085] Vthn≤Vth(n-1)≤…≤Vth3≤Vth2≤Vth1

[0086] For example, in some embodiments, the threshold voltage can be the same for multiple stages adjacent to the source side of the circuit, while the threshold voltage can be different values ​​in strictly descending order for multiple stages adjacent to the drain side of the circuit. This can be expressed by the following expression:

[0087] Vthn <Vth(n-1)<Vth(n-2)

[0088] Vth3 = Vth2 = Vth1

[0089] For example, in some embodiments, the threshold voltages can be different values ​​in strictly descending order for multiple stages adjacent to the source side of the circuit, and the number of cells can be the same for multiple stages adjacent to the drain side of the circuit, which can be expressed by the following expression:

[0090] Vthn=Vth(n-1=Vth(n-2)

[0091] Vth3 <Vth2<Vth1

[0092] It should be understood that, in different embodiments, the transistors in the integrated circuit can be PMOS or NMOS. (See reference) Figure 12A and Figure 12B . Figure 12A This is a schematic diagram illustrating an integrated circuit 1200a using NMOS according to some embodiments of the present disclosure. Figure 12A As shown, integrated circuit 1200a has two branches 1210a and 1220a. Transistors MA1-MAN in branch 1210a and transistors MB1-MBN in branch 1220a have the same multiple values ​​(e.g., multiple values ​​of 4). In some embodiments, transistors MA1-MA4 and MB1-MB4 in region 1230a adjacent to the source side (e.g., the side near system ground GND) operate as source negative feedback resistors in the linear region. Figure 12B This illustrates some embodiments according to the present disclosure. Figure 12A A schematic diagram of the equivalent circuit 1200b of integrated circuit 1200a in the diagram is shown. Figure 12B As shown, transistors MA1-MA4 and MB1-MB4 can be represented by their corresponding equivalent resistors.

[0093] In some embodiments, since transistors MA1-MAN and MB1-MB4 operating in the linear region have little effect on the current mismatch between currents Id1 and Id2, the "multiple" values ​​of transistors MA1-MAN and MB1-MBN in region 1230a can be reduced. By reducing the number of parallel transistors MA1-MAN and MB1-MBN cells, the area of ​​integrated circuit 1200a can be reduced without sacrificing current mismatch performance.

[0094] refer to Figure 12C and Figure 12D . Figure 12CThis is a schematic diagram illustrating an integrated circuit 1200c using NMOS according to some embodiments of the present disclosure. Figure 12D This illustrates some embodiments according to the present disclosure. Figure 12C A schematic diagram of the equivalent circuit 1200d of integrated circuit 1200c in the diagram. Figure 12A Compared to the 1200a integrated circuit in the middle, such as Figure 12C As shown, each branch in integrated circuit 1200c includes two regions 1230c and 1240c. Region 1230c is adjacent to the source side (e.g., the side near system ground), and region 1240c is adjacent to the drain side (e.g., the positive power supply voltage terminal Vdd).

[0095] like Figure 12C As shown, the transistors in region 1230c (e.g., MA1, MA2, MB1, and MB2) have a first plurality of values ​​(e.g., a plurality of values ​​of 2), and the transistors in region 1240c have a second plurality of values ​​larger than the first plurality of values ​​(e.g., a plurality of values ​​of 4). Figure 12D As shown, since the transistors in region 1230c operate in the linear region as source negative feedback resistors, transistors MA1, MA2, MB1 and MB2 can be represented by their respective equivalent resistors.

[0096] Generally speaking, Figure 12B Equivalent circuit 1200b and Figure 12D The total resistance of the equivalent circuit 1200d is similar. In other words, in integrated circuit 1200c, although the values ​​of multiple transistors in region 1230c are reduced to 2, the resulting source negative feedback resistance is similar to that of integrated circuit 1200a with multiple values ​​of 4. Therefore, integrated circuit 1200c can achieve similar current mismatch performance with a smaller circuit area.

[0097] refer to Figure 13 This is a schematic diagram illustrating a stacked gate circuit 1300 using NMOS according to some embodiments of the present disclosure. Figure 13 As shown, the stacked gate circuit 1300 includes a first-stage circuit 1310 and a second-stage circuit 1320.

[0098] The second-stage circuit 1320 is coupled to the first-stage circuit 1310. Specifically, the gate terminal of the first-stage circuit 1310 is coupled to the gate terminal of the second-stage circuit 1320 to form the control terminal G of the stacked gate circuit 1300. The drain terminal of the first-stage circuit 1310 is coupled to the source terminal of the second-stage circuit 1320. The source terminal of the first-stage circuit 1310 can be configured as the source terminal S of the stacked gate circuit 1300. The drain terminal of the second-stage circuit 1320 can be configured as the drain terminal D of the stacked gate circuit 1300.

[0099] Similar to Figure 6 The stacked gate circuit 600 using PMOS is described above. In the stacked gate circuit 1300, the first stage circuit 1310 includes m parallel-coupled cells, each cell including one or more transistors coupled in series. For example, the first stage circuit 1310 may include 24 cells (e.g., multiple values ​​of 24) and 16 stages of transistors, their respective gates coupled together. The second stage circuit 1320 includes n parallel-coupled cells, each cell including one or more transistors coupled in series. For example, the second stage circuit 1320 may include 42 cells (e.g., multiple values ​​of 42) and 24 stages of transistors, their respective gates coupled together. As mentioned above, m and n are different positive integers. In some embodiments, m can be any positive integer less than n to reduce the circuit area of ​​the first stage circuit 1310.

[0100] refer to Figure 14 . Figure 14 This is a flowchart illustrating a method 1400 for manufacturing an integrated circuit according to some embodiments of the present disclosure. For a better understanding of the present disclosure, regarding... Figures 1 to 13 The embodiments shown discuss method 1400, but are not limited thereto. Figure 14 As shown, in some embodiments, method 1400 includes operations 1410-1460.

[0101] Operation 1410 is performed to implement a plurality of first transistors. The first transistors are arranged to form a first circuit comprising m first cells coupled in parallel. Operation 1420 is performed to connect one or more first transistors arranged in the same first cell in series between a first reference terminal and a second reference terminal. Operation 1430 is performed to connect the gates of the first transistors together. Thus, in some embodiments, the first transistors are arranged into m first cells by series coupling one or more first transistors in any one of the first cells. The first cells are coupled in parallel in the first circuit.

[0102] Operation 1440 is performed to implement a plurality of second transistors. The second transistors are arranged to form a second circuit coupled to the first circuit. The second circuit includes n second units coupled in parallel. Operation 1450 is performed to connect one or more second transistors arranged in the same second unit in series between a second reference terminal and a third reference terminal. Thus, in some embodiments, the second transistors are arranged as n second units by series coupling one or more second transistors in any one of the second units. The second units are coupled in parallel in the second circuit. The number of second units in the second circuit may be different from the number of first units in the first circuit. In other words, m and n may be different positive integers. For example, if the drain terminal of the first circuit is coupled to the source terminal of the second circuit, then m may be less than n.

[0103] Operation 1460 is performed to connect the gate of the second transistor to the gate of the first transistor. Thus, the second circuit is coupled to the first circuit. In some embodiments, the first and second transistors may be implemented using transistors having the same threshold voltage. In other embodiments, the first and second transistors may be implemented using transistors with different threshold voltages.

[0104] In some embodiments, method 1400 may optionally include forming a multi-stage circuit, wherein each stage circuit includes a plurality of units coupled in parallel, and each unit includes one or more transistors coupled in series. The number of units in each stage circuit is greater than or equal to the number of units in the preceding stage circuit. For example, a first circuit may be formed between a third circuit and a second circuit. In some embodiments, a third circuit coupled to the first circuit on the opposite side may also include the same number of units coupled in parallel (e.g., m units). In other embodiments, the number of units in the first circuit is greater than the number of units in the third circuit, and the number of units in the second circuit is greater than the number of units in the first circuit.

[0105] refer to Figure 15 . Figure 15 This is a flowchart illustrating a method 1500 for manufacturing an integrated circuit according to some embodiments of the present disclosure. For a better understanding of the present disclosure, regarding... Figures 1 to 13 The embodiments shown discuss method 1500, but are not limited thereto. Figure 15 As shown, in some embodiments, method 1500 includes operations 1510-1560.

[0106] Operation 1510 is performed to implement a plurality of first transistors having a first threshold voltage. The first transistors are arranged to form a first circuit comprising a plurality of cells coupled in parallel. Operation 1520 is performed to connect one or more first transistors arranged in the same cell in series between a first reference terminal and a second reference terminal. Operation 1530 is performed to connect the gates of the first transistors together.

[0107] Operation 1540 is performed to implement a plurality of second transistors having a second threshold voltage different from the first threshold voltage. The second transistors are arranged to form a second circuit coupled to the first circuit. The second circuit includes a plurality of parallel-coupled cells. Operation 1550 is performed to connect one or more second transistors arranged in the same cell in series between a second reference terminal and a third reference terminal. The number of cells in the second circuit may be the same as or different from the number of cells in the first circuit. Operation 1560 is performed to connect the control terminal (e.g., gate) of the second transistor to the control terminal (e.g., gate) of the first transistor. Therefore, in some embodiments, the first and second cells are arranged by transistors with different threshold voltages.

[0108] In some embodiments, method 1500 may also include the optional operation of forming a multi-stage circuit, wherein each stage circuit includes a plurality of units coupled in parallel, and each unit includes one or more transistors coupled in series. The threshold voltage of the transistors in each stage circuit is lower than or equal to the threshold voltage of the transistors in the preceding stage circuit. For example, a first circuit may be formed between a third circuit and a second circuit. In some embodiments, a third circuit coupled to the first circuit on the opposite side may include a third transistor having the same threshold voltage as the first transistor in the first circuit. In other embodiments, the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor, and the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

[0109] The above description includes exemplary operations, but it is not necessary to perform these operations in the order shown. Operations may be added, substituted, rearranged, and / or eliminated as appropriate without departing from the spirit and scope of this disclosure.

[0110] By arranging different numbers of cells in different stages, or by arranging transistors with different threshold voltages in different stages, it is possible to reduce the circuit area without undesirable performance degradation, which provides enhanced circuit design flexibility in space-constrained applications.

[0111] In some embodiments, an integrated circuit is disclosed, comprising: a first circuit including m parallel-coupled first units, each first unit including one or more series-coupled first transistors; and a second circuit including n parallel-coupled second units, each second unit including one or more series-coupled second transistors. The gate terminal of the first circuit is coupled to the gate terminal of the second circuit, and m and n are different positive integers.

[0112] In the aforementioned integrated circuit, the drain terminal of the first circuit is coupled to the source terminal of the second circuit, and m is less than n.

[0113] The aforementioned integrated circuit also includes a third circuit, which comprises m parallel-coupled third units, each of which includes one or more series-coupled third transistors, wherein the source terminal of the first circuit is coupled to the drain terminal of the third circuit.

[0114] The aforementioned integrated circuit also includes: a multi-level circuit, wherein each level of the circuit includes multiple parallel-coupled units, and each unit includes one or more series-coupled transistors, wherein the number of units in the first-level circuit is greater than or equal to the number of units in the previous-level circuit.

[0115] In the aforementioned integrated circuit, the threshold voltage of one or more first transistors is different from the threshold voltage of one or more second transistors.

[0116] In the aforementioned integrated circuit, the drain terminal of the first circuit is coupled to the source terminal of the second circuit, and the threshold voltage of one or more first transistors is greater than the threshold voltage of one or more second transistors.

[0117] The aforementioned integrated circuit also includes a third circuit, which comprises a plurality of third units coupled in parallel. Each third unit includes one or more third transistors coupled in series. The source terminal of the first circuit is coupled to the drain terminal of the third circuit, and the threshold voltage of one or more first transistors is the same as the threshold voltage of one or more third transistors.

[0118] The aforementioned integrated circuit also includes multi-level circuits, each level of which includes multiple parallel-coupled units, and each unit includes multiple series-coupled transistors. The threshold voltage of the transistors in the first level of the circuit is lower than or equal to the threshold voltage of the transistors in the previous level of the circuit.

[0119] In some embodiments, a circuit is also disclosed, comprising: a first stacked gate circuit including a first transistor having a gate terminal, the gate terminals of the first transistor being coupled to each other; and a second stacked gate circuit coupled to the first stacked gate circuit, the second stacked gate circuit including a second transistor having a gate terminal, the gate terminals of the second transistor being coupled to each other. The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

[0120] In the aforementioned integrated circuit, the source of the circuit is connected to the source terminal of one of the first transistors in the first stacked gate circuit, the drain of the circuit is connected to the drain terminal of one of the second transistors in the second stacked gate circuit, and the control node of the circuit is coupled to the gate terminal of the first transistor and the gate terminal of the second transistor.

[0121] In the aforementioned integrated circuit, the first transistor is arranged in m parallel-coupled first units, and the first transistors in the same first unit are coupled in series; wherein, the second transistor is arranged in n parallel-coupled second units, and the second transistors in the same second unit are coupled in series, where m and n are different positive integers.

[0122] In the aforementioned integrated circuit, the drain terminal of the first stacked gate circuit is coupled to the source terminal of the second stacked gate circuit, and m is less than n.

[0123] The aforementioned integrated circuit also includes a third stacked gate circuit coupled to a second stacked gate circuit. The third stacked gate circuit includes a plurality of third transistors having gate terminals, and the gate terminals of the third transistors are coupled to each other. The threshold voltage of the second transistor is greater than the threshold voltage of the third transistor.

[0124] In the aforementioned integrated circuit, the third transistor is arranged in multiple parallel-coupled third units, and the third transistors in the same third unit are coupled in series.

[0125] In some embodiments, a method is also disclosed. The method includes: arranging the first transistors into m first units by series coupling one or more first transistors in any first unit; coupling the first units in parallel in a first circuit; arranging the second transistors into n second units by series coupling one or more second transistors in any second unit, where m and n are different positive integers; coupling the second units in parallel in a second circuit; and coupling the second circuit to the first circuit.

[0126] The above method also includes: coupling the drain terminal of the first unit to the source terminal of the second unit, where m is less than n.

[0127] The above method further includes: arranging a plurality of third transistors into m third units by series coupling one or more third transistors in any one of the third units; coupling the third units in parallel in a third circuit; and coupling the third circuit to a first circuit.

[0128] The above method also includes arranging the first unit and the third unit using transistors with the same threshold voltage.

[0129] The above method also includes arranging the first unit and the second unit using transistors with different threshold voltages.

[0130] The above method also includes: connecting the control terminal of the first transistor and the control terminal of the second transistor.

[0131] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: A first circuit includes m parallel-coupled first units, each first unit including one or more series-coupled first transistors, the source terminals of the m first units being coupled to each other and the drain terminals being coupled to each other, respectively configured as the source terminal and drain terminal of the first circuit; as well as The second circuit includes n parallel-coupled second units, each second unit including one or more series-coupled second transistors, the source terminals of the n second units being coupled to each other and the drain terminals being coupled to each other, respectively configured as the source terminal and drain terminal of the second circuit; in, The gate terminal of the first circuit is coupled to the gate terminal of the second circuit, and m and n are different positive integers.

2. The integrated circuit according to claim 1, wherein, The drain terminal of the first circuit is coupled to the source terminal of the second circuit, and m is less than n.

3. The integrated circuit according to claim 1, further comprising: The third circuit includes m parallel-coupled third units, each third unit including one or more series-coupled third transistors, wherein the source terminal of the first circuit is coupled to the drain terminal of the third circuit.

4. The integrated circuit according to claim 1, further comprising: A multi-level circuit, wherein each level of the circuit includes multiple parallel-coupled units, and each unit includes one or more series-coupled transistors, wherein the number of units in a level of the circuit is greater than or equal to the number of units in the previous level of the circuit.

5. The integrated circuit according to claim 1, wherein, The threshold voltage of one or more first transistors is different from the threshold voltage of one or more second transistors.

6. The integrated circuit according to claim 1, wherein, The drain terminal of the first circuit is coupled to the source terminal of the second circuit, and the threshold voltage of one or more first transistors is greater than the threshold voltage of one or more second transistors.

7. The integrated circuit according to claim 1, further comprising: The third circuit includes a plurality of third units coupled in parallel, each third unit including one or more third transistors coupled in series, wherein the source terminal of the first circuit is coupled to the drain terminal of the third circuit, and the threshold voltage of one or more first transistors is the same as the threshold voltage of one or more third transistors.

8. The integrated circuit according to claim 1, further comprising: A multi-stage circuit, wherein any stage of the circuit includes multiple parallel-coupled units, and any unit includes multiple series-coupled transistors, wherein the threshold voltage of the transistors in the first stage of the circuit is lower than or equal to the threshold voltage of the transistors in the previous stage of the circuit.

9. An integrated circuit, comprising: A first stacked gate circuit includes a plurality of first transistors having gate terminals, the gate terminals of the first transistors being coupled to each other, the first transistors being arranged in m parallel-coupled first units, the first transistors in the same first unit being coupled in series, the source terminals of the m first units being coupled to each other and the drain terminals being coupled to each other, so as to be respectively configured as the source terminals and drain terminals of the first stacked gate circuit. as well as A second stacked gate circuit is coupled to the first stacked gate circuit. The second stacked gate circuit includes a plurality of second transistors having gate terminals. The gate terminals of the second transistors are coupled to each other. The second transistors are arranged in n parallel-coupled second units. The second transistors in the same second unit are coupled in series. m and n are different positive integers. The source terminals and drain terminals of the n second units are coupled to each other to be configured as the source terminals and drain terminals of the second stacked gate circuit, respectively. The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor.

10. The integrated circuit according to claim 9, wherein, The source of the integrated circuit is connected to the source terminal of one of the first transistors in the first stacked gate circuit, the drain of the circuit is connected to the drain terminal of one of the second transistors in the second stacked gate circuit, and the control node of the integrated circuit is coupled to the gate terminal of the first transistor and the gate terminal of the second transistor.

11. The integrated circuit according to claim 9, wherein, Both the plurality of first transistors and the plurality of second transistors are PMOS transistors.

12. The integrated circuit according to claim 11, wherein, The drain terminal of the first stacked gate circuit is coupled to the source terminal of the second stacked gate circuit, and m is less than n.

13. The integrated circuit according to claim 9, further comprising: A third stacked gate circuit is coupled to the second stacked gate circuit, the third stacked gate circuit including a plurality of third transistors having gate terminals, the gate terminals of the third transistors being coupled to each other; The threshold voltage of the second transistor is greater than the threshold voltage of the third transistor.

14. The integrated circuit according to claim 13, wherein, The third transistor is arranged in multiple parallel-coupled third units, and the third transistors in the same third unit are coupled in series.

15. A method for manufacturing an integrated circuit, comprising: Multiple first transistors are arranged into m first units by connecting one or more first transistors in series with any one of the first units; The first unit is coupled in parallel in the first circuit, wherein the source terminals of m first units are coupled to each other and the drain terminals are coupled to each other, so as to be respectively configured as the source terminals and drain terminals of the first circuit; Multiple second transistors are arranged into n second units by connecting one or more second transistors in series with any one of the second units, where m and n are different positive integers; The second unit is coupled in parallel in the second circuit, wherein the source terminals and drain terminals of the n second units are coupled to each other, respectively configured as the source terminals and drain terminals of the second circuit; and The second circuit is coupled to the first circuit.

16. The method of claim 15, further comprising: The drain terminal of the first unit is coupled to the source terminal of the second unit, where m is less than n.

17. The method of claim 15, further comprising: Multiple third transistors are arranged into m third units by connecting one or more third transistors in series in any one of the third units; The third unit is coupled in parallel in the third circuit; as well as The third circuit is coupled to the first circuit.

18. The method of claim 17, further comprising: The first unit and the third unit are arranged using transistors with the same threshold voltage.

19. The method of claim 15, further comprising: The first and second units are arranged using transistors with different threshold voltages.

20. The method of claim 15, further comprising: Connect the control terminal of the first transistor and the control terminal of the second transistor.

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