Automatic detection circuit and method for integrated circuit

Abstract

The present invention discloses an automatic detection circuit and method for integrated circuits. The automatic detection circuit is suitable for a system on a chip. In the automatic detection mode, the control unit of the automatic detection circuit: controls a first dynamic switching circuit to switch the control right of a main bus to a virtual master control circuit; controls a second dynamic switching circuit to connect a memory interface and a silicon intellectual property circuit to a virtual input-output circuit; transmits a detection vector to the virtual master control circuit to set and start the memory interface and the silicon intellectual property circuit; transmits a detection vector to the virtual input-output circuit to replace an external memory and an external device to transmit and receive signals; and compares a signal received by the virtual master control circuit or a signal received by the virtual input-output circuit with predetermined signal data to generate a detection result.

Description

Technical Field

[0001] The present invention relates to an automatic detection circuit and method for integrated circuits, and in particular to an automatic detection circuit and method for integrated circuits capable of simplifying the development, verification, mass production and testing processes of ICs. Background Art

[0002] During the development phase of an integrated circuit (IC) system on chip (SOC), it is usually necessary to prepare various IC verification equipment and develop verification procedures.

[0003] Specifically, during the mass production test phase of SOC, in addition to scan test (SCAN) and memory built-in self-test (MBIST), functional pattern test is also required. At this time, it is usually necessary to develop various IC test equipment and test procedures, and use the test machine to test and compare the test results.

[0004] However, as the functionality and complexity of SOCs increase, the number and complexity of verification equipment and verification procedures also increase, making the required verification time longer and longer, affecting the IC development schedule, and the required verification costs also continue to rise.

[0005] After IC mass production testing and shipment, some ICs may still have problems during system testing or actual use. At this time, the ICs usually need to be sent back to the original manufacturer for testing. Firstly, it is impossible to detect and discover the problems in real time, and secondly, it also takes a lot of testing time and manpower and material costs. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide an automatic detection circuit and method for integrated circuits that can simplify the development, verification, mass production and testing processes of ICs in view of the deficiencies in the prior art.

[0007] In order to solve the above technical problems, one of the technical solutions adopted by the present invention is to provide an automatic detection circuit for an integrated circuit, which is suitable for being arranged in a system single chip on a printed circuit board, and the system single chip includes a processor, a main bus, a plurality of memory interfaces connected to the main bus and a plurality of silicon intellectual property circuits, and a chip controller. The automatic detection circuit for an integrated circuit includes a first dynamic switching circuit, a second dynamic switching circuit, a virtual master control circuit, a virtual input and output circuit, a detection vector unit and a control unit. The first dynamic switching circuit is connected between the processor and the main bus. The second dynamic switching circuit is connected to the memory interfaces and the silicon intellectual property circuits, wherein the memory interfaces are respectively connected to a plurality of external memories through the second dynamic switching circuit, and the silicon intellectual property circuits are connected to a plurality of external devices through the second dynamic switching circuit. The virtual master control circuit is connected to the first dynamic switching circuit and is configured to replace the processor to set the memory interfaces and the silicon intellectual property circuits at runtime. The virtual input-output circuit is connected to the second dynamic switching circuit and is configured to replace the external memories and the external devices to transmit signals and receive signals transmitted by the memory interfaces and the silicon intellectual property circuits during operation. The detection vector unit is configured to generate a plurality of detection vectors required for detecting the system single chip. A control unit is connected to the chip controller, the first dynamic switching circuit, the second dynamic switching circuit, the virtual master circuit, the virtual input-output circuit and the detection vector unit, and is configured to: control the first dynamic switching circuit to switch the control of the main bus from the processor to the virtual master circuit; control the second dynamic switching circuit to switch the memory interfaces and the silicon intellectual property circuits to the virtual input-output circuit; transmit the detection vectors to the virtual master circuit so that the virtual master circuit sets and starts the memory interfaces and the silicon intellectual property circuits according to the detection vectors; transmit the detection vectors to the virtual input-output circuit so as to control the virtual input-output circuit to replace the external memories and the external devices to transmit signals and receive signals transmitted by the memory interfaces and the silicon intellectual property circuits; and compare the signals received by the virtual master circuit or the virtual input-output circuit with a predetermined signal data to generate a detection result.

[0008] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide an automatic detection method for integrated circuits, which is suitable for a system single chip set on a printed circuit board, wherein the system single chip includes a processor, a main bus, multiple memory interfaces and multiple silicon intellectual property circuits connected to the main bus, and a chip controller. The automatic detection method for integrated circuits includes: configuring a control unit to enter an automatic detection mode to: control a first dynamic switching circuit connected between the processor and the main bus to switch the control right of the main bus from the processor to the virtual main control circuit; control a second dynamic switching circuit connected to the memory interfaces and the silicon intellectual property circuits to switch so that the memory interfaces and the silicon intellectual property circuits are connected to a virtual input and output circuit, wherein the memory interfaces are respectively connected to the virtual input and output circuits through the second dynamic switching circuit. In a plurality of external memories, the silicon intellectual property circuits are connected to a plurality of external devices through the second dynamic switching circuit, and the virtual input-output circuit is connected to the second dynamic switching circuit and the control unit; a plurality of detection vectors for detecting the system single chip are obtained from a detection vector unit, and the detection vectors are transmitted to a virtual master control circuit connected to the first dynamic switching circuit, so that the virtual master control circuit sets and starts the memory interfaces and the silicon intellectual property circuits according to the detection vectors; the detection vectors are transmitted to the virtual input-output circuit to control the virtual input-output circuit to replace the external memories and the external devices to transmit signals, and to receive signals transmitted by the memory interfaces and the silicon intellectual property circuits; and the signals received by the virtual master control circuit or the virtual input-output circuit are compared with a predetermined signal data to generate the detection result.

[0009] One of the beneficial effects of the present invention is that the automatic detection circuit and method for integrated circuits provided by the present invention can eliminate the above-mentioned shortcomings of the prior art by combining circuit design methods, simplify IC development, verification, mass production and detection processes and methods, shorten the development time required for each stage and reduce the required costs, and can perform dynamic self-detection in the actual use stage to detect and discover problems in real time.

[0010] To further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are only for reference and description and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 The figure is a functional block diagram of an automatic detection circuit for an integrated circuit according to an embodiment of the present invention.

[0012] Figure 2 The figure is a flow chart of an automatic detection method for integrated circuits according to an embodiment of the present invention.

[0013] Explanation of symbols

[0014] 1: Automatic detection circuit

[0015] 10: The first dynamic switching circuit

[0016] 11: Second dynamic switching circuit

[0017] 12: Virtual master control circuit

[0018] 13: Virtual input and output circuit

[0019] 14: Detection vector unit

[0020] 15: Control unit

[0021] 16: Detection and recording unit

[0022] 17: Compare registers

[0023] CCON: Chip Controller

[0024] CPU: Processor

[0025] EC: External Circuit

[0026] EE: External Equipment

[0027] EM: External Memory

[0028] IP: Intellectual Property Circuit

[0029] MI: Memory Interface

[0030] PBUS: Main Bus

[0031] PCB: Printed Circuit Board

[0032] SBUS: Sub-bus

[0033] SOC: System on Chip

[0034] Ve: detection vector DETAILED DESCRIPTION

[0035] The following is an explanation of the implementation methods of the "automatic detection circuit and method for integrated circuits" disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention. In addition, the term "or" used in this article may include any one or more combinations of the associated listed items depending on the actual situation.

[0036] Figure 1 FIG. 1 is a functional block diagram of an automatic detection circuit for an integrated circuit according to an embodiment of the present invention. Figure 1 As shown, an embodiment of the present invention provides an automatic detection circuit 1 for an integrated circuit, which is suitable for being arranged in a system on a chip SOC on a printed circuit board PCB. The system on a chip SOC includes a processor CPU, a main bus PBUS, a plurality of memory interfaces MI connected to the main bus PBUS, a plurality of silicon intellectual property circuits IP, and a chip controller CCON.

[0037] The automatic detection circuit 1 for an integrated circuit comprises a first dynamic switching circuit 10 , a second dynamic switching circuit 11 , a virtual master control circuit 12 , a virtual input and output circuit 13 , a detection vector unit 14 and a control unit 15 .

[0038] The first dynamic switching circuit 10 is connected between the processor and the processor and the main bus, and the second dynamic switching circuit 11 is connected to the memory interfaces MI and the intellectual property (IP) circuits IP, wherein the memory interfaces MI are respectively connected to multiple external memories EM through the second dynamic switching circuit 11, and the intellectual property circuits IP are connected to multiple external devices EE or external circuits EC through the second dynamic switching circuit 11, or are connected to external devices EE through external circuits EC.

[0039] In addition, in some embodiments, the system on a chip SOC further includes a sub-bus SBUS connected between the main bus PBUS and a portion of the silicon intellectual property circuit IP, but the present invention is not limited thereto. The first dynamic switching circuit 10 and the second dynamic switching circuit 11 can respectively include a plurality of switch circuits controlled by the control unit 15.

[0040] The main bus PBUS and the sub-bus SBUS may be, for example, general internal buses such as internal buses compatible with the open core protocol (OCP) and the advanced eXtensible Interface (AXI) protocol.

[0041] The first dynamic switching circuit 10 is used to switch the control rights of the memory interfaces MI and the silicon intellectual property circuits IP between the processor CPU and the virtual master control circuit 12, while the second dynamic switching circuit 11 guides the silicon intellectual property circuits IP and the memory interfaces MI and externally transmitted signals to the virtual input and output circuit 13.

[0042] It should be noted that the full name of silicon IP is intellectual property core (IP core). In the reusable design methodology of integrated circuits, it refers to a reusable module in the form of logic units and chip designs provided by one party. Silicon IP has usually passed design verification. Designers can shorten the design cycle by designing based on silicon IP.

[0043] The virtual master control circuit 12 is connected to the first dynamic switching circuit 10 and is configured to replace the processor CPU to set the memory interfaces and the IP circuits during operation.

[0044] The virtual input / output circuit 13 is connected to the second dynamic switching circuit, and is configured to replace the external memories EM and the external devices to transmit signals, and receive signals transmitted by the memory interfaces MI and the intellectual property circuits IP during operation.

[0045] The detection vector unit 14 is configured to generate a plurality of detection vectors Ve required for detecting the system on a chip SOC. The detection vectors Ve may include, for example, a plurality of setting and activation detection vectors and a plurality of input and output detection vectors, wherein the setting and activation detection vectors are used by the virtual master control circuit 12 to set and activate the memory interfaces MI and the silicon intellectual property circuits IP, and the input and output detection vectors are used by the virtual input and output circuit 13 to replace the external memories EM and the external devices EE to transmit signals, and to receive signals transmitted by the memory interfaces MI and the silicon intellectual property circuits IP.

[0046] The control unit 15 is connected to the chip controller CCON, the first dynamic switching circuit 10, the second dynamic switching circuit 11, the virtual master control circuit 12, the virtual input and output circuit 13 and the detection vector unit, and the control unit 15 can enter the automatic detection mode according to a pin configuration. For example, during the IC verification and mass production test stage, the IC can be set to the automatic detection mode through the pin configuration, and the chip controller CCON can control the control unit 15 to enter the automatic detection mode according to the pin configuration, or, during the actual use of the IC, the system where the IC is located is in an idle state, and after a predetermined time, the control unit 15 can be dynamically switched to the automatic detection mode through the chip controller CCON, and after the detection is completed, or when the detection is interrupted, the chip controller CCON returns to the normal working mode. The control unit 15 can be hardware such as a central processing unit, a microcontroller, etc.

[0047] After describing the basic structure of the automatic detection circuit 1 of the present invention, the automatic detection method for integrated circuits of the present invention is further described. Figure 2 , which is a flow chart of an automatic detection method for an integrated circuit according to an embodiment of the present invention. As shown in the figure, the automatic detection method for an integrated circuit may include configuring the control unit 15 to enter an automatic detection mode to perform the following steps:

[0048] Step S100 : controlling the first dynamic switching circuit 10 to switch the control right of the main bus PBUS from the processor CPU to the virtual main control circuit 12 .

[0049] Step S101 : controlling the second dynamic switching circuit 11 to switch so that the memory interface MI and the intellectual property circuit IP are connected to the virtual input / output circuit 13 .

[0050] Step S102: Obtain multiple detection vectors Ve for detecting the system single chip SOC from the detection vector unit 14, and transmit the detection vectors Ve to the virtual master control circuit 12, so that the virtual master control circuit 12 sets and activates the memory interfaces MI and the silicon intellectual property circuits IP according to the detection vectors Ve. For example, the detection vectors Ve can be stored by the detection vector unit 14, or the detection vector unit 14 can obtain the detection vectors Ve from an external input signal source (for example, provided by a user).

[0051] Step S103: transmitting the detection vectors Ve to the virtual input-output circuit to control the virtual input-output circuit 13 to replace the external memories EM and the external devices EE to transmit signals, and to receive signals transmitted by the memory interfaces MI and the intellectual property circuits IP.

[0052] After each silicon intellectual property circuit IP is started and runs, the process proceeds to step S104: comparing the signal received by the virtual main control circuit 12 or the signal received by the virtual input and output circuit 13 with the predetermined signal data to generate a detection result.

[0053] Among them, Figure 1 As shown, the automatic detection circuit 1 may further include a comparison register 17 for storing predetermined signal data. The comparison register 17 may be, for example Figure 1 As shown, it is included in the control unit 15, or can be independently set in the automatic detection circuit 1 and accessed by the control unit 15, but the present invention is not limited to this.

[0054] like Figure 1 As shown, in a specific embodiment, the automatic detection circuit 1 further includes a detection recording unit 16 for storing the detection result. Therefore, optionally, after step S104, the automatic detection method may further proceed to step S105: configuring the detection recording unit to store the detection result.

[0055] In other words, after each silicon intellectual property circuit IP is started and runs, the virtual input-output circuit 13 can receive the signal originally scheduled to be transmitted to the input-output interface (i.e., the interface connected to the external memory EM, the external circuit EC or the external device EE) of each silicon intellectual property circuit IP and compare it to generate a detection result. Alternatively, the virtual main control circuit 12 can read and compare the register contents of each silicon intellectual property circuit IP and related circuits to determine whether the circuit detection result is normal, and store the detection result (including the error code) in the detection recording unit for subsequent observation and interpretation, and implement the required subsequent actions accordingly.

[0056] [Beneficial Effects of Embodiments]

[0057] One of the beneficial effects of the present invention is that the automatic detection circuit and method for integrated circuits provided by the present invention can eliminate the above-mentioned shortcomings of the prior art by combining circuit design methods, simplify IC development, verification, mass production and detection processes and methods, shorten the development time required for each stage and reduce the required costs, and can perform dynamic self-detection in the actual use stage to detect and discover problems in real time.

[0058] The contents disclosed above are only preferred feasible embodiments of the present invention, and are not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention's specification and drawings are included in the claims of the present invention.

Claims

1. An automatic detection circuit for an integrated circuit, which is suitable for being arranged in a system-on-chip on a printed circuit board, wherein the system-on-chip includes a processor, a main bus, a plurality of memory interfaces and a plurality of silicon intellectual property circuits connected to the main bus, and a chip controller, wherein the automatic detection circuit for an integrated circuit includes: a first dynamic switching circuit connected between the processor and the main bus; a second dynamic switching circuit connected to the plurality of memory interfaces and the plurality of silicon intellectual property circuits, wherein the plurality of memory interfaces are connected to a plurality of external memories through the second dynamic switching circuit, and the plurality of silicon intellectual property circuits are connected to a plurality of external devices through the second dynamic switching circuit; a virtual master control circuit connected to the first dynamic switching circuit and configured to replace the processor to set the plurality of memory interfaces and the plurality of silicon intellectual property circuits during operation; a virtual input-output circuit connected to the second dynamic switching circuit and configured to replace the plurality of external memories and the plurality of external devices to transmit signals and receive signals transmitted by the plurality of memory interfaces and the plurality of silicon intellectual property circuits during operation; a detection vector unit configured to generate a plurality of detection vectors required for detecting the system single chip; as well as A control unit is connected to the chip controller, the first dynamic switching circuit, the second dynamic switching circuit, the virtual master control circuit, the virtual input and output circuit, and the detection vector unit, and is configured to enter an automatic detection mode to: Controlling the first dynamic switching circuit to switch the control right of the main bus from the processor to the virtual master control circuit; Controlling the second dynamic switching circuit to switch the plurality of memory interfaces and the plurality of silicon intellectual property circuits to be connected to the virtual input-output circuit; Transmitting the plurality of detection vectors to the virtual master control circuit, so that the virtual master control circuit sets and activates the plurality of memory interfaces and the plurality of silicon intellectual property circuits according to the plurality of detection vectors; Transmitting the plurality of detection vectors to the virtual input-output circuit to control the virtual input-output circuit to replace the plurality of external memories and the plurality of external devices to transmit signals, and to receive signals transmitted by the plurality of memory interfaces and the plurality of silicon intellectual property circuits; and The signal received by the virtual main control circuit or the signal received by the virtual input-output circuit is compared with a predetermined signal data to generate a detection result.

2. The automatic detection circuit for integrated circuits as claimed in claim 1 further comprises a detection recording unit for storing detection results. 3 . The automatic detection circuit for an integrated circuit as claimed in claim 1 , wherein the control unit enters the automatic detection mode according to a pin configuration.

4. The automatic detection circuit for an integrated circuit as described in claim 1, wherein the multiple detection vectors include multiple set-up and start-up detection vectors and multiple input-output detection vectors, and the multiple set-up and start-up detection vectors are used by the virtual master control circuit to set and start the multiple memory interfaces and the multiple silicon intellectual property circuits, and the multiple input-output detection vectors are used by the virtual input-output circuit to replace the multiple external memories and the multiple external devices to transmit signals, and to receive signals transmitted by the multiple memory interfaces and the multiple silicon intellectual property circuits. 5 . The automatic detection circuit for an integrated circuit as claimed in claim 1 , wherein the detection vector unit stores the plurality of detection vectors. 6 . The automatic detection circuit for an integrated circuit as claimed in claim 1 , wherein the detection vector unit obtains the plurality of detection vectors from an external input signal source.

7. The automatic detection circuit for integrated circuit as claimed in claim 1, further comprising a comparison register for storing the predetermined signal data.

8. An automatic detection method for an integrated circuit, which is applicable to a system-on-chip disposed on a printed circuit board, wherein the system-on-chip includes a processor, a main bus, a plurality of memory interfaces and a plurality of silicon intellectual property circuits connected to the main bus, and a chip controller, and the automatic detection method for the integrated circuit comprises: Configuring a control unit to enter an automatic detection mode: Control a first dynamic switching circuit connected between the processor and the main bus to switch the control right of the main bus from the processor to a virtual main control circuit; Controlling a second dynamic switching circuit connected to the plurality of memory interfaces and the plurality of silicon intellectual property circuits to switch so that the plurality of memory interfaces and the plurality of silicon intellectual property circuits are connected to a virtual input-output circuit, wherein the plurality of memory interfaces are respectively connected to a plurality of external memories through the second dynamic switching circuit, the plurality of silicon intellectual property circuits are connected to a plurality of external devices through the second dynamic switching circuit, and the virtual input-output circuit is connected to the second dynamic switching circuit and the control unit; Acquire a plurality of detection vectors for detecting the system single chip from a detection vector unit, and transmit the plurality of detection vectors to a virtual master control circuit connected to the first dynamic switching circuit, so that the virtual master control circuit sets and activates the plurality of memory interfaces and the plurality of silicon intellectual property circuits according to the plurality of detection vectors; Transmitting the plurality of detection vectors to the virtual input-output circuit to control the virtual input-output circuit to replace the plurality of external memories and the plurality of external devices to transmit signals, and to receive signals transmitted by the plurality of memory interfaces and the plurality of silicon intellectual property circuits; as well as The signal received by the virtual main control circuit or the signal received by the virtual input-output circuit is compared with a predetermined signal data to generate a detection result. 9 . The automatic detection method for integrated circuits as claimed in claim 8 , further comprising configuring a detection recording unit to store the detection result.

10. The automatic detection method for an integrated circuit as claimed in claim 8, wherein the multiple detection vectors include multiple set-up and start-up detection vectors and multiple input-output detection vectors, and the multiple set-up and start-up detection vectors are used by the virtual master control circuit to set and start the multiple memory interfaces and the multiple silicon intellectual property circuits, and the multiple input-output detection vectors are used by the virtual input-output circuit to replace the multiple external memories and the multiple external devices to transmit signals, and to receive signals transmitted by the multiple memory interfaces and the multiple silicon intellectual property circuits.

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