General FPGA task scheduling method and device

Abstract

A universal FPGA task scheduling system and method is described. The system consists of three major components: an FPGA task scheduler, an FPGA task trigger source, and FPGA tasks. By flexibly connecting these three components, FPGA tasks with varying requirements can be scheduled and executed. This system and method is applicable to FPGA boards with different functional requirements. Through simple program configuration, FPGA task scheduling can be adjusted to meet different requirements without modifying the FPGA program. This invention improves the versatility of FPGA program design, reduces FPGA modification and maintenance costs, and reduces the number of FPGA project versions required for various applications, effectively improving the versatility, stability, and maintainability of FPGA programs.

Description

Technical Field

[0001] The present invention relates to the technical field of back-to-back flexible direct current transmission, and in particular to a general FPGA task scheduling method and device. Background Art

[0002] FPGA applications are expanding, and designs are becoming increasingly complex. FPGA design often requires program modifications and extensive debugging and testing due to minor changes in application requirements. The same applies to changes in the scheduling conditions of an FPGA task. When an application requires different execution conditions for a task, a new round of FPGA program adjustments and extensive testing and debugging are typically required. This work increases the workload and time required for FPGA program development while also compromising the versatility, stability, and maintainability of FPGA programs.

[0003] In existing design solutions, different FPGA task scheduling is usually designed according to the specific needs of the application, which leads to the following defects:

[0004] 1) The task scheduler is not universal. Different boards have different schedulers, which are not easy to inherit and maintain.

[0005] 2) FPGA program configuration is not flexible. Once the application has different requirements, the FPGA program needs to be modified. The modification and maintenance costs of FPGA are high, and there are many FPGA versions, which is very detrimental to the stability and maintainability of FPGA programs. Summary of the Invention

[0006] The purpose of the present invention is to address the deficiencies of the existing technology and provide a universal FPGA task scheduling system and method, which can be applied to FPGA boards with different functional requirements. The program can adjust the FPGA task scheduling to meet different requirements through simple configuration without modifying the FPGA program.

[0007] To achieve the above objectives, the present invention adopts the following technical solutions:

[0008] A first aspect of the present invention provides a universal FPGA task scheduling system, comprising N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks, where N1, N2, and N3 are natural numbers;

[0009] Each of the FPGA task schedulers is triggered by a different FPGA task trigger source and is connected to an FPGA task triggered by the corresponding FPGA task trigger source;

[0010] The FPGA task trigger source is a collection of various trigger sources for triggering the FPGA task scheduler;

[0011] The FPGA tasks are various specific FPGA work tasks that are executed by the FPGA task scheduler.

[0012] Furthermore, one task scheduler can select multiple FPGA trigger sources for triggering; one FPGA task scheduler can be connected to multiple FPGA tasks.

[0013] Furthermore, it also includes a configuration interface, through which the FPGA scheduler is configured with corresponding FPGA task trigger sources and FPGA tasks.

[0014] Furthermore, it also includes a configuration register for storing the configuration relationship between the FPGA task scheduler, FPGA task trigger source and FPGA task.

[0015] A second aspect of the present invention provides a general FPGA task scheduling method, which is executed by the general FPGA task scheduling system as described above, and includes the following steps:

[0016] Set up N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks;

[0017] Set the FPGA task trigger source and FPGA task corresponding to each FPGA task scheduler;

[0018] When a certain FPGA task trigger source meets the trigger condition, the corresponding FPGA task scheduler is triggered to execute, and the FPGA task scheduler schedules the execution of the corresponding attached FPGA task.

[0019] Furthermore, one task scheduler can select multiple FPGA trigger sources for triggering; one FPGA task scheduler can be connected to multiple FPGA tasks.

[0020] Furthermore, the FPGA scheduler is configured with corresponding FPGA task trigger sources and FPGA tasks through a configuration interface.

[0021] Furthermore, a configuration register is set to store the configuration relationship between the FPGA task scheduler, the FPGA task trigger source and the FPGA task.

[0022] Furthermore, the configuration relationship among the FPGA task scheduler, the FPGA task trigger source, and the FPGA task can be modified.

[0023] In summary, the present invention provides a universal FPGA task scheduling system and method. This system consists of three major components: an FPGA task scheduler, an FPGA task trigger source, and FPGA tasks. By flexibly connecting these three components, FPGA tasks with varying requirements can be scheduled and executed. This system and method are applicable to FPGA boards with different functional requirements. Through simple program configuration, FPGA task scheduling can be adjusted to meet different requirements without modifying the FPGA program. This invention improves the versatility of FPGA program design, reduces FPGA modification and maintenance costs, and reduces the number of FPGA project versions required for various applications, effectively improving the versatility, stability, and maintainability of FPGA programs. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a block diagram of an FPGA task scheduling system according to an embodiment of the present invention;

[0025] Figure 2 Schematic diagram of the process of the FPGA task scheduling method according to an embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of a specific implementation of the FPGA task scheduling system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0028] The first aspect of the present invention provides a general FPGA task scheduling system, such as Figure 1 As shown, a general FPGA task scheduler is designed according to application requirements: N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks are designed, where N1, N2, and N3 are natural numbers. Each FPGA task scheduler is triggered by a different FPGA task trigger source, and is attached with FPGA tasks triggered by the corresponding FPGA task trigger source, for scheduling the execution of different FPGA tasks. The FPGA task trigger source is a collection of various trigger sources used to trigger the FPGA task scheduler. FPGA tasks are various specific FPGA work tasks attached to the FPGA task scheduler for execution.

[0029] Furthermore, a single task scheduler can select multiple FPGA trigger sources for triggering; a single FPGA task scheduler can be attached to multiple FPGA tasks. The specific attachment method for the FPGA task scheduler is set: the FPGA task selects the attached FPGA task scheduler, and the FPGA task scheduler selects the FPGA task trigger source. Each FPGA task can select any FPGA task scheduler for attachment, and each FPGA task scheduler can select 1-N2 FPGA task trigger sources as its trigger conditions.

[0030] Furthermore, the system also includes a configuration interface for configuring the FPGA scheduler with corresponding FPGA task trigger sources and FPGA tasks. Furthermore, the system also includes a configuration register for storing the configuration relationship between the FPGA task scheduler, FPGA task trigger sources, and FPGA tasks. Through the configuration interface and configuration register, the FPGA task can select the FPGA task scheduler, and the FPGA task scheduler can select the FPGA task trigger source.

[0031] The second aspect of the present invention provides a general FPGA task scheduling method, which is executed by the general FPGA task scheduling system as described above. Figure 2 As shown, the following steps are included:

[0032] Step S100 , setting N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks; N1, N2, and N3 are natural numbers.

[0033] Step S200, setting the FPGA task trigger source and FPGA task corresponding to each FPGA task scheduler; the FPGA task trigger source is a collection of various trigger sources used to trigger the FPGA task scheduler; the FPGA task is various specific FPGA work tasks that the FPGA task scheduler is attached to execute.

[0034] In step S300, when a trigger source for an FPGA task meets the trigger condition, the corresponding FPGA task scheduler is triggered and executed. The FPGA task scheduler schedules the execution of the corresponding attached FPGA task. The task triggering procedure of a general FPGA task scheduler: When the FPGA task trigger source condition is met, the corresponding FPGA task scheduler is first triggered to enter the execution state. The FPGA task scheduler then starts the FPGA task attached to the scheduler and puts it into the running state. This process implements the scheduling process for a specific FPGA task.

[0035] Furthermore, one task scheduler can select multiple FPGA trigger sources for triggering; one FPGA task scheduler can be connected to multiple FPGA tasks.

[0036] Furthermore, the FPGA scheduler is configured with corresponding FPGA task trigger sources and FPGA tasks through a configuration interface.

[0037] Furthermore, a configuration register is set to store the configuration relationship between the FPGA task scheduler, the FPGA task trigger source and the FPGA task.

[0038] Furthermore, the configuration relationship among the FPGA task scheduler, the FPGA task trigger source, and the FPGA task can be modified.

[0039] The present invention will be further described below through a specific embodiment. Specific embodiment 1:

[0041] like Figure 3 As shown, according to the above steps, a general FPGA task scheduler with N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks is designed.

[0042] According to the specific application requirements, the scheduling requirements of N3 FPGA task sources are analyzed to complete the design of the FPGA scheduler configuration scheme. In Example 1, FPGA task 1 is attached to FPGA task scheduler 1, and its trigger condition is trigger source 2; FPGA tasks 2, 4 and N3 have the same scheduling requirements, and FPGA tasks 2, 4, and N3 are attached to FPGA task scheduler 2, and the trigger condition is trigger source N2; FPGA task 3 has a unique scheduling requirement, and it is attached to FPGA task scheduler N1, and its trigger condition is any one of trigger source 1 and trigger source 2. The specific attachment method and trigger source are as follows Figure 3 shown.

[0043] According to the design scheme of FPGA scheduler configuration, the FPGA scheduler is configured through the configuration interface.

[0044] When the trigger source 1 condition is met, the FPGA task scheduler N1 is triggered to execute, and the FPGA task scheduler N1 schedules the execution of FPGA task 3.

[0045] When the trigger source 2 condition is met, FPGA task scheduler 1 and N1 are triggered to execute. FPGA task scheduler 1 schedules FPGA task 1 for execution; FPGA task scheduler N1 schedules FPGA task 3 for execution.

[0046] When the trigger source N2 condition is met, FPGA task scheduler 2 is triggered to execute, and FPGA task scheduler 2 schedules the execution of FPGA tasks 2, 4, and N3.

[0047] The above completes the design, configuration and implementation of a specific facility example.

[0048] In summary, the present invention provides a universal FPGA task scheduling system and method. This system consists of three major components: an FPGA task scheduler, an FPGA task trigger source, and FPGA tasks. By flexibly connecting these three components, FPGA tasks with varying requirements can be scheduled and executed. This system and method are applicable to FPGA boards with different functional requirements. Through simple program configuration, FPGA task scheduling can be adjusted to meet different requirements without modifying the FPGA program. This invention improves the versatility of FPGA program design, reduces FPGA modification and maintenance costs, and reduces the number of FPGA project versions required for various applications, effectively improving the versatility, stability, and maintainability of FPGA programs.

[0049] It should be understood that the above-described specific embodiments of the present invention are merely illustrative or illustrative of the principles of the present invention and do not constitute limitations of the present invention. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present invention should be included within the scope of protection of the present invention. In addition, the appended claims are intended to cover all variations and modifications that fall within the scope and metes and bounds of the appended claims, or equivalents thereof.

Claims

1. A general FPGA task scheduling system, characterized in that: It includes N1 FPGA task schedulers, N2 FPGA task trigger sources and N3 FPGA tasks, where N1, N2 and N3 are natural numbers. Each of the FPGA task schedulers is triggered by a different FPGA task trigger source, and is connected to an FPGA task triggered by the corresponding FPGA task trigger source, for scheduling and executing different FPGA tasks; The task triggering procedure of the FPGA task scheduler includes: when the FPGA task trigger source condition is met, first triggering the corresponding FPGA task scheduler to enter the execution state, and then the FPGA task scheduler starts the FPGA task attached to the scheduler to enter the running state; attaching FPGA task 1 to FPGA task scheduler 1, and its triggering condition is trigger source 2; FPGA tasks 2, 4, and N3 have the same scheduling requirements, and attaching FPGA tasks 2, 4, and N3 to FPGA task scheduler 2, and the triggering condition is trigger source N2; FPGA task 3 has a unique scheduling requirement, and attaching it to FPGA task scheduler N1, and its triggering condition is either trigger source 1 or trigger source 2; The FPGA task trigger source is a collection of various trigger sources for triggering the FPGA task scheduler; The FPGA tasks are various specific FPGA work tasks that are executed by the FPGA task scheduler; the configuration relationship between the FPGA task scheduler, FPGA task trigger source and FPGA task can be changed.

2. The universal FPGA task scheduling system according to claim 1, characterized in that: One task scheduler can select multiple FPGA trigger sources for triggering; one FPGA task scheduler can connect multiple FPGA tasks.

3. The universal FPGA task scheduling system according to claim 1 or 2, characterized in that: It also includes a configuration interface, through which the FPGA task scheduler is configured with corresponding FPGA task trigger sources and FPGA tasks.

4. The universal FPGA task scheduling system according to any one of claims 1 to 3, characterized in that: It also includes a configuration register for storing the configuration relationship between the FPGA task scheduler, the FPGA task trigger source and the FPGA task.

5. A general FPGA task scheduling method, executed by the general FPGA task scheduling system according to any one of claims 1 to 4, characterized in that: The steps include: Set up N1 FPGA task schedulers, N2 FPGA task trigger sources, and N3 FPGA tasks; Set the FPGA task trigger source and FPGA task corresponding to each FPGA task scheduler; When a certain FPGA task trigger source meets the trigger condition, the corresponding FPGA task scheduler is triggered to execute, and the FPGA task scheduler schedules the execution of the corresponding attached FPGA task.

6. The general FPGA task scheduling method according to claim 5, characterized in that: One task scheduler can select multiple FPGA trigger sources for triggering; one FPGA task scheduler can connect multiple FPGA tasks.

7. The general FPGA task scheduling method according to claim 5 or 6, characterized in that: The FPGA task scheduler is configured with corresponding FPGA task trigger sources and FPGA tasks through a configuration interface.

8. The general FPGA task scheduling method according to any one of claims 5 to 7, characterized in that: A configuration register is set to store the configuration relationship between the FPGA task scheduler, the FPGA task trigger source and the FPGA task.

Images