A voltage-controlled processor SPUF

Abstract

The present invention discloses a voltage-controlled processor SPUF. By utilizing the low voltage characteristic, a 32-bit RISC-V processor is used to generate an abnormal information result in an abnormal working state. The abnormal information result is used to characterize the characteristics of the 32-bit RISC-V processor without special hardware overhead. The 5-bit binary data obtained by comparing the abnormal information result with the normal information result has high randomness and uniqueness. Since it is very difficult to directly extract the internal abnormal information result from the hardware circuit of the 32-bit RISC-V processor, a modeling attack that needs to calculate the 5-bit binary data of the 32-bit RISC-V processor after obtaining the abnormal information result of the 32-bit RISC-V processor is almost impossible to achieve. In addition, when the 32-bit RISC-V processor is in an abnormal working state, a frequency compensation method is used to dynamically adjust the operating frequency of the 32-bit RISC-V processor, thereby improving the stability of the PUF output response data. The advantages are good randomness and uniqueness, high security and high stability.

Description

Technical Field

[0001] The present invention relates to a processor SPUF, and in particular to a voltage-controlled processor SPUF. Background Art

[0002] As the number of connected remote embedded devices on IoT infrastructure continues to increase, IoT can make great contributions to social and economic development like the Internet, but it also faces various security threats. According to a report by Kaspersky Lab, more than 105 million IoT attacks were detected from 279,000 unique IP addresses in the first half of 2019. Most of the existing IoT security systems require high implementation costs and subsequent maintenance costs. As a lightweight security primitive, PUF generates unpredictable CRPs that provide the possibility of solving security issues on extremely resource-constrained IoT platforms.

[0003] Traditional PUF uses a dedicated circuit structure to generate an output response (i.e., a characteristic key) with randomness, uniqueness, and anti-tampering characteristics. This type of PUF that uses a hardware circuit structure to generate an output response is called a hard PUF. At present, typical hard PUFs include arbiter PUF (APUF) and ring oscillator PUF (RO PUF). Lim et al. constructed an APUF circuit using the delay changes of wires and transistors, and enhanced the APUF's anti-model attack capability by introducing nonlinear elements in the signal path. Compared with APUF, RO PUF is easier to implement layout on FPGA and has good performance. RO-PUF generates information entropy by comparing the frequency values ​​of two randomly selected oscillation loops. The entropy evaluation criteria of this circuit design are relatively simple, but the amount of information entropy is small, and the reliability of information entropy is easily affected by temperature. Lee et al. designed a leaky PUF circuit using the dependence of subthreshold leakage current on the change of transistor threshold voltage, and achieved output stability without reducing the challenge response pair (CRP) space by remapping. Taneja et al. designed a monostable PUF based on an adjustable cascode current mirror through an automated digital design process. The PUF has a hysteresis characteristic and improves the robustness of the PUF against noise, voltage, and temperature. However, in application environments such as the Internet of Things where hardware resources are extremely limited, hard PUFs are difficult to play an effective role. At the same time, hard PUFs require equipment replacement, which will increase product design and time costs. Even some hardware equipment in the Internet of Things system cannot be replaced, so hard PUFs are difficult to meet demand.

[0004] Under normal working conditions, the chip runs according to the correct logical function; however, under abnormal working conditions, its function will fail, and the abnormal information can reflect the characteristic information of the chip. This provides an opportunity for the study of soft PUF (PUF that generates output response through software program). SPUF (Software PUF) extracts hardware random process deviation through abnormal information of abnormal working of the device, establishes the response relationship between abnormal information and hardware characteristics to obtain PUF output response data, and realizes the safe application of PUF circuit without changing product design or replacing existing hardware devices. It can provide a solution to the high security problem of extremely resource-constrained systems and provide security for the development of the Internet of Things. In terms of SPUF design, Wang et al. proposed the MScanPUF solution by using the uncertainty characteristics of trigger sampling data under timing violations to solve the problem of storage PUF obtaining response, but this solution needs to add a data selector to the original scan chain structure, which has high security but poor stability. Maiti et al. proposed a processor PUF that generates PUF responses based on the error differences of multiple execution instructions of different chips under overclocking. This PUF does not require dedicated hardware overhead, but requires precise frequency changes and multiple repeated executions of instructions, making it vulnerable to side channel attacks and having poor security and stability. Chen et al. proposed a SPUF scheme based on the Camellia encryption algorithm, which produces timing violations by adjusting the operating frequency of the chip, but the cryptographic algorithm will amplify the instability of the data, so although the scheme has high security, it has poor stability. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a voltage-controlled processor SPUF with both high security and high stability.

[0006] The technical solution adopted by the present invention to solve the above technical problems is: a voltage-controlled processor SPUF, including a 32-bit RISC-V processor, wherein the 32-bit RISC-V processor has a temperature sensor for monitoring its operating temperature and a voltage sensor for monitoring its operating voltage, and the following method is used on the 32-bit RISC-V processor to generate an output response:

[0007] (1) Randomly select four groups of instructions and four groups of operands corresponding to the four groups of instructions from the R-type instructions, wherein the four groups of instructions are all 32-bit binary data, and the four groups of operands are all 64-bit binary data;

[0008] (2) The 32-bit RISC-V processor is connected to a power supply voltage, at which point the power supply voltage is the normal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters a normal working state under the normal working voltage, at which point its operating frequency is the normal working frequency. The four groups of operands are sequentially loaded into a general register using a load instruction, the four groups of instructions are sorted in order, the four groups of instructions and the corresponding four groups of operands are sequentially executed in order of sorting, at which point four normal information results corresponding to the four groups of instructions are obtained in turn, and the four normal information results are stored in the general register, the four normal information results are 32-bit binary data respectively;

[0009] (3) reducing the power supply voltage connected to the 32-bit RISC-V processor to 0.7 V. At this time, the power supply voltage is an abnormal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters an abnormal working state under the abnormal working voltage.

[0010] (4) The 32-bit RISC-V processor obtains its current operating temperature from the temperature sensor and obtains its current operating voltage from the voltage sensor, and the current operating temperature of the 32-bit RISC-V processor is recorded as temp cur , the current operating voltage of the 32-bit RISC-V processor is recorded as V cur , the compensation operating frequency of the 32-bit RISC-V processor is calculated using formula (1):

[0011]

[0012] In formula (1), temp ref is the reference temperature (temp) of the 32-bit RISC-V processor ref =25℃), V ref is the reference voltage (V ref =0.7V), F ref is the normal operating frequency of the 32-bit RISC-V processor, F com is the compensated operating frequency of the 32-bit RISC-V processor, α temp is the temperature compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor at different temperatures fluctuates with temperature; α vdd is the voltage compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor under different power supply voltages fluctuates with the voltage, and ln is a logarithmic operator;

[0013] (5) Setting the operating frequency of the 32-bit RISC-V processor to the compensation operating frequency;

[0014] (6) Use the load instruction again to load the four groups of operands into the general register in sequence, and then execute the four groups of instructions and the corresponding four groups of operands in the same order as step (2). At this time, the four exception information results corresponding to the four groups of instructions are obtained in sequence and stored in the general register. The four exception information results are also 32-bit binary data respectively.

[0015] (7) Compare the normal information results and abnormal information results corresponding to the four groups of instructions one by one, determine the number of error bits of the abnormal information results corresponding to each group of instructions relative to its normal information results, count the number of error bits, and then convert the number of error bits into 5-bit binary data, thereby obtaining four 5-bit binary data corresponding to the four groups of instructions;

[0016] (8) The four 5-bit binary data are sequentially concatenated in order from first to last and from high to low according to the execution order of their corresponding instructions to obtain 20-bit binary data, which is the output response of the SPUF.

[0017] The four groups of instructions are addition instructions, subtraction instructions, multiplication instructions and division instructions.

[0018] Compared with the prior art, the advantages of the present invention are that by utilizing the low voltage characteristics and using the 32-bit RISC-V processor in an abnormal working state to generate an abnormal information result, the abnormal information result is used to characterize the characteristics of the 32-bit RISC-V processor, no dedicated hardware overhead is required, and the 5-bit binary data obtained by comparing the abnormal information result with the normal information result has high randomness and uniqueness. Since it is very difficult to directly extract the internal abnormal information result from the hardware circuit of the 32-bit RISC-V processor, it is almost impossible to implement a modeling attack that requires calculating the 5-bit binary data of the abnormal information result of the 32-bit RISC-V processor after obtaining the abnormal information result of the 32-bit RISC-V processor. Therefore, the SPUF of the present invention has high security. In addition, when the 32-bit RISC-V processor is in an abnormal working state, the operating frequency of the 32-bit RISC-V processor is dynamically adjusted by using the frequency compensation method, thereby improving the stability of the PUF output response data. Therefore, the present invention has good randomness and uniqueness, high security and high stability, provides a solution to the high security problem of extremely resource-constrained systems, and provides security for the development of the Internet of Things. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of the working status of a 32-bit RISC-V processor under different power supply voltages;

[0020] Figure 2 The output response entropy distribution diagram of 50 SPUFs;

[0021] Figure 3 Statistical histogram and fitting curve diagram of the SPUF average HD of the present invention;

[0022] Figure 4 The autocorrelation result of the SPUF output response of the present invention;

[0023] Figure 5 is the bit error rate of the SPUF of the present invention under different power supply voltages;

[0024] Figure 6 is the bit error rate of the SPUF of the present invention at different temperatures. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to the accompanying drawings.

[0026] Embodiment: A voltage-controlled processor SPUF includes a 32-bit RISC-V processor, wherein the 32-bit RISC-V processor has a temperature sensor for monitoring its operating temperature and a voltage sensor for monitoring its operating voltage. The following method is used to generate an output response on the 32-bit RISC-V processor:

[0027] (1) Randomly select four groups of instructions and four groups of operands corresponding to the four groups of instructions from the R-type instructions, where the four groups of instructions are all 32-bit binary data and the four groups of operands are all 64-bit binary data;

[0028] (2) The 32-bit RISC-V processor is connected to the power supply voltage, at which point the power supply voltage is the normal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters the normal working state under the normal working voltage, at which point its operating frequency is the normal working frequency. The four groups of operands are sequentially loaded into the general register using the load instruction, and the four groups of instructions are sorted in order (the order can be preset), and the four groups of instructions and the corresponding four groups of operands are sequentially executed in the order of sorting, at which point four normal information results corresponding to the four groups of instructions are obtained in turn, and the four normal information results are stored in the general register, and the four normal information results are 32-bit binary data respectively;

[0029] (3) The power supply voltage connected to the 32-bit RISC-V processor is reduced to 0.7V. At this time, the power supply voltage is the abnormal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters an abnormal working state under the abnormal working voltage;

[0030] (4) The 32-bit RISC-V processor obtains its current operating temperature from the temperature sensor and its current operating voltage from the voltage sensor. The current operating temperature of the 32-bit RISC-V processor is recorded as temp cur , the current operating voltage of the 32-bit RISC-V processor is recorded as V cur , using formula (1) to calculate the compensated operating frequency of the 32-bit RISC-V processor:

[0031]

[0032] In formula (1), temp ref is the reference temperature of the 32-bit RISC-V processor (temp ref =25℃), V ref The reference voltage (V ref =0.7V), F ref is the normal operating frequency of the 32-bit RISC-V processor, F com is the compensated operating frequency of the 32-bit RISC-V processor, α temp is the temperature compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor fluctuates with temperature at different temperatures; α vdd is the voltage compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor under different power supply voltages fluctuates with the voltage, and ln is a logarithmic operator;

[0033] (5) Setting the operating frequency of the 32-bit RISC-V processor to the compensation operating frequency;

[0034] (6) Use the load instruction again to load the four groups of operands into the general register in sequence, and then execute the four groups of instructions and the corresponding four groups of operands in the same order as step (2). At this time, the four exception information results corresponding to the four groups of instructions are obtained in sequence and stored in the general register. The four exception information results are also 32-bit binary data respectively.

[0035] (7) Compare the normal information results and abnormal information results corresponding to the four groups of instructions one by one, determine the number of error bits of the abnormal information results corresponding to each group of instructions relative to its normal information results, count the number of error bits, and then convert the number of error bits into 5-bit binary data, thereby obtaining four 5-bit binary data corresponding to the four groups of instructions;

[0036] (8) The four 5-bit binary data are concatenated in sequence from first to last and from high to low according to the execution order of their corresponding instructions to obtain 20-bit binary data, which is the output response of the SPUF.

[0037] In this embodiment, the four groups of instructions are addition instructions, subtraction instructions, multiplication instructions and division instructions.

[0038] Use RISC-V instructions to activate the 32-bit RISC-V processor path, and obtain abnormal information of the 32-bit RISC-V processor under abnormal working conditions by reducing the power supply voltage and adjusting the operating frequency of the 32-bit RISC-V processor. Figure 1 As shown, analysis Figure 1 It can be seen that different power supply voltages can put the 32-bit RISC-V processor in three different working states: normal state, abnormal state and inoperable state. When the processor is in the normal state, the 32-bit RISC-V processor has a short path delay, high energy consumption, no timing violation occurs during instruction execution, and no abnormal information is generated. When the processor is in an inoperable state, instructions cannot be executed, the 32-bit RISC-V processor has the largest path delay, and energy consumption is also high due to leakage current. Therefore, the output response of the SPUF of the present invention is generated in Figure 1 In the middle gray area (abnormal state), RISC-V instructions have timing violations in some paths inside the 32-bit RISC-V processor. The 32-bit RISC-V processor has low energy consumption and large path delay, resulting in abnormal information results that carry the characteristics of the RISC-V processor.

[0039] PUF randomness is usually measured intuitively by information entropy. PUF output has two states, namely logic 1 and logic 0. Thus, information entropy E can be expressed as:

[0040]

[0041] In formula (2), p(r=0) and p(r=1) represent the probability of outputting logic 0 and logic 1 respectively. E=1 if and only if p(r=0)=p(r=1)=0.5. To further study the impact of randomization on output response, 50 Monte Carlo simulations were performed at 0.7V to simulate the random process deviations between 50 32-bit RISC-V processors, and the output responses of 50 SPUFs were counted. The output response entropy distribution of 50 SPUFs is shown in the figure below. Figure 2 As shown, analysis Figure 2It can be seen that the information entropy of each group of SPUF output responses is greater than 0.97. This shows that the SPUF output response of the present invention has very good randomness. The proportion of logic 0 and logic 1 in the output response is 50.41% and 49.59% respectively, and the corresponding randomness is 99.18%, which is close to the ideal value of 100% and has no obvious logical bias.

[0042] Uniqueness refers to the ability of PUF to obtain process deviations and to identify the differences between different SPUF individuals. The SPUF solution of the present invention measures the Hamming distance (HD) between the output responses of different individuals of the same type of SPUF. Uniqueness represents the average HD between K different SPUF individuals, which can be expressed as:

[0043]

[0044] In formula (3, k is the number of SPUFs, R i and R j are the output responses of the i-th and j-th SPUFs, HD(R i , R j ) is the Hamming distance between the i-th and j-th SPUFs. The uniqueness of the SPUF output response calculated by formula (3) is 50.1%, which is close to the ideal value of 50%, indicating that the SPUF data has no bias at all. The statistical histogram (including the fitting curve) of the average HD of the SPUF of the present invention is as follows: Figure 3 As shown, the HD distribution of the output response of 6000 Monte Carlo simulations obeys the normal distribution with mathematical expectation μ=0.5010 and standard deviation σ=0.093.

[0045] Security means that it is difficult for an adversary to predict the PUF response to a new stimulus by using the used CRPs or the CRPs of other PUFs. The NIST SP800-22 test suite and the autocorrelation test are usually used to evaluate the security of the SPUF of the present invention.

[0046] 1. NIST Test: The NIST statistical test suite can be used to evaluate the randomness of cryptographic applications and pseudo-random numbers. A 51200-bit random response sequence is generated from the test chip as the NIST input, and these inputs are divided into 50 separate bit streams and subjected to different NIST tests. The table shows the results of the SPUF output response application NIST test. The P values ​​of the generated bit streams are all greater than 0.01, and the generated sequences successfully pass all tests. The specific test data is shown in Table 1.

[0047] Table 1 NIST test

[0048]

[0049] 2. Autocorrelation test: The autocorrelation test describes the correlation between the current value and the past value of the random response sequence, and determines whether the tested PUF can generate independent and identically distributed numbers in the sequence. The present invention is tested by evaluating the autocorrelation of the 4500-bit SPUF output response. The autocorrelation result of the SPUF output response is as follows: Figure 4 shown. Figure 4 In the example, the autocorrelation test value of 0 indicates that the generated response sequence has no spatial correlation. The test results show that within the 95% confidence interval, the autocorrelation test value of the proposed SPUF is 0.022, which is close to the ideal value of 0.

[0050] System noise, supply voltage and temperature changes will lead to a decrease in the stability of PUF. In order to evaluate the effectiveness of the frequency compensation method of the present invention, we tested the bit error rate of 50 sets of calibrated SPUF output response data and 50 sets of uncalibrated SPUF output response data under different voltages. The bit error rate of SPUF under different supply voltages is shown in Figure 2. Figure 5 shown. Figure 5 In the experiment, under nominal conditions (0.7V and 20°C), without calibration, the worst bit error rate is 28%; with calibration, the worst bit error rate is 16%, so the frequency compensation method proposed in the present invention reduces the bit error rate by 1.75 times. In order to evaluate the reliability of the SPUF to temperature before and after calibration, the SPUF of the present invention is tested over a wide temperature range. The bit error rates of the SPUF of the present invention at different temperatures are shown in Figure 2. Figure 6 Analysis Figure 6 It can be seen that within the temperature variation range of -20-100°C, the worst bit error rate before calibration is 27%; after frequency compensation, the lowest bit error rate is reduced to 17%, which proves the effectiveness of the frequency compensation method proposed in the present invention.

Claims

1. A voltage-controlled processor SPUF, comprising a 32-bit RISC-V processor, characterized in that The 32-bit RISC-V processor has a temperature sensor for monitoring its operating temperature and a voltage sensor for monitoring its operating voltage. The following method is used to generate an output response on the 32-bit RISC-V processor: (1) Randomly select four groups of instructions and four groups of operands corresponding to the four groups of instructions from the R-type instructions, wherein the four groups of instructions are all 32-bit binary data, and the four groups of operands are all 64-bit binary data; (2) The 32-bit RISC-V processor is connected to a power supply voltage, at which point the power supply voltage is the normal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters a normal working state under the normal working voltage, at which point its operating frequency is the normal working frequency. The four groups of operands are sequentially loaded into a general register using a load instruction, the four groups of instructions are sorted in order, the four groups of instructions and the corresponding four groups of operands are sequentially executed in order of sorting, at which point four normal information results corresponding to the four groups of instructions are obtained in turn, and the four normal information results are stored in the general register, the four normal information results are 32-bit binary data respectively; (3) reducing the power supply voltage connected to the 32-bit RISC-V processor to 0.7 V. At this time, the power supply voltage is an abnormal working voltage of the 32-bit RISC-V processor. The 32-bit RISC-V processor enters an abnormal working state under the abnormal working voltage. (4) The 32-bit RISC-V processor obtains its current operating temperature from the temperature sensor and obtains its current operating voltage from the voltage sensor, and the current operating temperature of the 32-bit RISC-V processor is recorded as temp cur , the current operating voltage of the 32-bit RISC-V processor is recorded as V cur , the compensation operating frequency of the 32-bit RISC-V processor is calculated using formula (1): In formula (1), temp ref is the reference temperature of the 32-bit RISC-V processor, temp ref =25℃,V ref is the reference voltage of the 32-bit RISC-V processor, V ref =0.7V, F ref is the normal operating frequency of the 32-bit RISC-V processor, F com is the compensated operating frequency of the 32-bit RISC-V processor, α temp is the temperature compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor at different temperatures fluctuates with temperature; α vdd is the voltage compensation coefficient of the 32-bit RISC-V processor, which is determined by testing the speed at which the delay of the 32-bit RISC-V processor under different power supply voltages fluctuates with the voltage, and ln is a logarithmic operator; (5) Setting the operating frequency of the 32-bit RISC-V processor to the compensation operating frequency; (6) Use the load instruction again to load the four groups of operands into the general register in sequence, and then execute the four groups of instructions and the corresponding four groups of operands in the same order as step (2). At this time, the four exception information results corresponding to the four groups of instructions are obtained in sequence and stored in the general register. The four exception information results are also 32-bit binary data respectively. (7) Compare the normal information results and abnormal information results corresponding to the four groups of instructions one by one, determine the number of error bits of the abnormal information results corresponding to each group of instructions relative to its normal information results, count the number of error bits, and then convert the number of error bits into 5-bit binary data, thereby obtaining four 5-bit binary data corresponding to the four groups of instructions; (8) The four 5-bit binary data are sequentially concatenated in order from first to last and from high to low according to the execution order of their corresponding instructions to obtain 20-bit binary data, which is the output response of the SPUF.

2. A voltage-controlled processor SPUF according to claim 1, characterized in that The four groups of instructions are addition instructions, subtraction instructions, multiplication instructions and division instructions.

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