Method and apparatus for configuring chip, device, and storage medium

Abstract

Embodiments of the present application disclose a method and device for configuring a chip, equipment and a storage medium. The method comprises: obtaining winding information of a wiring area corresponding to a functional unit; determining a blank area in the wiring area which is not wound according to the winding information; and increasing the width of a power line already arranged on the wiring area by using the blank area, so as to reduce the resistance voltage drop of a power network already arranged above the functional unit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the chip design field, and relate to but are not limited to a method and device for configuring a chip, equipment and a storage medium. BACKGROUND

[0002] The problem of IR drop has always existed in a chip. If the global IR drop of the chip is too high, the logic gate may malfunction, which makes the chip completely fail, although the logic simulation shows that the design is correct. If the local IR drop is too high (which usually occurs under some specific conditions, such as all bus data are flipped synchronously), the chip may intermittently exhibit some functional failures. Even if the above extreme situation does not occur, the IR drop will still cause the reduction of the computing speed of the chip. Experiments show that 5% IR drop on a logic gate unit will reduce the normal gate speed by 15%. With the evolution of semiconductor technology to the deep submicron level, the problem of IR drop has become a bottleneck of chip design. How to reduce the IR drop has become a problem that chip designers have to consider. SUMMARY

[0003] Therefore, the method and device for configuring a chip, equipment and a storage medium provided by embodiments of the present application make full use of the blank area of the unwound wiring layer to widen the power line, thereby reducing the IR drop of the power network and improving the computing speed of the chip. The method and device for configuring a chip, equipment and a storage medium provided by embodiments of the present application are implemented as follows:

[0004] The method for configuring a chip provided by embodiments of the present application comprises: obtaining wiring information of a wiring area corresponding to a functional unit; determining a blank area in the wiring area which is not wound according to the wiring information; and increasing the width of a power line already disposed on the wiring area by using the blank area, so as to reduce the IR drop of a power network already disposed above the functional unit.

[0005] The device for configuring a chip provided by embodiments of the present application comprises: an obtaining module configured to obtain wiring information of a wiring area corresponding to a functional unit; a determining module configured to determine a blank area in the wiring area which is not wound according to the wiring information; and an enhancing module configured to increase the width of a power line already disposed on the wiring area by using the blank area, so as to reduce the IR drop of a power network already disposed above the functional unit.

[0006] The electronic device provided by embodiments of the present application comprises a memory and a processor. The memory stores a computer program which can run on the processor. When the processor executes the program, the method provided by embodiments of the present application is implemented.

[0007] The computer readable storage medium provided in the embodiment of the present application has a computer program stored thereon, and the computer program is executed by a processor to implement the method provided in the embodiment of the present application.

[0008] In the embodiment of the present application, the blank area in the wiring area above the functional unit is fully utilized, the width of the deployed power supply line in the wiring area is widened, the resistance voltage drop of the deployed power supply network above the functional unit is reduced without increasing the chip area, and the computing speed of the chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0009] The drawings incorporated into the specification and forming a part of the specification, show embodiments consistent with the present application, and are used to explain the technical solutions of the present application together with the specification.

[0010] Figure 1 The schematic diagram of the wiring of each layer of the chip;

[0011] Figure 2 The schematic diagram of the pre-planned power supply / ground (Power / Ground, PG) line in the Mth layer above the memory unit;

[0012] Figure 3 The schematic diagram of the implementation process of the method for configuring the chip in the embodiment of the present application;

[0013] Figure 4 The schematic diagram of the implementation process of another method for configuring the chip in the embodiment of the present application;

[0014] Figure 5 The schematic diagram of the implementation process of still another method for configuring the chip in the embodiment of the present application;

[0015] Figure 6 The schematic diagram of the width of the power supply line in the embodiment of the present application;

[0016] Figure 7 The schematic diagram of the wasted space above the memory unit;

[0017] Figure 8 The schematic diagram of a wiring layer of the enhanced power supply network in the embodiment of the present application;

[0018] Figure 9 The structural schematic diagram of the device for configuring the chip in the embodiment of the present application;

[0019] Figure 10 The structural schematic diagram of the electronic device in the embodiment of the present application. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0023] It should be noted that the terms "first, second, third" used in the embodiments of this application are used to distinguish similar or different objects and do not represent a specific order of objects. It can be understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0024] In chip design, the number of wiring metal layers typically ranges from 4 to 15, but is not limited to this. Wiring directions within the same layer are consistent, and the wiring directions of adjacent layers are perpendicular. For example, Figure 1 As shown, the wiring direction of layer Mn 102 is vertical, while the wiring directions of the two adjacent layers above and below, namely layer Mn-1 101 and layer Mn+1 103, are horizontal. This is a basic rule for wiring in chip design.

[0025] During their research, the inventors discovered that the utilization rate of the PG network (i.e., the power network consisting of power lines and ground lines) in the wiring area above the relevant memory units was only about 15%. This means that the pre-planned PG lines (i.e., power lines and ground lines) accounted for about 15% of the wiring resources, and the remaining space needed to be reserved for signal line deployment. For example, Figure 2 As shown, the pre-planned PG lines in the Mn layer above the storage cell account for only about 15% of the wiring resources of this wiring layer.

[0026] However, the number of signal lines passing over the space above the storage cells is not entirely consistent. Some areas with more standard cells require more signal lines to cross the space above the storage cells, while some corner storage cells have almost no signal lines above them. Therefore, the space above these storage cells has neither power lines nor signal lines, and these wiring areas are obviously wasted.

[0027] Therefore, the embodiment of the present application provides a method for configuring a chip, aiming at making full use of the routing resources above the functional units such as storage units, enhancing the power network above the functional units without any cost, and reducing the resistance voltage drop of the power network.

[0028] The method can be applied to an electronic device, which can be a mobile phone, a tablet computer, a notebook computer, a desktop computer or any device with information processing capability. The function realized by the method for configuring a chip can be realized by calling program code by a processor in the electronic device, and of course the program code can be saved in a computer storage medium. It can be seen that the electronic device at least includes a processor and a storage medium.

[0029] Figure 3 The implementation flowchart of the method for configuring a chip provided by the embodiment of the present application is shown in FIG. 1. Figure 3 As shown in FIG. 1, the method can include the following steps 301 to 303:

[0030] Step 301, obtaining the routing information of the corresponding routing area above the functional unit.

[0031] In some embodiments, the routing information of the corresponding routing area above the functional unit can be obtained from a configured chip map. The configured chip map can be a design map in which the partial or complete basic power network and signal network of the chip have been deployed. For example, the configured chip map is a chip layout that meets the tapeout standard. The basic power network refers to a power network that meets the basic requirement of resistance voltage drop. For example, a power network with a resistance voltage drop of no more than 5%.

[0032] In the embodiment of the present application, the functional unit can be various. In some embodiments, the functional unit can be a device group unit occupying a relatively large chip area (for example, greater than a certain threshold). For example, the functional unit is a static storage unit or a processor unit.

[0033] It can be understood that the functional unit composed of devices is usually deployed at the bottom layer of the chip, and the routing layer above the functional unit is deployed with signal networks and power networks. The corresponding routing area above the functional unit can be an area with a size comparable to the functional unit, or a routing area covering the functional unit and having an area greater than the size of the functional unit. The range of the routing area is not limited in the embodiment of the present application.

[0034] In some embodiments, the electronic device can obtain the routing area of each routing layer above the functional unit, and increase the width of the deployed power line in the blank area of the routing area, so as to realize the enhancement of the power network and reduce the resistance voltage drop of the deployed power network.

[0035] In the embodiments of the present application, the type of the power supply line is not limited. The power supply line can be a power line or a ground line.

[0036] In step 302, according to the wire information, a blank area without wire in the wire region is determined.

[0037] In some embodiments, the wire information of the wire region can include attribute information of the wire segments such as power supply lines and signal lines deployed on the wire region. The attribute information of the wire segment can include the position, length and width of the wire segment.

[0038] It can be understood that the blank area without wire refers to an area without any wire segment deployed in the wire region.

[0039] In step 303, the width of the power supply line deployed on the wire region is increased by using the blank area, so as to reduce the resistance voltage drop of the power supply network deployed above the functional unit.

[0040] It should be noted that the way of increasing the width of the power supply line can be various. For example, a power supply line with a width greater than the existing power supply line in parallel is deployed on the blank area, so that the resistance voltage drop can be effectively reduced, and several power supply lines can be saved, thereby shortening the chip configuration period; for another example, one or more other power supply lines with the same width in parallel with the deployed power supply line are generated on the blank area, so as to widen the deployed power supply line.

[0041] In the embodiments of the present application, the blank area without wire in the wire region above the functional unit is fully utilized to widen the width of the power supply line deployed on the wire region, so as to reduce the resistance voltage drop of the power supply network deployed above the functional unit without increasing the chip area, thereby improving the computing speed of the chip.

[0042] It can be understood that the resistance voltage drop refers to the resistance voltage drop of the metal line between the power supply point and the device. The greater the voltage drop, the smaller the voltage from the power supply point to the device (i.e. the voltage triggering the device to work); the smaller the voltage triggering the device to work, the slower the working speed of the device, for example, the opening speed of the metal oxide semiconductor field effect (MOS) tube, and accordingly, the computing speed of the chip is also slower.

[0043] Ideally, we want the voltage at the power supply point to remain unchanged after reaching the device. However, in reality, due to the resistance (voltage drop) of the metal line between the power supply point and the device, the voltage at the power supply point decreases upon reaching the device, thus slowing down the device's turn-on speed. Therefore, in this embodiment, by enhancing the deployed power network, the resistance voltage drop of the original power network can be reduced, thereby improving the chip's computing speed.

[0044] This application embodiment further provides a method for configuring a chip. Figure 4 A schematic diagram illustrating the implementation flow of the chip configuration method in the embodiments of this application is shown below. Figure 4 As shown, the method may include the following steps 401 to 404:

[0045] Step 401: Obtain the layout data of the chip layout that meets the submission manufacturing standards;

[0046] Step 402: Obtain the wiring information of the wiring area corresponding to the functional unit above the layout data.

[0047] In the embodiments of this application, the functional unit is typically a collection of device units that occupy a relatively large chip area (e.g., greater than a certain threshold). For example, the functional unit is a static storage unit.

[0048] Understandably, in this embodiment, power network enhancement is performed close to tapeout, meaning that power lines are added to the blank areas above functional units to increase the width of the deployed power lines, while the overall chip configuration is basically frozen and meets the tapeout standards. In this way, large-scale manual modification of integrated circuits (Engineer Changing Order, ECO) is avoided, and the resistance voltage drop of the original power network above functional units can be reduced without affecting chip performance, thereby improving chip computing speed.

[0049] Step 403: Based on the winding information, determine the blank areas in the wiring area that are not wound;

[0050] Step 404: Determine the target power line that meets the conditions from the power lines already deployed in the wiring area.

[0051] In some embodiments, the condition can be each power line that has been routed on the routing area. That is, each power line that has been routed on the routing area is a target power line. In other embodiments, the condition can also be a resistance value greater than a resistance value threshold or a length greater than a length threshold. That is, in some embodiments, the electronic device can implement step 404 by determining a resistance value of each power line that has been routed on the routing area; determining a power line with a resistance value greater than a resistance threshold as the target power line; and / or, determining a length of each power line that has been routed on the routing area; determining a power line with a length greater than a length threshold as the target power line.

[0052] It can be appreciated that the greater the resistance value of a power line, the greater the resistance voltage drop generated by the power line. The longer the power line, the greater the resistance value of the power line, and accordingly, the greater the resistance voltage drop generated by the power line. In view of this, in some embodiments, only the power line with a resistance value greater than a resistance threshold or the power line with a length greater than a length threshold is widened, instead of each power line that has been routed on the routing area. In this way, the resistance voltage drop of the routed power network can be effectively reduced even without widening each power line that has been routed on the routing area, thereby reducing the resistance voltage drop of the power network while shortening the chip configuration period.

[0053] Step 405, on the blank area of the routing area, routing at least one other power line in parallel with the target power line to increase the width of the target power line, thereby reducing the resistance voltage drop of the routed power network above the functional unit.

[0054] In the embodiments of the present application, the widening of the target power line is achieved by routing at least one other power line in parallel with the target power line on the blank area of the corresponding routing area above the functional unit. In this way, the widening of the target power line can be achieved without modifying the original power network. It can be seen that this design is relatively simple and easy to implement, and the method can reduce the resistance voltage drop of the routed power network above the functional unit while shortening the chip configuration period.

[0055] The embodiments of the present application further provide a method for configuring a chip, Figure 5 The implementation flowchart of the method for configuring a chip in the embodiments of the present application is shown in FIG. 5, which can include the following steps 501 to 507: Figure 5

[0056] Step 501, obtaining layout data of a chip layout that meets a submission standard;

[0057] Step 502, obtaining routing information of a routing area corresponding to the functional unit from the layout data.

[0058] ​In the application embodiment, the functional unit is usually a device collection unit with a relatively large chip area (e.g., greater than a certain threshold). For example, the functional unit is a static storage unit.

[0059] In some embodiments, the reasonable wiring sequence should be: first, deploy the global power network (i.e., the power network before enhancement), and then deploy the global signal network; finally, according to the actual situation, locally increase some power lines. In this way, without introducing ECO, the chip resistance voltage drop can be reduced and the chip performance can be improved. It can be seen that, in the application embodiment, the power network enhancement based on the chip layout can meet the requirement of the above wiring sequence.

[0060] Step 503, determining a blank area in the wiring area according to the winding information;

[0061] Step 504, determining the resistance value of each power line already deployed on the wiring area.

[0062] In some embodiments, the length and cross-sectional area of each power line already deployed on the wiring area are determined; and the resistance value of the corresponding power line is determined according to the length and cross-sectional area of each power line.

[0063] It can be understood that the line width required for connecting different devices to the power supply point can be different. The larger the line width, the smaller the resistance value, and the smaller the corresponding resistance voltage drop. Even if the line connected to the power supply point is long, it can also not need to be widened. Therefore, in this embodiment, the resistance value of the power line is determined based on the length and cross-sectional area of the power line, so that the power lines that actually need to be widened can be selected, and the resistance voltage drop of the deployed power network can also be effectively reduced by widening fewer power lines, thereby shortening the chip configuration period.

[0064] Step 505, determining the power line with a resistance value greater than the resistance threshold as the target power line;

[0065] Step 506, deploying at least one other power line parallel to the target power line in the blank area of the wiring area;

[0066] Step 507, adding a via at the end point of the other power line to connect the other power line with a power line located in an adjacent wiring layer of the wiring layer of the other power line and perpendicular to the target power line, so that the other power line is connected in parallel with the target power line. In this way, the width of the target power line is equivalent to being increased, thereby reducing the resistance voltage drop of the power network already deployed above the functional unit.

[0067] Understandably, in a chip, the wiring direction remains constant across each layer, and the wiring directions of adjacent layers are perpendicular. For example, Figure 2 As shown, the wiring direction of layer Mn 202 is vertical, while the wiring directions of the adjacent upper and lower layers, namely layer Mn-1 201 and layer Mn+1 203, are horizontal. Therefore, in this embodiment, by adding through-holes at the endpoints of other power lines, it is possible to connect the power line to the power lines in the two adjacent layers above and below it that are perpendicular to the target power line, thereby realizing the parallel connection of the other power lines and the target power line.

[0068] For example, such as Figure 6 As shown, assuming there are wiring layers 601 to 604 above the functional unit, taking power supply point A0 on wiring layer 601 as an example, in the deployed power network, such as Figure 6 As shown in (a), the original traces from power supply point A0 to the underlying device D0 include segments A0B0, B0C0, and C0D0. Using the chip configuration method described above, a new segment A parallel to segment A0B0 was finally added to the wiring layer 601. 11 B 11 and line segment A 12 B 12 A new line segment B, parallel to line segment B0C0, was added to the wiring layer 602. 21 C 21 and line segment B 22 C 22 A new line segment C parallel to line segment C0D0 was added to the wiring layer 603. 31 D 31 On line segment B 21 C 21 and line segment B 22 C 22 For example, adding a through hole at the end point, such as Figure 6 As shown in (b), by punching holes at both ends of these newly added line segments, these line segments can be connected to line segments A0B0 and C0D0, which are perpendicularly connected to the original line segment B0C0, thereby realizing the connection of line segment B. 21 C 21 Line segment B 22 C 22 Parallel to line segment B0C0.

[0069] It can be understood that the resistance voltage drop refers to a phenomenon of voltage drop or rise on the power supply network in the integrated circuit. With the evolution of semiconductor technology, the width of the metal interconnection line becomes narrower, resulting in the increase of its resistance value, so there will be a certain resistance voltage drop in the entire chip range. The size of the resistance voltage drop is determined by the size of the equivalent resistance between the power supply point and the calculated logic gate unit. The more the metal lines in parallel between the power supply point and the device, the smaller the equivalent resistance between them, and the smaller the resistance voltage drop.

[0070] It can be seen that in the embodiment of the present application, the blank area above the functional unit is increased with sufficient power lines, so as to equivalently widen the width of the target power line in parallel with the newly added power line, thereby reducing the equivalent resistance between the power supply point and the device, and further effectively reducing the resistance voltage drop of the power supply network already deployed above the functional unit, and improving the calculation speed of the chip.

[0071] The exemplary application of the embodiment of the present application in an actual application scenario will be described below.

[0072] The inventor found in the research process that the number of space signal lines above the storage unit is not completely consistent. As shown in Figure 7 , some areas with more standard units need to cross more signal lines above the storage unit, while some storage units in the corners have almost no signal lines, so the space above these storage units has neither power lines nor signal lines, obviously these areas are wasted.

[0073] Therefore, in the embodiment of the present application, a method for configuring a chip is provided, and the implementation steps are as follows:

[0074] Step 1) The entire design (Design) is basically frozen, basically meeting the standard for submission to manufacturing, and no large-scale ECO will occur.

[0075] That is, in the embodiment of the present application, the power supply network enhancement can be performed after the chip map has been completely configured, that is, before it is submitted to the chip manufacturer. That is, the power supply network enhancement is performed in the last stage before the chip map is submitted to the chip manufacturer.

[0076] Step 2) The power supply network enhancement step above the storage unit is implemented on the chip map output in step 1), which is realized by a script, and the blank area is inserted with PG lines according to certain rules to enhance the power supply network, as shown in Figure 7 ; Figure 8

[0077] Step 3) Adjust the density of the inserted PG lines according to the actual situation.

[0078] ​In practical applications, the number of inserted power lines can be determined according to actual engineering requirements, that is, the density of inserted PG lines is adjusted.

[0079] Step 4) Punching, completing the penetration of each layer of PG lines.

[0080] The method for configuring a chip provided in the embodiments of the present application can enhance the power network without any cost, thereby effectively reducing the resistance voltage drop of the chip.

[0081] In the embodiments of the present application, 1) the blank area above the storage unit without wiring is fully utilized to enhance the power network; 2) an automatic implementation script is developed without increasing any workload; and 3) the enhancement of the power network is performed before the chip is delivered to the manufacturer, so that the chip performance is not affected and the resistance voltage drop is reduced.

[0082] Based on the foregoing embodiments, the embodiments of the present application provide a device for configuring a chip, which comprises the modules included and the units included in the modules, and can be implemented by a processor in an electronic device; of course, it can also be implemented by a specific logic circuit; in the implementation process, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0083] Figure 9 The structural schematic diagram of the device for configuring a chip in the embodiments of the present application is shown in FIG. 9, which comprises an acquisition module 901, a determination module 902, and an enhancement module 903; wherein, Figure 9

[0084] The acquisition module 901 is configured to acquire the wiring information of the wiring area corresponding to the functional unit.

[0085] The determination module 902 is configured to determine the blank area without wiring in the wiring area according to the wiring information.

[0086] The enhancement module 903 is configured to increase the width of the power line already arranged on the wiring area by using the blank area, so as to reduce the resistance voltage drop of the power network already arranged above the functional unit.

[0087] In some embodiments, the acquisition module 901 is configured to: acquire the layout data of a chip layout meeting the delivery standard; and acquire the wiring information of the wiring area corresponding to the functional unit from the layout data.

[0088] ​In some embodiments, the enhancement module 903 is configured to: determine a target power line that meets the conditions from the power lines already deployed on the wiring area; and deploy at least one other power line in parallel with the target power line in a blank area of ​​the wiring area to increase the width of the target power line.

[0089] In some embodiments, the determining module 902 is configured to: determine the resistance value of each power line deployed in the wiring area; determine power lines with resistance values ​​greater than a resistance threshold as the target power lines; and / or determine the length of each power line deployed in the wiring area; determine power lines with lengths greater than a length threshold as the target power lines.

[0090] In some embodiments, the determining module 902 is configured to: determine the length and cross-sectional area of ​​each power line deployed in the wiring area; and determine the resistance value of the corresponding power line based on the length and cross-sectional area of ​​each power line.

[0091] In some embodiments, the enhancement module 903 is configured to: add through-holes at the endpoints of the other power lines to connect the other power lines to a power line located in an adjacent wiring layer of the wiring layer of the other power lines and perpendicular to the target power line, thereby connecting the other power lines in parallel with the target power line.

[0092] In some embodiments, the functional unit is a static storage unit.

[0093] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0094] It should be noted that, in the embodiments of this application... Figure 9 The module division of the configuration chip device shown is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, exist as separate physical units, or be integrated into one unit with two or more units. The integrated units can be implemented in hardware, as software functional units, or a combination of both.

[0095] Correspondingly, such as Figure 10As shown, the electronic device 100 provided by the embodiments of the present application can include a memory 1001 and a processor 1002, the memory 1001 stores a computer program executable on the processor 1002, and the processor 1002 implements the steps in the method provided by the embodiments of the present application when executing the program.

[0096] The memory 1001 is configured to store instructions executable by the processor 1002 and applications, and can also cache data (for example, image data, audio data, voice communication data and video communication data) to be processed by the processor 1002 and each module in the electronic device 100, which has been processed or has been processed, and can be implemented by a FLASH or a Random Access Memory (RAM).

[0097] It should be noted that in the embodiments of the present application, if the method of configuring the chip is implemented in the form of a software function module and is sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a plurality of instructions for causing an electronic device to execute all or part of the method described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a Read Only Memory (ROM), a magnetic disk or an optical disk, and various media that can store program codes. Thus, the embodiments of the present application are not limited to any specific hardware and software combination.

[0098] The embodiments of the present application provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps in the method of configuring the chip provided in the embodiments of the present application.

[0099] The embodiments of the present application provide a computer program product containing instructions, which, when executed on a computer, cause the computer to perform the method of configuring the chip provided by the method embodiments.

[0100] It should be noted that: the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects to the method embodiments. For technical details not disclosed in the storage medium, chip and terminal device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0101] It should be understood that the term "one embodiment" or "an embodiment" or "some embodiments" as used herein means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, the appearances of the phrase "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described in the various embodiments of the present application does not mean that the execution order of the processes is prior or posterior, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The sequence of the above embodiments of the present application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0102] It should be noted that the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0103] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The embodiments of the touch screen system described above are merely illustrative, for example, the division of the modules is only a logical functional division, and actual implementation can have another division manner, for example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0104] The modules described above as separate components can or can not be physically separate, and the components shown as modules can or can not be physical modules; they can be located in one place or distributed on multiple network units; and some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiments.

[0105] In addition, each functional module in each embodiment of the present application can be integrated in one processing unit, or each module can be a separate unit, or two or more modules can be integrated in one unit. The integrated modules can be implemented in the form of hardware or hardware plus software function units.

[0106] Those skilled in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the foregoing program can be stored in a computer readable storage medium. When the program is executed, the steps of the method embodiments are executed. The storage medium includes mobile storage devices, read-only memory (ROM), magnetic discs or optical discs, and various storage medium that can store program codes.

[0107] Alternatively, when the integrated units of the present application are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of software products, which are stored in a storage medium and include a number of instructions for causing an electronic device to execute all or part of the methods described in the embodiments of the present application. The storage medium includes mobile storage devices, ROM, magnetic discs or optical discs, and various storage medium that can store program codes.

[0108] The methods disclosed in the several method embodiments of the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0109] The features disclosed in the several product embodiments of the present application can be combined arbitrarily without conflict to obtain new product embodiments.

[0110] The features disclosed in the several method or device embodiments of the present application can be combined arbitrarily without conflict to obtain new method or device embodiments.

[0111] The above is only an implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of configuring a chip, the method comprising: The method comprises: obtaining winding information of a corresponding wiring area above the functional unit; determining, according to the winding information, a blank area in the wiring area which is not wound; increasing the width of the power lines already arranged on the wiring area by using the blank area, so as to reduce the resistance voltage drop of the power network already arranged above the functional unit; wherein the increasing the width of the power lines already arranged on the wiring area by using the blank area comprises: determining the resistance of each power line already arranged on the wiring area; determining the power line whose resistance is greater than a resistance threshold value as a target power line; and / or determining the length of each power line already arranged on the wiring area; determining the power line whose length is greater than a length threshold value as the target power line; arranging at least one other power line in parallel with the target power line on the blank area of the wiring area.

2. The method of claim 1, wherein, The obtaining winding information of a corresponding wiring area above the functional unit comprises: obtaining layout data of a chip layout which meets a delivery manufacturing standard; and obtaining the winding information of the corresponding wiring area above the functional unit from the layout data.

3. The method of claim 1, wherein, The determining the resistance of each power line already arranged on the wiring area comprises: determining the length and cross-sectional area of each power line already arranged on the wiring area; and determining the resistance of the corresponding power line according to the length and cross-sectional area of each power line.

4. The method of claim 1, wherein, The arranging at least one other power line in parallel with the target power line on the blank area of the wiring area comprises: adding a via at the end point of the other power line, so as to connect the other power line with a power line which is located in an adjacent wiring layer of the wiring layer of the other power line and is perpendicular to the target power line, thereby making the other power line parallel to the target power line.

5. The method according to any one of claims 1 to 4, characterized in that, The functional unit is a static storage unit.

6. An apparatus for configuring a chip, the apparatus comprising: comprise: an obtaining module, configured to obtain winding information of a corresponding wiring area above a functional unit; a determining module, configured to determine, according to the winding information, a blank area in the wiring area which is not wound; an enhancing module, configured to increase the width of the power lines already arranged on the wiring area by using the blank area, so as to reduce the resistance voltage drop of the power network already arranged above the functional unit; wherein the increasing the width of the power lines already arranged on the wiring area by using the blank area comprises: determining the resistance of each power line already arranged on the wiring area; determining the power line whose resistance is greater than a resistance threshold value as a target power line; and / or determining the length of each power line already arranged on the wiring area; determining the power line whose length is greater than a length threshold value as the target power line; arranging at least one other power line in parallel with the target power line on the blank area of the wiring area.

7. An electronic device comprising a memory and a processor, the memory storing a computer program operable on the processor, characterized in that, The processor implements the method in any one of claims 1 to 5 when executing the program.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the method in any one of claims 1 to 5 when executed by a processor.

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