Reverse bias optimization

Abstract

This application relates to reverse bias optimization. A device, such as an electronic device, may include a first substrate region and a second substrate region. The device may also include a voltage generator disposed on the first substrate region and including an output terminal coupled to a conductive path. The device may further include a set of clamping circuitry disposed on the second substrate region. The set of clamping circuitry may be configured to selectively couple the conductive path to a voltage supply.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 096,225, entitled “BACK-BIAS OPTIMIZATION,” filed November 12, 2020, by Brox et al., which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves reverse bias optimization. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states and can store any of them. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods even without external power. Volatile memory devices (e.g., DRAM) may lose their stored state when disconnected from external power. Summary of the Invention

[0006] An apparatus is described. The apparatus may include: a first substrate region and a second substrate region; a voltage generator disposed on the first substrate region and including an output terminal coupled to a conductive path; and a plurality of clamping circuits disposed on the second substrate region, each of the plurality of clamping circuits being configured to couple the conductive path to a voltage supply.

[0007] An apparatus is described. The apparatus may include: a first substrate region and a second substrate region; a voltage generator disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages being used to bias at least a transistor in the second substrate region; and a plurality of clamping circuits disposed on the second substrate region and coupled to the voltage generator, wherein each of the plurality of clamping circuits is configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages being used to bias the transistor.

[0008] An apparatus is described. The apparatus may include: a first voltage generator disposed on a first substrate region, the first voltage generator being configured to generate a first voltage and a second voltage for biasing a transistor in a second substrate region; a second voltage generator disposed on the first substrate region, the second voltage generator being configured to generate the first voltage and the second voltage for biasing the transistor; and a clamping circuit disposed on the second substrate region at least partially surrounded by the first substrate region, and configured to provide a third voltage and a fourth voltage for biasing the transistor. Attached Figure Description

[0009] Figure 1 This document describes an example of a system that supports back bias optimization based on the examples disclosed herein.

[0010] Figure 2 This document describes an example of a device that supports reverse bias optimization based on the examples disclosed herein.

[0011] Figure 3A and 3B This document describes an example of a process flow that supports reverse bias optimization based on the examples disclosed in this article. Detailed Implementation

[0012] For example, devices in electronic devices can apply bias voltages to various electronic components to prevent or mitigate harmful electrical phenomena. For instance, a device can apply a bias voltage to the body (or "back side") of a transistor to mitigate current leakage. This process can be called reverse biasing. Devices employing reverse biasing can include bias circuitry comprising a voltage generator and clamping circuitry, each providing different reverse bias voltages for different scenarios. Due to their size and complexity, the bias circuitry can be placed on a substrate region of the device that is relatively unconstrained by component placement (e.g., a fully custom region). Conductive paths can couple the bias circuitry to various transistors, some of which can be placed on another substrate region (e.g., a semi-custom region) subject to relatively restrictive component placement constraints. However, due to the length of the conductive paths or the limited ability of the generator to locally control various conditions, the reverse bias voltage generated on one or more conductive paths may vary at different points on one or more conductive paths, which can negatively impact the effectiveness of reverse biasing.

[0013] According to the techniques described herein, variations in bias voltage along conductive paths can be reduced, for example, by placing clamping circuits at various intervals along one or more conductive paths within a semi-custom region. The size and simplicity of the clamping circuits relative to one or more voltage generators allow for placement within a semi-custom region, meaning that the bias voltage along the conductive path can be anchored (or “clamped”) at various points along the conductive path by the clamping circuits, thereby reducing variations, and other advantages. Therefore, the effectiveness of reverse bias can be improved.

[0014] Firstly, in reference Figure 1 The features of this disclosure are described within the context of the system being described. (Referencing...) Figure 2 Features of this disclosure are described in the context of the described apparatus. These and other features of this disclosure are illustrated by reference to [reference needed]. Figure 3A and 3B The process flow related to reverse bias optimization is further explained and described.

[0015] Figure 1 This document describes an example of a system 100 that supports inverse bias optimization, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0016] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system, operable to store data from one or more other components of system 100.

[0017] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0018] Memory device 110 may be a standalone device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0019] Memory device 110 is operable to store data of components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0020] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using bus 135.

[0021] Processor 125 is operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by processor 125 or may be part of processor 125.

[0022] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0023] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package or multi-chip memory or multi-chip package.

[0024] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions enabling the memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0025] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0026] Local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, local memory controller 165 is operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155 and local memory controller 165, or external memory controller 120 may perform the various functions described herein. Thus, local memory controller 165 is operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0027] External memory controller 120 is operable to enable communication of one or more of the following: information, data, or commands between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret the communication exchanged between a component of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is described as being external to memory device 110, in some instances, external memory controller 120, or the functionality described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0028] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to act as part of a channel.

[0029] Channel 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or double data rate (DDR) signaling can be used to convey signaling through channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal can be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal can be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0030] System 100 may include various electronic components (e.g., switching components, such as transistors) for operation. To prevent transistor leakage current (a phenomenon that negatively impacts transistor performance), system 100 may apply a bias voltage to the body (or "back") of the transistor. This technique may be referred to as "reverse bias." Because different reverse bias voltages may be preferred for different scenarios, system 100 may include a voltage generator that provides a first set of reverse bias voltages (e.g., analog voltages) and a clamping circuit that provides a second set of reverse bias voltages (e.g., circuit supply voltages). The voltage generator and clamping circuit may be coupled together and, due to the size and complexity of the resulting circuit, may be placed on a substrate region with relatively few restrictions on component placement. For example, the combination of the voltage generator and clamping circuit may be placed on a substrate region (referred to as a "fully customized region") that is desired for relatively unrestricted customization in memory production or design.

[0031] A combination of a voltage generator and clamping circuitry (collectively referred to herein as bias circuitry) can be used to supply a reverse bias voltage to transistors (e.g., the entire device), including transistors disposed on a substrate region that is relatively constrained by component placement limitations. For example, transistors may be disposed on a substrate region (referred to as a “semi-custom region”) that is desired for relatively restricted customization. To facilitate reverse biasing of these and other transistors, the device may include one or more conductive paths coupling the transistors to the voltage generator and clamping circuitry. In some instances, the conductive paths may traverse (e.g., span) the semi-custom region and therefore may have non-trivial lengths that affect reverse bias. For example, the reverse bias voltage along the conductive path may vary at different points based on the electrical distance from the voltage generator / clamping circuitry (e.g., the reverse bias voltage may vary with the midpoint length of the conductive path). Therefore, the reverse bias voltage applied to the transistors in the semi-custom region (and other regions that may be alternative examples) may be inconsistent, which can negatively impact the effectiveness of the reverse bias.

[0032] According to the techniques described herein, the device of system 100, for example, can reduce the variation of reverse bias voltage along one or more conductive paths by using one or more clamping circuits distributed along conductive paths within a semi-custom region. Because the relative length of the conductive paths between the clamping circuits is reduced compared to using voltage generators, the voltage along the conductive paths can be more consistent compared to other techniques that use one or more voltage generators / clamping circuits outside the semi-custom region. Therefore, the effectiveness of reverse bias can be improved.

[0033] Figure 2 This document describes an example of a device 200 supporting reverse bias optimization, based on the examples disclosed herein. Device 200 may be used as a reference. Figure 1Examples of the described system 100 or memory device 110. However, the techniques described herein are not limited to the devices described herein and can be implemented by any type of device having one or more substrate regions. Device 200 may include voltage generators 205-a, 205-b, and clamping circuits 210-a to 210-d, as well as other components. Clamping circuits 210 may be distributed (e.g., positioned) along conductive path 220 such that the reverse bias voltage at different points along the conductive path may have reduced variation (e.g., more uniform) compared to other techniques.

[0034] Although described with reference to two conductive paths 220, the techniques described herein can be implemented for any number of conductive paths (including a single conductive path). A conductive path may also be referred to as a conductive line or trace, and other suitable terms. If a conductive path contains switching components (e.g., one or more transistors located along one or more conductive paths), then the conductive path can be considered an active conductive path.

[0035] Device 200 may include multiple substrate regions (e.g., portions, segments, regions) with different characteristics and / or design constraints. For example, device 200 may include substrate region 215-a, which may be a fully custom region, and substrate region 215-b, which may be a semi-custom region. In addition to other characteristics described herein, substrate region 215-a may have minimal or no restrictions on the placement or size of components or wiring, while substrate region 215-b may have various restrictions for the placement of components and wiring. In some instances, substrate region 215-b may have a wiring grid, while substrate region 215-a may not have a wiring grid. In some instances, substrate region 215-b may be configured as a pattern (e.g., a matrix) of sub-regions (or “blocks”) subject to placement constraints. Figure 2 As described herein, substrate region 215-a may at least partially or completely surround substrate region 215-b. However, other configurations of substrate region 215 are taken into account and fall within the scope of this disclosure.

[0036] Voltage generator 205 can generate (e.g., provide, create, supply, output) reverse bias voltages for components of device 200 (e.g., transistors disposed on substrate region 215-b, and other substrate regions). For example, voltage generator 205 can generate a first voltage, referred to as "VPW," for biasing a first type of transistor, such as an n-type transistor, and a second voltage, referred to as "VNW," for biasing a second type of transistor, such as a p-type transistor. In some instances, the reverse bias voltage generated by voltage generator 205 can be an analog voltage based on one or more supply voltages, analog voltages, and / or pump-assisted voltages received by voltage generator 205. In some instances, VPW is a negative voltage, and VNW is a positive voltage. Voltage generator 205 can include various components (including large and complex components such as voltage pumps and comparators) to generate VNW and VPW.

[0037] Although described with reference to two voltage generators 205, the techniques described herein can be implemented for any number of voltage generators (including a single voltage generator or more than two voltage generators). Similarly, the techniques described herein can be implemented for any number of reverse bias voltages. For example, the techniques described herein can be implemented for a single reverse bias voltage (e.g., VNW or VPW) generated by voltage generator 205.

[0038] Voltage generator 205 may be powered by one or more supply voltages and may be controlled by digital control signals received from a controller, such as controller 245. Controller 245 may be configured to control (e.g., enable, disable, activate, deactivate) any combination of voltage generator 205 and clamping circuit 210. Therefore, controller 245 may be coupled to one or more of voltage generators 205 and one or more of clamping circuits 210. In some instances, one or both of voltage generators 205 may include or be coupled to a corresponding clamping circuit (not shown), which may be internal or external to voltage generator 205. In this scenario, the clamping circuit may be said to be located on substrate region 215-a.

[0039] Voltage generator 205 can be used independently or in combination to generate a reverse bias voltage on conductive path 220. For example, voltage generator 205 can generate VNW on conductive path 220-a and VPW on conductive path 220-b. Using multiple voltage generators 205 as shown can reduce the variation of VNW and VPW along the conductive lines; however, the use of a single voltage generator 205 is also contemplated. The voltage on conductive path 220 can be propagated to various components of device 200 via a distributed network (not shown) that may include one or more conductive lines, activatable conductive paths, and the like.

[0040] Clamping circuit 210 can be used, for example, to provide a reverse bias voltage, such as an alternative reverse bias voltage, when VPW and VNW are unsuitable or too high for a given application or implementation. For example, each clamping circuit 210 can provide a reverse bias voltage called VNW for a reverse-biased n-type transistor. DD The first alternative voltage, and can provide a voltage called V for the reverse biased p-type transistor. SS The second alternative voltage. The alternative voltage can be based on the circuit's normal or nominal supply voltage, such as voltage supply VDD and voltage supply VSS.

[0041] Therefore, the clamping circuit 210 can be coupled to one or more supply voltages. Alternate voltage V DD It can be lower than VNW and replace voltage V SS It can be higher than VPW. Therefore, compared with VNW and VPW, the alternative voltage V is used. DD V SS This can lead to higher transistor performance (e.g., larger drive current), but also higher transistor leakage. Therefore, the alternative voltage V... DD V SS Suitable for low-leakage scenarios. However, in high-leakage scenarios, VNW and VPW are superior to the alternative voltage V. DD V SS Examples of low-leakage and high-leakage scenarios are described below. Compared to the large, complex voltage generator 205 that contains multiple analog inputs, the clamping circuit 210 can be small, simple, and includes digital inputs.

[0042] like Figure 2 The description indicates that the number of clamping circuits 210 in device 200 may be greater than the number of voltage generators 205. Although described with reference to four clamping circuits 210, the techniques described herein can be implemented for any number of clamping circuits. Similarly, the techniques described herein can be implemented for any number of alternative reverse bias voltages. For example, the techniques described herein can be implemented for a single alternative reverse bias voltage (e.g., V). DD or V SS (or can be implemented for multiple reverse bias voltages.)

[0043] Due to the size and complexity of the voltage generator 205, and the constraints of the substrate region 215-b, the voltage generator 205 can be disposed on the substrate region 215-a. For example, the voltage generator 205 can be disposed on the substrate region 215-a because it is difficult or, in some embodiments, impossible to place the voltage generator 205 in the substrate region 215-b, even using automated placement and routing (APR) tools. However, since the clamping circuit 210 is relatively simple and small compared to the voltage generator 205, the clamping circuit 210 can be disposed within the substrate region 215-b. Distributing the clamping circuit 210 along the conductive path 220 reduces the variation in bias voltage at different points on the conductive path 220, which increases the effectiveness of reverse bias.

[0044] As mentioned, clamping circuit 210 can be used to couple conductive path 220 to voltage supply (e.g., VDD, VSS) to replace reverse bias voltage (e.g., V DD V SS This is generated on the conductive line. For example, clamping circuit 210 can couple conductive path 220-a to voltage supply VDD and conductive path 220-b to voltage supply VSS when properly activated. Therefore, clamping circuit 210 can have multiple sub-circuits 225 for coupling conductive path 220. As an illustration, clamping circuit 210-a can include sub-circuit 225-a, which can be configured to couple conductive path 220-a to VDD, and clamping circuit 210-b, which can be configured to couple conductive path 220-b to VSS.

[0045] Sub-circuit 225-a may include transistors 230-a, 235-a, and 240-a, which can be activated and deactivated by applying an appropriate voltage. Transistor 240-a can be activated to couple conductive path 220-a to VDD. Transistor 240-a can be deactivated by transistor 230-a and activated by transistor 235-a to achieve a sufficiently low voltage (e.g., VDD). SS The transistor is activated by applying a common voltage (e.g., V) to the gate of transistor 230-a and the gate of transistor 235-a. DD Transistor 230-a can be deactivated, and transistor 235-a can be activated (e.g., simultaneously, for at least a partially overlapping duration). Therefore, the gate of transistor 240-a can be isolated from VNW and coupled to VSS, which can cause transistor 240-a to conduct (e.g., transferring charge / current from VDD to conduction path 220-a). To isolate conduction path 220-a from VDD, the voltage applied to transistors 230-a and 235-a can be modified (e.g., to V...). SSThis activates transistor 230-a and deactivates transistor 235-a. Therefore, the gate of transistor 240-a can be isolated from VSS and coupled to VNW, which can cause transistor 240-a to turn off.

[0046] Sub-circuit 225-b can operate similarly to sub-circuit 225-a. For example, to couple conductive path 220-b to VSS, transistor 240-b can be activated. Transistor 240-b can achieve a sufficiently high voltage (e.g., VSS) by activating transistor 230-a and deactivating transistor 235-a. DD ) is activated by applying a common voltage (e.g., V) to the gate of transistor 230-b and the gate of transistor 235-b. SS Transistor 230-b can be activated, and transistor 235-b can be deactivated (e.g., simultaneously). Therefore, the gate of transistor 240-b can be coupled to VDD and isolated from VPW, which can cause transistor 240-b to conduct (e.g., transfer charge / current from VSS to conduction path 220-b). To isolate conduction path 220-b from VSS, the voltage applied to transistors 230-b and 235-b can be modified (e.g., to VDD). DD This deactivates transistor 230-b and activates transistor 235-b. Therefore, the gate of transistor 240-b can be isolated from VDD and coupled to VPW, which can cause transistor 240-b to turn off. Although described with reference to transistors, sub-circuit 225 can be implemented using any type of switching component.

[0047] As mentioned, controller 245 can be configured to control the bias mode of device 200 by enabling and disabling voltage generator 205 and clamping circuit 210. In some instances, controller 245 can be configured to enable voltage generator 205 and clamping circuit 210 (or any combination thereof) at different times, such that when voltage generator 205 is enabled, clamping circuit 210 is disabled, and vice versa. For example, when a high leakage scenario is detected (e.g., determined, measured), controller 245 can be configured to select and enter a first bias mode, which may include enabling voltage generator 205 (e.g., to compensate for increased current leakage) and disabling clamping circuit 210 (e.g., because clamping circuit 210 is not needed).

[0048] One example of a high leakage scenario is when device 200 undergoes aging, which can be a mode that puts stress on device 200 (e.g., to allow the manufacturer to address a point of failure) (e.g., a test mode). Because high temperature and high pressure increase current leakage, operating modes that increase the operating temperature and / or operating voltage of device 200 (e.g., aging test modes) can be associated with increased current leakage. Another example of a high leakage scenario is when device 200 has a fast process corner. The term fast process corner can refer to a switching component (e.g., a transistor) with a low threshold voltage and therefore a fast switching time (relative to the nominal values ​​of the threshold voltage and switching time).

[0049] When encountering a low-leakage scenario, controller 245 can be configured to select and enter a second bias mode, which may include enabling clamping circuit 210 and disabling voltage generator 205. The second bias mode provides sufficient reverse bias for the low-leakage scenario but with reduced power consumption compared to the first bias mode. One example of a low-leakage scenario is when device 200 operates in a mode different from the aging test mode. Another example of a low-leakage scenario is when device 200 has a slow process corner, meaning that device 200 has switching components (e.g., transistors) with high threshold voltages and therefore slower switching times (relative to the nominal values ​​of threshold voltage and switching time). In some instances, entering the second bias mode may occur before entering the first bias mode. Alternatively, in some instances, entering the second bias mode may occur after entering the first bias mode.

[0050] Therefore, controller 245 can determine which bias mode to enable based on the operating mode of device 200 and / or based on the switching characteristics of the transistors in device 200 (e.g., threshold voltage, switching speed) and other factors or conditions. Although shown separate from substrate region 215, controller 245 may be partially or wholly located on one or both of substrate regions 215.

[0051] Therefore, the distributed clamping circuit 210 can be used to reduce the variation of the reverse bias voltage along the conductive path 220.

[0052] In some instances, controller 245 or another circuit (e.g., circuitry on the memory of device 200) may select a bias mode based on the temperature of the memory, which may be measured by controller 245 or the other circuitry. For example, when the memory temperature reaches a threshold temperature, device 200 may switch from a second bias mode (which may be referred to as a “clamping mode”) to a first bias mode (which may be referred to as a “generator mode”). Alternatively or concurrently, the bias mode may be controlled by measurement circuitry (e.g., a ring oscillator) characterizing the process angle of device 200. For example, the ring oscillator on device 200 may measure the oscillation frequency of various aspects of device 200. If the oscillation frequency satisfies a threshold frequency associated with or indicating a fast process angle, then device 200 may select the first bias mode for use. Otherwise, device 200 may select the second bias mode for use.

[0053] Figure 3A This document describes an example of a process flow 300 supporting reverse bias optimization, based on the examples disclosed herein. Process flow 300-a can be implemented by devices and / or controllers as described herein. Process flow 300-a allows devices with one or more voltage generators and one or more distributed clamping circuits to strategically enable / disable the voltage generators and clamping circuits based on the device's operating mode.

[0054] At 305, the device may determine the operating mode of the device. In some instances, the device may determine the operating mode based on a mode register contained in the device and using one or more bits to indicate the operating mode. Alternatively, the device may determine the operating mode based on an instruction received from another device. For example, the device may receive (e.g., from a host device) an instruction that indicates the operating mode of the device to be used. In some instances, the device may determine the operating mode based on whether the device is turned on or out of a low-power mode. At 310, the device may determine whether the device is in an aging test mode (or another operating mode associated with high leakage).

[0055] If at 310, the device determines that it is in an aging test mode, then at 315, the device can select a first bias mode based on the fact that the device is in an aging test mode. At 320, the device can enable the voltage generator and disable the clamping circuit based on the selection of the first bias mode. Therefore, when the device is in an aging test mode, the device can effectively reverse bias the transistors of the device.

[0056] If at 310, the device determines that it is in a mode different from the aging test mode, then at 325, the device can select a second bias mode based on the fact that it is in a mode different from the aging test mode. At 330, the device can disable the voltage generator and enable the clamping circuit based on the selection of the second bias mode. Therefore, compared to the first bias mode, the device can save power while effectively reverse biasing the transistors of the device when it is in a mode different from the aging test mode.

[0057] In summary, the device can strategically enable / control the voltage generator and clamping circuit based on the device's operating mode.

[0058] Figure 3B This document describes an example of a process flow 300-b that supports reverse bias optimization, based on the examples disclosed herein. Process flow 300-b can be implemented by devices and / or controllers as described herein. Process flow 300-b allows devices with one or more voltage generators and one or more distributed clamping circuits to strategically enable / disable the voltage generators and clamping circuits based on the device's process corner. In some instances, process flow 300-b may follow or be used in conjunction with process flow 300-a.

[0059] In section 335, the device can determine the type of process corner associated with the device. In some instances, the device can determine the type of process corner based on a fuse or other circuitry included in the device and indicating the type of process corner. Thus, a fuse can directly or indirectly indicate the switching characteristics of transistors in the device (e.g., threshold voltage, switching speed). A fuse can refer to circuitry permanently or semi-permanently configured to be in an open or closed state. Therefore, the state of the fuse can indicate the type of process corner associated with the device (e.g., an open-circuit fuse can indicate a fast process corner, while a closed-circuit fuse can indicate a slow process corner).

[0060] In some instances, the device may use on-die measurement circuitry (e.g., circuitry on the device's memory die or other components) to determine the type of process corner. For example, the device may determine the type of process corner based on the temperature of the memory die, which may be determined by on-die temperature measurement circuitry. As another example, the device may determine the type of process corner based on the oscillation frequency of one or more components, such as that measured by a ring oscillator.

[0061] At 340, the device can determine whether it is associated with a rapid process corner.

[0062] If at 340, the device determines that it is associated with a fast process corner, then at 345, the device can select a first bias mode based on this association. When using on-die measurement circuitry, the device can determine its association with a fast process corner based on the memory die (or another die) temperature meeting a threshold temperature and / or the memory die (or other component) oscillation frequency meeting a threshold frequency. At 350, the device can enable the voltage generator and disable the clamping circuitry based on the selection of the first bias mode. Therefore, the device can effectively reverse bias transistors of a device with low threshold voltage and / or fast switching characteristics.

[0063] If at 340, the device determines that it is associated with a process corner other than the fast process corner (e.g., a slow process corner), then at 350, the device can select a second bias mode based on the association with the process corner other than the fast process corner. When using on-die measurement circuitry, the device can determine its association with a process corner other than the fast process corner based on the memory die (or another die) temperature not meeting a threshold temperature and / or based on the memory die (or other component) oscillation frequency not meeting a threshold frequency. At 355, the device can disable the voltage generator and enable the clamping circuitry based on the selection of the second bias mode. Therefore, compared to the first bias mode, the device can save power while effectively reverse biasing the transistors of the device with a higher threshold voltage and / or slow switching characteristics (relative to the threshold).

[0064] In summary, the device can strategically enable / control the voltage generator and clamping circuit based on the device's process angle.

[0065] In some instances, the device may switch between a first bias mode and a second bias mode one or more times based on the device's operating mode and / or process angle. In some instances, the device may use the first bias mode to reverse bias a first type of switching component and may use the second bias mode to reverse bias a second type of switching component. In such instances, the first and second bias modes may be enabled simultaneously (e.g., for at least partial overlap). In some instances, the device may select between the first and second bias modes based on the device's power state (e.g., based on the device's remaining battery power or based on access to power). In some instances, the device may select between the first and second bias modes based on a desired performance level for reverse biasing.

[0066] It should be noted that the techniques and methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0067] An apparatus is described. The apparatus may include: a first substrate region and a second substrate region; a voltage generator disposed on the first substrate region and including an output terminal coupled to a conductive path; and a plurality of clamping circuits disposed on the second substrate region, each of the plurality of clamping circuits being configured to couple the conductive path to a voltage supply.

[0068] In some instances, the device includes clamping circuitry disposed on a first substrate region and coupled to a voltage generator.

[0069] In some instances, the device includes a controller coupled to a voltage generator and a plurality of clamping circuits, the controller being configured to independently enable and disable the voltage generator and the plurality of clamping circuits.

[0070] In some instances of the device, the controller may be configured to enable or disable the voltage generator and multiple clamping circuits, at least in part, based on the device’s operating mode.

[0071] In some instances, the device may include a mode register configured to indicate the operating mode of the device, wherein the controller may be configured to enable or disable the voltage generator and a plurality of clamping circuits based at least in part on the operating mode indicated by the mode register.

[0072] In some instances, the device may include a fuse configured to indicate the switching nature of transistors in the device, wherein the controller may be configured to enable or disable a voltage generator and a plurality of clamping circuits at least in part based on the switching nature.

[0073] In some instances, the device may include a second conductive path coupled to a second output terminal of a voltage generator, wherein a plurality of clamping circuits may be configured to couple the second conductive path to a second voltage supply. In some instances of the device, each of the plurality of clamping circuits includes a first transistor coupled to the conductive path and the voltage supply, and a second transistor coupled to the second conductive path and the second voltage supply.

[0074] In some instances, the device includes a second voltage generator disposed on a first substrate region and including an output terminal coupled to a conductive path. In some instances, the voltage generator and the second voltage generator may be located on opposite sides of the second substrate region.

[0075] In some instances of the device, the conductive path spans the entire length of the second substrate region, and multiple clamping circuits are distributed along the conductive path. In some instances of the device, the second substrate region may be at least partially surrounded on both sides by the first substrate region.

[0076] In some instances of the device, the second substrate region may be subject to a set of constraints on which one or more wirings or components are placed, while the first substrate region does not comply with the set of constraints. In some instances of the device, the second substrate region may be a peripheral substrate region comprising a matrix subregion that may be subject to the set of constraints, and each clamping circuit may be disposed on a corresponding subregion of the matrix subregion.

[0077] Another device is described. The device may include: a first substrate region and a second substrate region; a voltage generator disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages being used to bias at least a transistor in the second substrate region; and a plurality of clamping circuits disposed on the second substrate region and coupled to the voltage generator, wherein each of the plurality of clamping circuits is configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages being used to bias the transistor.

[0078] In some instances of the device, a first conductive path may be coupled to a first type of transistor, and a second conductive path may be coupled to a second type of transistor.

[0079] In some instances of the device, the first type of transistor contains p-type transistors, and the second type of transistor contains n-type transistors.

[0080] In some instances, the device may include a controller configured to individually enable a voltage generator during a first duration and individually enable multiple clamping circuits during a second duration, which may not overlap with the first duration. In some instances, the controller may be configured to enable the voltage generator and disable the multiple clamping circuits at least in part based on determining that the device may be in a test mode. In some instances, the controller may be configured to enable the voltage generator and disable the multiple clamping circuits at least in part based on determining that the transistors may have a switching speed equal to or faster than a threshold switching speed. In some instances, the controller may be configured to enable the multiple clamping circuits and disable the voltage generator at least in part based on determining that the transistors may have a switching speed slower than a threshold switching speed.

[0081] In some instances, the device may include a controller configured to select a first bias mode or a second bias mode based at least in part on the switching properties of the transistors or the device's operating mode, wherein the controller may be configured to enable or disable a voltage generator and a plurality of clamping circuits based at least in part on the selected bias mode. In some instances of the device, the first voltage may be higher than a third voltage, and the second voltage may be lower than a fourth voltage.

[0082] Another device is described. The device may include: a first voltage generator disposed on a first substrate region, the first voltage generator being configured to generate a first voltage and a second voltage for biasing a transistor in a second substrate region; a second voltage generator disposed on the first substrate region, the second voltage generator being configured to generate the first voltage and the second voltage for biasing the transistor; and a clamping circuit disposed on the second substrate region at least partially surrounded by the first substrate region, and configured to provide a third voltage and a fourth voltage for biasing the transistor.

[0083] In some instances, the device may include a first conductive path coupled to a first voltage generator and a second voltage generator, wherein the first voltage generator and the second voltage generator may each be configured to generate a first voltage on the first conductive path. In some instances, the device may include a first voltage supply coupled to a clamping circuit, wherein the clamping circuit may be configured to provide a third voltage from the first voltage supply to the first conductive path.

[0084] In some instances, the device may include a second conductive path coupled to a first voltage generator and a second voltage generator, wherein the first voltage generator and the second voltage generator may each be configurable to generate a second voltage on the second conductive path. In some instances, the device may include a second voltage supply coupled to a clamping circuit, wherein the clamping circuit may be configured to provide a fourth voltage from the second voltage supply to the second conductive path.

[0085] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, which may have multiple bit widths.

[0086] The terms “electronic connectivity,” “conductive contact,” “connection,” and “coupling” refer to the relationship between components that support signal flow between them. Components are considered electronically connected (or electrically contacted, connected, or coupled) to each other if there are any conductive paths between them that can support signal flow at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacted, connected, or coupled) may be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0087] The term "coupling" refers to the condition that changes from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0088] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then they are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive paths that previously allowed signal flow. As used herein, the term "substantially" means that a modified characteristic (e.g., a verb or adjective modified by the term "substantially") does not need to be absolute but is close enough to achieve the advantages of the characteristic.

[0089] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0090] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degraded) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "off" or "deactivated".

[0091] The descriptions set forth herein, taken in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to other instances." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0092] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0093] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0094] For example, the various illustrative blocks and modules described in this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but in alternative embodiments, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0095] As used herein, the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") encompasses the contents of the claims, indicating a list such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0096] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave), then the definition of media includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (e.g., infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0097] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for reverse biasing, comprising: First substrate region and second substrate region; A voltage generator is disposed on the first substrate region and includes an output terminal coupled to a conductive path; Multiple clamping circuits are disposed on the second substrate region, each of the multiple clamping circuits being configurable to couple the conductive path to a voltage supply; and A controller coupled to the voltage generator and the plurality of clamping circuits, the controller being configured to independently enable and disable the voltage generator and the plurality of clamping circuits.

2. The device according to claim 1, further comprising: A clamping circuit is disposed on the first substrate region and coupled to the voltage generator.

3. The device of claim 1, wherein the controller is configured to enable or disable the voltage generator and the plurality of clamping circuits at least in part based on the operating mode of the device.

4. The device according to claim 1, further comprising: A mode register configured to indicate the operating mode of the device, wherein the controller is configured to enable or disable the voltage generator and the plurality of clamping circuits based at least in part on the operating mode indicated by the mode register.

5. The device according to claim 1, further comprising: A fuse configured to indicate the switching characteristics of transistors in the device, wherein the controller is configured to enable or disable the voltage generator and the plurality of clamping circuits at least in part based on the switching characteristics.

6. The device according to claim 1, further comprising: A second conductive path is coupled to a second output terminal of the voltage generator, wherein the plurality of clamping circuits are configured to couple the second conductive path to a second voltage supply.

7. The device according to claim 1, further comprising: A second voltage generator is disposed on the first substrate region and includes an output terminal coupled to the conductive path.

8. The device of claim 7, wherein the voltage generator and the second voltage generator are on opposite sides of the second substrate region.

9. The device of claim 1, wherein the conductive path spans the entire length of the second substrate region, and the plurality of clamping circuits are distributed along the conductive path.

10. The device of claim 1, wherein the second substrate region is at least partially surrounded on both sides by the first substrate region.

11. The device of claim 1, wherein the second substrate region is subject to a set of constraints for placing one or more wirings or components, and the first substrate region does not comply with the set of constraints.

12. The device of claim 11, wherein the second substrate region is a peripheral substrate region comprising a matrix subregion constrained by the group constraints, and wherein each clamping circuit is disposed on a corresponding subregion of the matrix subregion.

13. A device for reverse biasing, comprising: A first substrate region and a second substrate region, the second substrate region being configured for components smaller than a threshold size; A voltage generator disposed on the first substrate region and including an output terminal coupled to a conductive path, the voltage generator being larger than the threshold size; Multiple clamping circuits are disposed on the second substrate region, each of the multiple clamping circuits being configured to couple the conductive path to the voltage supply and each being smaller than the threshold size; and A second conductive path is coupled to a second output terminal of the voltage generator, wherein the plurality of clamping circuits are configured to couple the second conductive path to a second voltage supply, and each of the plurality of clamping circuits includes: A first transistor, which is coupled to the conductive path and the voltage supply; and The second transistor is coupled to the second conductive path and the second voltage supply.

14. A device for reverse biasing, comprising: First substrate region and second substrate region; A voltage generator is disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages being used to bias at least a transistor in the second substrate region. and A plurality of clamping circuits are disposed on the second substrate region and coupled to the voltage generator, wherein each of the plurality of clamping circuits is configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages being used to bias the transistor, wherein the first voltage is higher than the third voltage and the second voltage is lower than the fourth voltage.

15. The device of claim 14, wherein the first conductive path is coupled to a transistor of a first type, and the second conductive path is coupled to a transistor of a second type.

16. The device of claim 15, wherein the transistor of the first type comprises a p-type transistor, and the transistor of the second type comprises an n-type transistor.

17. The device according to claim 14, further comprising: A controller configured to enable the voltage generator individually during a first duration and the plurality of clamping circuits individually during a second duration that does not overlap with the first duration.

18. The device of claim 17, wherein the controller is configured to: The voltage generator is enabled and the plurality of clamping circuits are disabled, at least in part, based on the determination that the device is in test mode.

19. The device of claim 17, wherein the controller is configured to: The plurality of clamping circuits are enabled and the voltage generator is disabled, at least in part, based on the determination that the transistor has a switching speed slower than the threshold switching speed.

20. The device according to claim 14, further comprising: A controller configured to select a first bias mode or a second bias mode based at least in part on the switching properties of the transistor or the operating mode of the device, wherein the controller is configured to enable or disable the voltage generator and the plurality of clamping circuits based at least in part on the selected bias mode.

21. A device for reverse biasing, comprising: A first substrate region and a second substrate region, the second substrate region being configured for components smaller than a threshold size; A voltage generator, larger than the threshold size, is disposed on the first substrate region and configured to generate a first voltage on a first conductive path and a second voltage on a second conductive path, the first and second voltages being used to bias at least a transistor in the second substrate region. and A plurality of clamping circuits are disposed on the second substrate region and coupled to the voltage generator, wherein each of the plurality of clamping circuits is smaller than the threshold size and configured to provide a third voltage to the first conductive path and a fourth voltage to the second conductive path, the third and fourth voltages being used to bias the transistor; and A controller configured to individually enable the voltage generator during a first duration and individually enable the plurality of clamping circuits during a second duration that does not overlap with the first duration, wherein the controller is configured to: The voltage generator is enabled and the plurality of clamping circuits are disabled, at least in part, based on the determination that the transistor has a switching speed equal to or faster than a threshold switching speed.

22. A device for reverse biasing, comprising: A first voltage generator is disposed on a first substrate region, and the first voltage generator is configured to generate a first voltage and a second voltage for biasing transistors in a second substrate region. A second voltage generator is disposed on the first substrate region, and the second voltage generator is configured to generate the first voltage and the second voltage for biasing the transistor. and A clamping circuit is disposed on a second substrate region at least partially surrounded by the first substrate region and is configured to provide a third voltage and a fourth voltage for biasing the transistor.

23. The device according to claim 22, further comprising: A first conductive path is coupled to a first voltage generator and a second voltage generator, wherein the first voltage generator and the second voltage generator are each configured to generate the first voltage on the first conductive path; and A first voltage supply coupled to the clamping circuit, wherein the clamping circuit is configured to provide the third voltage from the first voltage supply to the first conductive path.

24. The device according to claim 23, further comprising: A second conductive path is coupled to the first voltage generator and the second voltage generator, wherein the first voltage generator and the second voltage generator are each configured to generate the second voltage on the second conductive path; and A second voltage supply coupled to the clamping circuit, wherein the clamping circuit is configured to provide the fourth voltage from the second voltage supply to the second conductive path.

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