Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a first bonding layer on a first wafer, and forming an etching mask on the first bonding layer; etching an edge portion of the first bonding layer using the etching mask, and exposing a portion of the first wafer; removing the etching mask; and fixing a second wafer to the first bonding layer. The etching mask is not only used for partially etching the first bonding layer and the first wafer, but also used for protecting the bonding layer so that a surface of the bonding layer can be maintained smooth. Therefore, in the wafer bonding process, the bonding layer provides excellent bonding effect so as to facilitate fixing the second wafer on the first wafer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of manufacturing a semiconductor device. BACKGROUND

[0002] Currently, three-dimensional integrated circuits (3D-IC) have wide applications and developments in semiconductor packaging, in which multiple semiconductor wafers are stacked with each other, such as package-on-package (PoP) and system-in-package (SiP) packaging technologies. Some advantages of three-dimensional integrated circuit assemblies include smaller footprint and lower power consumption by reducing the length of signal interconnections, thereby improving yield and reducing manufacturing cost.

[0003] With the development of semiconductor technology, wafer-to-wafer bonding or wafer-to-wafer bonding technology is applied to three-dimensional integrated circuit assemblies. For example, in wafer-to-wafer bonding technology, many methods have been developed to bond two wafers together.

[0004] Therefore, how to provide an effective wafer bonding technology to calibrate the position between wafers has become one of the important issues. SUMMARY

[0005] Therefore, how to provide an effective wafer bonding technology to calibrate the position between wafers has become one of the important issues.

[0006] In one or more embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes forming an integrated circuit structure on the first wafer, wherein the integrated circuit structure is located between the first wafer and the first bonding layer.

[0007] In one or more embodiments of the present disclosure, the integrated circuit structure includes a substrate and a via through the substrate.

[0008] In one or more embodiments of the present disclosure, the via contacts a first conductive feature of the first bonding layer.

[0009] In one or more embodiments of the present disclosure, a width of the via is less than a width of the conductive feature.

[0010] In one or more embodiments of the present disclosure, the first bonding layer includes a dielectric layer and a first conductive feature through the dielectric layer.

[0011] In one or more embodiments of the present disclosure, forming the etching mask includes forming a photoresist layer on the first bonding layer, and performing an edge trimming process to remove an edge portion of the photoresist layer.

[0012] In one or more embodiments of the application, securing the second wafer to the first bonding layer includes: contacting the second bonding layer on the second wafer to the first bonding layer; and bonding the first bonding layer and the second bonding layer.

[0013] In one or more embodiments of the application, the first conductive feature within the first bonding layer contacts the second conductive feature within the second bonding layer.

[0014] In one or more embodiments of the application, the width of the first conductive feature is equal to the width of the second conductive feature.

[0015] In summary, the etching mask is not only used for partially etching the first bonding layer and the first wafer, but also used for protecting the bonding layer, so that the surface of the bonding layer can be kept smooth. Therefore, in the wafer-to-wafer process, the first wafer and the bonding layer can provide excellent bonding effect.

[0016] The above descriptions are only used to explain the problems to be solved by the present application, technical means for solving the problems, and effects thereof, and specific details of the present application will be described in the embodiments and related drawings below. BRIEF DESCRIPTION OF DRAWINGS

[0017] To achieve the above-mentioned advantages and features, the principles described above will be explained in more detail with reference to the embodiments, and the specific embodiments are shown in the drawings. These drawings only illustratively describe the present application, and therefore do not limit the scope of the application. Through the drawings, the principles of the present application will be clearly explained, and additional features and details will be fully described, wherein:

[0018] Figure 1 a flowchart illustrating a method of manufacturing a semiconductor device in some embodiments of the present application; and

[0019] Figures 2 to 7 illustrating each step of a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0020] In the following, several embodiments of the present application will be disclosed with reference to the drawings. For the purpose of clear illustration, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present application. That is, in some embodiments of the present application, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in the drawings in a simple schematic manner.

[0021] Reference will now be made to Figure 1 , Figure 1A method 100 for manufacturing a semiconductor device is illustrated in some embodiments of the present invention. Method 100 begins at step 110, wherein step 110 includes forming a first bonding layer on a first wafer and forming an etch mask on the first bonding layer. Next, method 100 proceeds to step 130, wherein step 130 includes etching an edge portion of the first bonding layer using the etch mask, thereby exposing a portion of the first wafer. Next, method 100 proceeds to step 150, wherein step 150 includes removing the etch mask. Method 100 continues to step 170, wherein step 170 includes securing a second wafer to the first bonding layer.

[0022] Figures 2 to 7 Cross-sectional views illustrating various steps of a method 100 for manufacturing a semiconductor device 200 in some embodiments of the present invention. Figures 2 to 4 Used to represent graphically Figure 1 Step 110 in the document. Please refer to... Figures 2 to 4 A first bonding layer 230 is formed on the first wafer 210, and an etch mask 240 is formed on the first bonding layer. Therefore, the first bonding layer 230 is disposed between the first wafer 210 and the etch mask 240. Specifically, the first wafer 210 can be a semiconductor substrate, such as a doped (p-type doped or n-type doped) or undoped bulk semiconductor. In some embodiments, the first wafer 210 is a silicon wafer or other suitable substrate, such as a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate. The semiconductor material of the first wafer 210 may include silicon, germanium, or compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, alloy semiconductors, or combinations thereof. Various electronic components (e.g., transistors, capacitors) can be used to meet the structural and functional requirements designed into the first wafer 210. In some embodiments, the first wafer 210 does not have through semiconductor vias, depending on design requirements. In other embodiments, through semiconductor vias are formed in the first wafer 210.

[0023] In some embodiments of the present application, the first bonding layer 230 can include a first dielectric layer 231 and a plurality of first conductive features 233 extending through the first dielectric layer 231, wherein the first dielectric layer 231 covers the first conductive features 233. The first dielectric layer 231 includes a dielectric material, such as silicon oxide, and can be formed by spin-coating, laminating or other suitable deposition techniques, followed by patterning the dielectric material to form the first dielectric layer 231 having a plurality of openings (not shown). For example, the first dielectric layer 231 can be patterned using photolithography and etching processes or other suitable processes. Then, the first conductive features 233 are formed in the plurality of openings of the first dielectric layer 231 by electroplating, deposition processes, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) or other suitable deposition processes, but the present application is not limited thereto.

[0024] In some embodiments of the present application, forming the etch mask 240 includes forming a photoresist layer 241 on the first bonding layer 230, and performing an edge trim process to remove an edge portion 241a of the photoresist layer 241. In particular, the edge portion 241a includes an edge bead, and includes a wafer edge exposure (WEE) or an edge bead removal (EBR) process, such as an optical edge bead removal process or a chemical edge bead removal process including applying a propylene glycol methyl ether acetate (PGMEA) solution or a ethylene glycol monomethyl ether acetate (EGMEA) solution to the photoresist layer 241. The etch mask 240 can be an unpatterned photoresist mask, but the present application is not limited thereto.

[0025] In some embodiments of the application, the method 100 further comprises a step 120, which is performed before the step 130, wherein the step 120 comprises forming an integrated circuit structure 220 on the first wafer 210, and the integrated circuit structure 220 is disposed between the first wafer 210 and the first bonding layer 230. In particular, the integrated circuit structure 220 comprises a logic die, such as a central processing unit, a graphics processing unit, or a memory die (e.g., a dynamic random access memory die or a static random access memory die, etc.), a power management die, a radio frequency die, a sensing die, a microelectromechanical system die, or a combination thereof. In some specific embodiments, the memory and / or the electronic control functions can be integrated in the same integrated circuit structure 220. In some embodiments, the integrated circuit structure 220 comprises a semiconductor substrate 221 and a plurality of through semiconductor vias (TSVs) 223, which extend through the semiconductor substrate 221, although the application is not limited thereto.

[0026] In some embodiments of the application, an interconnection structure is formed between the first wafer 210 and the integrated circuit structure 220. The via 223 in the first wafer 210 can be electrically connected to the via 223 of the integrated circuit structure 220 through the interconnection structure.

[0027] In some embodiments of the application, the plurality of vias 223 are respectively electrically connected to the plurality of first conductive features 233 of the first bonding layer 230. For example, the plurality of vias 223 respectively contact the plurality of first conductive features 233 of the first bonding layer 230, although the application is not limited thereto.

[0028] In some embodiments of the application, the width of each via 223 is greater than the width of each first conductive feature 233 in the first bonding layer 230. In some alternative embodiments, the width of each via 223 is greater than the width of each first conductive feature 233, although the application is not limited thereto.

[0029] Please refer to Figure 4 and Figure 5 . Figure 4 and Figure 5 may be used to graphically represent Figure 1At step 130 in FIG. 1, step 130 includes etching and removing edge portions 235 of the integrated circuit structure 220 and the edge portions 235 of the first bonding layer 230 using the etch mask 240, thereby exposing a portion of the first wafer 210. In some embodiments of the present application, the edge portions 235 and the edge portions 235 can be removed, for example, by a dry etching anisotropic etching process. In some embodiments, the dry etching can be a reactive ion etch (RIE), a plasma etch process, or any suitable etching process, without limitation. In some examples, the etch mask 240 can at least protect the first bonding layer 230 from contamination by the anisotropic etching process. As a result, the first bonding layer 230 has a smooth surface, that is, the surface of the first bonding layer 230 has few defects.

[0030] Referring to Figure 5 and Figure 6 , Figure 5 and Figure 6 may be used to graphically represent Figure 1 step 150 in FIG. 1, where step 150 includes removing the etch mask 240. In particular, a planarization process can be implemented in conjunction with an end point detection to remove the etch mask 240, and the planarization process can include a mechanical grinding process and / or a chemical mechanical polishing process (CMP) or other suitable process, without limitation.

[0031] Referring to Figure 6 and Figure 7 . Figure 6 and Figure 7 may be used to graphically represent Figure 1 Figure 6 Figure 7 Figure 6 Figure 7 Figure 1In some embodiments of the present application, step 170 further includes contacting the first bonding layer 230 to a second bonding layer 330 on the second wafer 310, and bonding the first bonding layer 230 and the second bonding layer 330. The first bonding layer 230 and the second bonding layer 330 can be bonded to each other using a hybrid bonding process, a fusion bonding process, a direct bonding process, a dielectric bonding process, a metal bonding process, a solder joints process, or other suitable processes. Specifically, pressure can be applied to the first wafer 210 and the second wafer 310 to firmly bond to each other, such that the first conductive features 233 of the first bonding layer 230 directly contact the second conductive features 333 of the second bonding layer 330, respectively. For example, after the first dielectric layer 231 and the second dielectric layer 331 of the second bonding layer 330 are bonded via a dielectric-to-dielectric bond process, the first conductive features 233 and the second conductive features 333 of the second wafer 310 are bonded via a metal-to-metal bond process. In some embodiments of the present application, the width of each first conductive feature 233 corresponds to the width of the second conductive feature 333, but the present application is not limited thereto.

[0032] In summary, the etch mask is not only used for partially etching the first bonding layer and the first wafer, but also used for protecting the bonding layer, so that the surface of the bonding layer can be maintained smooth. Therefore, in the wafer bonding process, the first wafer and the bonding layer can provide excellent bonding effect.

[0033] Having described the different embodiments of the present application as above, it should be understood that the different embodiments are presented by way of example only, and are not by way of limitation. Many modifications of the embodiments of the present application, in light of the disclosures herein, can be made by those skilled in the art without departing from the spirit and scope of the present application. Accordingly, the breadth and scope of the present application should not be limited by the examples described above.

[0034]

Symbol Description

[0035] 100: method

[0036] 110, 120, 130, 150, 170: step

[0037] 200: semiconductor device

[0038] 210: first wafer

[0039] 220: integrated circuit structure

[0040] 221: substrate

[0041] 223: via

[0042] 230: first bonding layer

[0043] 231: first dielectric layer

[0044] 233: first conductive feature

[0045] 235: edge portion

[0046] 240: etch mask

[0047] 241: photoresist layer

[0048] 241a: edge portion

[0049] 310: second wafer

[0050] 330: second bonding layer

[0051] 331: second dielectric layer

[0052] 333: second conductive feature

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: forming a first bonding layer on a first wafer, and forming an etch mask on the first bonding layer; etching an edge portion of the first bonding layer using the etch mask, wherein the etching terminates at an upper surface of the first wafer and exposes a portion of the first wafer; removing the etch mask; and securing a second wafer to the first bonding layer. Further comprising:

2. The method of claim 1, wherein, forming an integrated circuit structure on the first wafer, wherein the integrated circuit structure is located between the first wafer and the first bonding layer. The integrated circuit structure includes a substrate and a via through the substrate.

3. The method of claim 2, wherein, The via contacts a first conductive feature of the first bonding layer.

4. The method of claim 3, wherein, A width of the via is less than a width of the first conductive feature.

5. The method of claim 4, wherein, The first bonding layer includes a dielectric layer and a first conductive feature through the dielectric layer.

6. The method of claim 1, wherein, Forming the etch mask includes:

7. The method of claim 1, wherein, forming a photoresist layer on the first bonding layer; and performing an edge trim process to remove an edge portion of the photoresist layer. Securing the second wafer to the first bonding layer includes:

8. The method of claim 1, wherein, contacting a second bonding layer on the second wafer to the first bonding layer; and bonding the first bonding layer and the second bonding layer. A first conductive feature within the first bonding layer contacts a second conductive feature within the second bonding layer.

9. The method of claim 8, wherein, The width of the first conductive feature is equal to a width of the second conductive feature.

10. The method of claim 9, wherein, ​

Images