Transistor and its fabrication method

Abstract

This application provides a transistor and a method for fabricating the same. The method for fabricating the transistor includes: removing a portion of a semiconductor layer to form a fin structure; forming a first gate insulating layer on the surface of the fin structure; processing the first gate insulating layer to transform it into a second gate insulating layer, wherein the dielectric constant of the second gate insulating layer is higher than that of the first gate insulating layer; and forming a third gate insulating layer on the side of the second gate insulating layer near the fin structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a field-effect transistor and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are currently the most commonly used type of field-effect transistor in the semiconductor industry. Since the invention of the first hexagonal topology MOSFET in 1979, MOSFET technology has developed for over 40 years, with researchers focusing on reducing the gate length to improve the storage performance of memory devices. However, when the gate length shrinks to a certain size (e.g., below 20 nanometers), several problems arise. The biggest problem is that as the gate length decreases, the distance between the source and drain becomes closer, and the oxide layer beneath the gate becomes thinner, potentially causing electrons to tunnel through and generate leakage. Another significant issue is that while the flow of electrons through the channel between the source and drain is normally controlled by the gate voltage, as the gate length decreases, the contact area between the gate and the channel also decreases, weakening the gate's control over carrier migration.

[0003] To address these issues, the Fin Field Effect Transistor (FINFET) was developed. FINFET replaces the 2D MOSFET with a 3D FINFET structure; its resemblance to a fish fin gives it the name "fin." In some examples, FINFET pulls the source and drain high into a three-dimensional plate-like structure, making the channel between them plate-like. This increases the contact area between the gate and the channel, allowing for better control of electron migration between the source and drain, thus improving current control and reducing leakage current and dynamic power loss, resulting in greater energy efficiency.

[0004] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0005] This application provides a method for fabricating a transistor. The method includes: forming a fin structure; forming a first gate insulating layer on the surface of the fin structure; processing the first gate insulating layer to transform it into a second gate insulating layer, wherein the dielectric constant of the second gate insulating layer is higher than that of the first gate insulating layer; and forming a third gate insulating layer on the side of the second gate insulating layer near the fin structure.

[0006] In one embodiment, the step of processing the first gate insulation layer includes: processing the first gate insulation layer in an atmospheric environment by a heat treatment process, wherein the atmosphere includes at least one of N2, N2O and NO.

[0007] In one embodiment, after a first gate insulating layer is formed on the surface of the fin structure, the remaining portion of the fin structure forms a first fin structure; the step of forming the third gate insulating layer includes: forming the third gate insulating layer on the surface of the first fin structure, wherein the dielectric constant of the third gate insulating layer is lower than the dielectric constant of the second gate insulating layer.

[0008] In one embodiment, the third gate insulation layer includes a first portion and a second portion, the first portion and the second portion being arranged in a direction from far to near toward the fin structure; the step of forming the third gate insulation layer includes: forming the first portion on the side of the second gate insulation layer near the fin structure at a first temperature; and forming the second portion on the side of the first portion near the fin structure at a second temperature higher than the first temperature.

[0009] In one embodiment, the first temperature is between 500°C and 750°C, and the second temperature is above 900°C.

[0010] In one embodiment, the first temperature is maintained for 5 minutes to 5 hours, and the second temperature is maintained for 5 seconds to 1 hour.

[0011] In one embodiment, the time taken to raise the temperature from the first temperature to the second temperature is 2 to 30 minutes.

[0012] In one embodiment, the thickness of the first gate insulating layer is 2 nm to 4 nm, the thickness of the third gate insulating layer is 1 nm to 2 nm, and the ratio of the thickness of the third gate insulating layer formed at the first temperature to the thickness of the third gate insulating layer formed at the second temperature is 0.5 to 2.

[0013] In one embodiment, the first gate insulation layer and the third gate insulation layer are formed by an in-situ water vapor growth process.

[0014] In one embodiment, the first gate insulating layer is made of an oxide, the second gate insulating layer is made of a nitride, and the third gate insulating layer is made of an oxide.

[0015] In one embodiment, the step of forming the fin structure includes: removing a portion of the semiconductor layer from one side of the semiconductor layer to form a plurality of mutually isolated trenches, and forming the fin structure in the portion located between two adjacent trenches.

[0016] In one embodiment, after forming the fin structure, the method further includes: filling a portion of the trench, wherein the filling portion of the trench forms a shallow trench isolation structure that covers a portion of the fin structure, the covered portion of the fin structure being a first fin and the uncovered portion of the fin structure being a second fin, and a first gate insulating layer being formed on the surface of the second fin.

[0017] In one embodiment, the method further includes: during the processing of the first gate insulation layer, the surface layer of the shallow trench isolation structure is transformed into the second gate insulation layer.

[0018] Another aspect of this application provides a transistor, characterized in that it includes: a fin structure; a third gate insulating layer including a first portion and a second portion, wherein the second portion covers the surface of the fin structure, the first portion is located on the side of the second portion away from the fin structure, and the dielectric constant of the first portion is higher than the dielectric constant of the second portion; and a second gate insulating layer located on the side of the first portion away from the fin structure and covering the surface of the first portion, wherein the dielectric constant of the second gate insulating layer is higher than the dielectric constant of the first portion.

[0019] In one embodiment, the thickness of the third gate insulation layer is 1 nm to 2 nm, and the ratio of the thickness of the first portion to the thickness of the second portion is 0.5 to 2.

[0020] In one embodiment, the thickness of the second gate insulating layer is 2 nm to 4 nm.

[0021] In one embodiment, the material of the second gate insulating layer includes nitride, and the material of the third gate insulating layer includes oxide.

[0022] In one embodiment, the fin structure includes a first fin and a second fin, and the transistor further includes: a first semiconductor layer, the first fin being located on the first semiconductor layer, the second fin being located on the side of the first fin away from the first semiconductor layer; and a shallow trench isolation structure located on the first semiconductor layer and connected to the first fin, wherein the side of the shallow trench isolation structure away from the first semiconductor layer is coplanar with the side of the first fin away from the first semiconductor layer.

[0023] In another aspect, this application provides a three-dimensional memory including any of the transistors described above.

[0024] In one embodiment, the three-dimensional memory includes a 3D NAND memory.

[0025] The solution in this application first forms a second gate insulating layer on the surface of the fin structure, and then forms a third gate insulating layer between the second gate insulating layer and the fin structure. The second gate insulating layer has a high dielectric constant, which ensures the gate's control over electron transport between the source and drain. The third insulating layer is located between the fin structure and the second gate insulating layer, which avoids direct contact between the high dielectric constant layer and the fin structure, thereby reducing the impact of the high dielectric constant layer on carrier migration and improving transistor performance. Attached Figure Description

[0026] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0027] Figure 1a and Figure 1b These are schematic diagrams and three-dimensional views of transistor fabrication methods in some implementations;

[0028] Figure 2 A flowchart illustrating a method for fabricating a transistor according to an exemplary embodiment of this application is shown schematically.

[0029] Figures 3 to 6 This is a process schematic diagram of a transistor fabrication method according to an exemplary embodiment of this application;

[0030] Figure 7 This is a schematic diagram of the fabrication process conditions of the third gate insulating layer according to an exemplary embodiment of this application; and

[0031] Figure 8 This is a partial structural schematic diagram of a transistor according to an exemplary embodiment of this application. Detailed Implementation

[0032] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first gate insulating layer discussed herein may also be referred to as the second gate insulating layer, and the first fin may also be referred to as the second fin, and vice versa.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the first gate insulation layer shown in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar terms used herein are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] The features, principles and other aspects of this application are described in detail below.

[0039] In existing technologies, nitrogen doping in oxide layers is generally performed through decoupled plasma nitridation (DPN). This method can incorporate a high concentration of nitrogen atoms and allows the nitridation depth to remain on the surface of the oxide layer, making it a widely accepted method in the semiconductor industry for improving the dielectric properties of materials. Figure 1a This is a schematic diagram of the transistor fabrication process according to some implementation methods. Figure 1b yes Figure 1a The corresponding 3D structural diagram. Combined with... Figure 1a and Figure 1b As shown, firstly, an oxide layer 110 is grown on the surface of the fin structure 100. Then, the oxide layer 110 is nitrogen-doped using, for example, a decoupled plasma nitriding process, followed by annealing to form a nitride layer 120 on the side of the oxide layer 110 away from the fin structure 100. In some examples, a portion of the oxide layer 110 near the outer surface is also nitrided to form the nitride layer 120.

[0040] The inventors of this application discovered that when the oxide layer 110 is nitrided using a decoupled plasma nitriding process, the distribution of nitrogen exhibits a certain directionality. For example, during the nitriding process, the nitrogen plasma diffuses from top to bottom (along the opposite direction of y) under the influence of voltage, and upon contact with the fin structure 100, it nitrids a portion of the fin structure 100 into a nitrided layer 120. The nitrides first accumulate at the top of the fin structure 100 and then sequentially accumulate downwards. Therefore, after the nitriding process is completed, the portion 101 of the nitrided layer 120 corresponding to the top of the fin structure 100 tends to have a high nitrogen content, while the portion 102 corresponding to the sides of the fin structure 100 tends to have a low nitrogen content. In particular, the nitrogen content in the lower region of the two side portions 102 (along the opposite direction of y) is significantly lower, resulting in differences in nitrogen concentration at different locations in the nitrided layer 120, thereby causing differences in the dielectric constant k value at different locations in the nitrided layer 120. The difference in the value of the dielectric constant k will directly affect the gate 30's ability to control the transfer of electrons between the source 10 and the drain 20 in the fin structure 100, thus reducing the device performance.

[0041] This application proposes a field-effect transistor and its manufacturing method, which can at least partially improve or solve the above-mentioned problems, achieving a small difference in nitrogen concentration at different locations of the nitride layer 120, which is beneficial to improving the control capability of the gate 30. It should be noted that the fin junction trench described in the embodiment of this application includes the semiconductor portion located between the source and drain, corresponding to the gate.

[0042] Figure 2This is a flowchart of a transistor fabrication method 1000 according to an exemplary embodiment of this application. For example... Figure 2 As shown, the transistor fabrication method 1000 provided in this application includes: step S1100, removing a portion of the semiconductor layer to form a fin structure; step S1200, forming a first gate insulating layer on the surface of the fin structure; step S1300, processing the first gate insulating layer to transform it into a second gate insulating layer, wherein the dielectric constant of the second gate insulating layer is higher than that of the first gate insulating layer; and step S1400, forming a third gate insulating layer on the side of the second gate insulating layer near the fin structure.

[0043] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 2 The execution is performed in the order shown.

[0044] Figures 3 to 7 This is a schematic diagram of the fabrication method 1000 of the three-dimensional memory according to an embodiment of this application. The following is in conjunction with... Figures 3 to 7 The above steps S1100 to S1400 are further described.

[0045] Step S1100: Remove a portion of the semiconductor layer to form a fin structure.

[0046] like Figure 3 As shown, in step S1100, a portion of the semiconductor layer 200 may be removed to form a plurality of mutually isolated fin structures 210. Exemplarily, a plurality of trenches 290 can be formed by covering and etching the substrate to be etched using, for example, patterned photoresist. The unetched portion of the semiconductor layer 200 located below the trenches 290 (in the opposite direction of y) forms the substrate 200, and the unetched portion adjacent to the trenches 290 (in the x direction or the opposite direction of x) forms the fin structures 210. Exemplarily, the materials of the substrate 200 and the fin structures 210 may include, for example, silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof.

[0047] In other embodiments, the fin structure 210 may be located on a silicon-on-insulator (SOI) substrate, which may include a silicon substrate and an oxide layer located between the silicon substrate and the fin structure 210.

[0048] In some embodiments, after forming the fin structure 210, a shallow trench isolation structure 220 is further formed within the trench 290. The shallow trench isolation structure 220 covers a portion of the fin structure 210, the covered portion of the fin structure 210 being the first fin portion 211, and the uncovered portion of the fin structure 210 being the second fin portion 212. Figure 3 The dashed line in the middle is the dividing line between the first fin 211 and the second fin 212. The upper surface of the shallow groove isolation structure 220 is coplanar with the upper surface of the first fin 211, and the second fin 212 is located on the upper side of the first fin 211.

[0049] The material of the shallow trench isolation structure 220 may include, for example, oxides. Exemplarily, the front trench isolation structure 220 may be formed by a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0050] In the context of this application, some steps, such as planarization, surface cleaning, and scum removal, are omitted from the description of the manufacturing method of the shallow trench isolation structure 220. These are not the focus of this invention and will not be described further here. Those skilled in the art can add or omit steps in the manufacturing method of the shallow trench isolation structure 220 of this invention as needed.

[0051] It should be understood that the cross-sectional shape of the fin structure 210 in this application is trapezoidal, which is only for illustrative purposes and not a limitation on the cross-sectional shape of the fin structure 210. Those skilled in the art can make different designs according to actual needs. For example, the cross-sectional shape of the fin structure 210 can be designed as a triangle, rectangle or other irregular shape, etc., and this application does not make specific limitations in this regard.

[0052] Step S1200, forming a first gate insulation layer on the surface of the fin structure.

[0053] like Figure 4 As shown, a first gate insulating layer 230 can be formed on the surface of the second fin 212 using, for example, an in-situ vapor growth (ISSG) process. It should be noted that during this process, silicon elements, for example, in the near-surface portion of the second fin 212 participate in the ISSG reaction, transforming a layer near the surface of the second fin 212 into the first gate insulating layer 230. The first gate insulating layer 230 then continues to grow outwards on the surface of the second fin 212. Exemplarily, the thickness of the outwardly growing portion of the first gate insulating layer 230 can be two to three times the thickness of the portion of the first gate insulating layer 230 located within the surface of the second fin 212 (in the opposite x-direction), and the thickness of the first gate insulating layer 230 is, for example, 2 nm to 4 nm.

[0054] In some embodiments, the material forming the first gate insulating layer 230 may include, for example, oxides.

[0055] As another embodiment of this application, the first gate insulation layer 230 can also be formed by a combination of thermal oxidation process and thin film deposition process.

[0056] Step S1300: The first gate insulation layer is processed to transform it into a second gate insulation layer, wherein the second gate insulation layer... The dielectric constant of the insulating layer is higher than that of the first gate insulating layer.

[0057] like Figure 5 As shown, the first gate insulation layer 230 is heat-treated to nitridate it during the heat treatment process, thereby forming the second gate insulation layer 240. In some embodiments, the first gate insulation layer 230 can be heat-treated by introducing an atmosphere such as nitrogen, nitrogen dioxide, nitric oxide, or any combination thereof into a heating device. Since the atmosphere is non-directional, the first gate insulation layer 230 undergoes nitriding under the atmosphere covering conditions, and the nitrogen content in the top portion 241 of the formed second gate insulation layer 240 is relatively similar to the nitrogen content in the sidewall portion 242. The thickness of the second gate insulation layer 240 can remain substantially the same as the thickness of the first gate insulation layer 230.

[0058] In some embodiments, a portion 243 of the shallow trench isolation structure 220 near the upper surface is also transformed into the second gate insulation layer 240 during heat treatment. Exemplarily, the upper surface of the shallow trench isolation structure 220 is covered with an atmosphere such as nitrogen, nitrogen dioxide, nitric oxide, or any combination thereof, and nitrided into the second gate insulation layer 240 during heat treatment.

[0059] In some embodiments, the shallow trench isolation structure 220 and the first gate insulation layer 230 may be made of the same material, for example, both of which are silicon oxide.

[0060] S1400, a third gate insulation layer is formed on the side of the second gate insulation layer near the fin structure.

[0061] The inventors of this application have also discovered that performing a thermal oxidation process after forming the second gate insulating layer 240 can yield transistors with even better performance. For example... Figure 6 As shown, a third gate insulating layer 250 can be formed on the side of the second gate insulating layer 240 near the second fin 212 using, for example, the ISSG process. The dielectric constant of the third gate insulating layer 250 is lower than that of the third gate insulating layer. It should be noted that because the bond energy of the Si-O bond is greater than that of the Si-N bond, and the bond energy of the Si-N bond is greater than that of the Si-Si bond, O atoms, for example, are more likely to bond with Si atoms, for example, on the surface of the second fin 212 during the ISSG process, forming an oxide located on the side of the second gate insulating layer 240 near the second fin 212. The presence of the third gate insulating layer 250 can isolate the second gate insulating layer 240 from the second fin 242, thereby reducing the influence of the higher dielectric constant of the second gate insulating layer 240 on the migration of charge carriers from the source to the drain.

[0062] In some embodiments, silicon, for example, in the portion of the second fin 212 near the second gate insulating layer 240 participates in an ISSG reaction, transforming a layer near the surface of the second fin 212 into a third gate insulating layer 250. The third gate insulating layer 250 then continues to grow outward from the surface of the second fin 212, ultimately forming a layer such as... Figure 6 The third gate insulation layer 250 is shown. The thickness of the third gate insulation layer 250 is, for example, 1 nm to 2 nm.

[0063] In some embodiments, the material of the third gate insulation layer 250 may be the same as or different from that of the first gate insulation layer 230, for example, both may be silicon oxide.

[0064] In some implementations, such as... can be applied during the ISSG process. Figure 7 The stepped temperature shown is used to obtain a third gate insulation layer 250 of better quality. Specifically, the second fin 212 is first oxidized at a first temperature C1 for time t1, and then the temperature is increased to a second temperature C2 and held for time t2.

[0065] In some embodiments, the first temperature C1 may be selected as 500-750°C (inclusive), and the second temperature C2 may be selected as not lower than 900°C. In some embodiments, the time taken to raise the temperature from the first temperature C1 to the second temperature C2 may be 2 minutes to 30 minutes.

[0066] In some embodiments, time t1 can be greater than or less than time t2, and the specific time t1 and time t2 can be adjusted according to the required thickness of the third gate insulating layer 250. The duration t1 of the first temperature C1 is, for example, 5 minutes to 5 hours, and the duration t2 of the second temperature C2 is 5 seconds to 1 hour. The third gate insulating layer 250 may include a first portion and a second portion. The first portion of the third gate insulating layer is formed at the first temperature C1, and the second portion is formed at the second temperature C2. The second portion of the third gate insulating layer is located between the first portion and the second fin 212, and the first portion of the third gate insulating layer is in contact with the second gate insulating layer 240. It has a higher dielectric constant than the first portion of the third gate insulating layer. The ratio of the thickness of the first portion to the second portion of the third gate insulating layer is, for example, 0.5 to 2.

[0067] For example, the material of the third gate insulating layer 250 can be an insulating material, and the second gate insulating layer 240 can be a nitrided layer. During the formation of the first portion of the third gate insulating layer, a small portion of the insulating material near the nitrided layer is nitrided. During the formation of the second portion of the third gate insulating layer, the subsequently formed insulating material is isolated from the nitrided layer and thus avoids nitriding, thereby making the dielectric constant of the second portion of the third gate insulating layer lower than that of the first portion of the third gate insulating layer.

[0068] Another aspect of this application provides a transistor. This transistor can be fabricated using any of the fabrication methods described in the above embodiments.

[0069] refer to Figure 8 As shown, the transistor may include a fin structure 210, a third gate insulating layer 250, and a second gate insulating layer 240. The third gate insulating layer may include a first portion and a second portion, the second portion covering the surface of the fin structure 210, the first portion located on the side of the second portion away from the fin structure 210, and the dielectric constant of the first portion being higher than that of the second portion. The second gate insulating layer 240 is located on the side of the first portion of the third gate insulating layer 250 away from the fin structure 210 and covers the surface of the first portion. The dielectric constant of the second gate insulating layer 240 is higher than that of the first portion of the third gate insulating layer 250.

[0070] In some embodiments, the thickness of the third gate insulating layer 250 may be 1 nm to 2 nm, and the ratio of the thickness of the first portion of the third gate insulating layer 250 to the thickness of the second portion is 0.5 to 2. The thickness of the second gate insulating layer 240 may be 2 nm to 4 nm. The material of the second gate insulating layer 240 includes nitrides, and the material of the third gate insulating layer 250 includes oxides.

[0071] In some embodiments, the fin structure 210 includes a first fin 211 and a second fin 212. The transistor further includes a first semiconductor layer 200' and a shallow trench isolation structure 220. The first fin 211 is located on the first semiconductor layer 200' (along the y-direction), and the second fin 212 is located on the side of the first fin 211 away from the first semiconductor layer 200'. The shallow trench isolation structure 220 is also located on the first semiconductor layer 200' and connected to the first fin 211. The side of the shallow trench isolation structure 220 away from the first semiconductor layer 200' is coplanar with the side of the first fin 211 away from the first semiconductor layer 200'.

[0072] In some embodiments, a third gate insulation layer 250 covers the surface of the second fin 212, and a second gate insulation layer 240 covers the surface of the third gate insulation layer 250.

[0073] Another aspect of this application provides a three-dimensional memory that may include the transistors in any of the above embodiments and may be fabricated by the method for fabricating transistors in any of the above embodiments.

[0074] In one implementation, the three-dimensional memory may include, for example, a 3D NAND memory.

[0075] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated.

[0076] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a transistor, characterized in that, The method includes: Forming fin structures; A first gate insulation layer is formed on the surface of the fin structure; The first gate insulating layer is treated in a nitrogen-containing atmosphere using a heat treatment process to transform it into a second gate insulating layer, wherein the dielectric constant of the second gate insulating layer is higher than that of the first gate insulating layer; and A third gate insulation layer is formed on the side of the second gate insulation layer near the fin structure.

2. The method according to claim 1, wherein, The atmosphere includes at least one of N2, N2O, and NO.

3. The method according to claim 1, wherein, After the first gate insulation layer is formed on the surface of the fin structure, the remaining part of the fin structure forms the first fin structure; The steps for forming the third gate insulation layer include: The third gate insulating layer is formed on the surface of the first fin structure, wherein the dielectric constant of the third gate insulating layer is lower than that of the second gate insulating layer.

4. The method according to claim 3, wherein, The third gate insulation layer includes a first part and a second part, wherein the first part and the second part are arranged in a direction from far to near toward the fin structure; The steps for forming the third gate insulation layer include: At a first temperature, the first portion is formed on the side of the second gate insulating layer near the fin structure; as well as At a second temperature higher than the first temperature, the second part is formed on the side of the first part near the fin structure.

5. The method according to claim 4, wherein, The first temperature is between 500°C and 750°C, and the second temperature is above 900°C.

6. The method according to claim 4, wherein, The duration of the first temperature is 5 minutes to 5 hours, and the duration of the second temperature is 5 seconds to 1 hour.

7. The method according to claim 4, wherein, The time required to raise the temperature from the first temperature to the second temperature is 2 to 30 minutes.

8. The method according to claim 4, wherein, The thickness of the first gate insulation layer is 2 nm to 4 nm, the thickness of the third gate insulation layer is 1 nm to 2 nm, and the ratio of the thickness of the third gate insulation layer formed at the first temperature to the thickness of the third gate insulation layer formed at the second temperature is 0.5 to 2.

9. The method according to claim 1, wherein, The first gate insulation layer and the third gate insulation layer are formed by an in-situ water vapor growth process.

10. The method according to claim 9, wherein, The first gate insulation layer is made of oxide, the second gate insulation layer is made of nitride, and the third gate insulation layer is made of oxide.

11. The method according to claim 1, wherein, The steps for forming the fin structure include: A portion of the semiconductor layer is removed from one side to form multiple isolated trenches, and the portion located between two adjacent trenches forms the fin structure.

12. The method according to claim 11, wherein, After forming the fin structure, the method further includes: A portion of the trench is filled, wherein the filled portion of the trench forms a shallow trench isolation structure that covers a portion of the fin structure, the covered portion of the fin structure being a first fin and the uncovered portion of the fin structure being a second fin, and a first gate insulating layer is formed on the surface of the second fin.

13. The method according to claim 12, wherein, Also includes: During the processing of the first gate insulation layer, the surface layer of the shallow trench isolation structure is transformed into the second gate insulation layer.

14. A transistor, characterized in that, include: Fin structure; A third gate insulating layer includes a first portion and a second portion, wherein the second portion covers the surface of the fin structure, the first portion is located on the side of the second portion away from the fin structure, and the dielectric constant of the first portion is higher than that of the second portion; and A second gate insulating layer is located on the side of the first portion away from the fin structure and covers the surface of the first portion. The material of the second gate insulating layer includes nitrides, wherein the dielectric constant of the second gate insulating layer is higher than that of the first portion.

15. The transistor of claim 14, wherein, The thickness of the third gate insulation layer is 1 nm to 2 nm, and the ratio of the thickness of the first part to the thickness of the second part is 0.5 to 2.

16. The transistor of claim 14, wherein, The thickness of the second gate insulation layer is 2nm to 4nm.

17. The transistor of claim 14, wherein, The material of the third gate insulation layer includes oxides.

18. The transistor of claim 14, wherein, The fin structure includes a first fin and a second fin, and the transistor further includes: A first semiconductor layer, the first fin located on the first semiconductor layer, and the second fin located on the side of the first fin away from the first semiconductor layer; and A shallow trench isolation structure is located on the first semiconductor layer and connected to the first fin. The side of the shallow trench isolation structure away from the first semiconductor layer is coplanar with the side of the first fin away from the first semiconductor layer.

19. A three-dimensional memory, characterized in that, Includes the transistor according to any one of claims 14-18.

20. The three-dimensional memory according to claim 19, wherein, The three-dimensional memory includes 3D NAND memory.

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