A SiP packaging design method of an IPC monitoring chip

Abstract

The application provides a SiP packaging design method of an IPC monitoring chip, which fully utilizes the layout of a die in a package, adjusts the distribution sequence of a main control die DDR PHY interface signal, saves RDL, and can inevitably reduce the production and manufacturing cost of the IPC monitoring chip, so that the IPC monitoring chip has higher cost performance and is more competitive in market promotion. The method comprises the following steps: S1, determining the specification of a chip SiP memory die; S2, collecting signal pad diagram position information of the memory die; S3, adjusting the memory PHY interface pad position of the main control die during the back-end design of the main control die according to the information collected in S2, so that the main control die DDR memory PHY interface pad position and the interface pad sequence of the memory die are consistent; and S4, placing the main control die and the memory die on the same level on a substrate, and realizing one-to-one mapping of the main control die memory PHY to the memory die through a bonding wire.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a SiP packaging design method for an IPC monitoring chip. Background Technology

[0002] Integrated circuits can be divided into application-specific integrated circuits (ASICs) and general-purpose integrated circuits (GPCs), also known as dedicated chips and general-purpose chips. ASICs are characterized by high reliability, good performance, and high functional utilization, while general-purpose chips are characterized by strong versatility, high portability, and good scalability.

[0003] With the development of electronic engineering, the focus has gradually shifted from developing single components to integrating multiple components into a single system. Driven by the demands for high performance and slim, lightweight products, chips with different functions have begun to be integrated. During this period, the continuous development and breakthroughs in packaging technology have become one of the driving forces behind this integration, leading to the emergence of the concept of System-on-Package (SiP). SiP, as a packaging technology, refers to integrating multiple chip dies into a single package, thereby enabling the chip to achieve system functionality.

[0004] Currently, the main electronic components inside IPC monitoring products on the market include a main control chip, a system memory chip, a storage chip for storing the running program, a network transmission chip, and an image sensor chip. Among these, the interconnections between the main control chip and the memory chip on the PCB are complex, and the memory chip occupies a relatively large PCB area. To simplify the PCB hardware design of IPC monitoring products and reduce development costs, IPC monitoring chips commonly use SiP (System-in-Package) technology to encapsulate the main control chip die and the DDR memory chip die into a single chip. A side view of the common SiP stacking method for IPC monitoring chips is shown in the attached image. Figure 1 As shown, the controller die 1 is on top, and the DDR memory die 4 is on the bottom. However, the solder joints of the commonly used DDR memory die 4 are located in the middle of the die, which requires RDL 2 (such as...) Figure 2 (As shown in the example) The solder joints are arranged at the edge of the die to facilitate the interconnection of the DDR PHY interface of the main die and the bonding wire 4 of the memory die.

[0005] The IPC monitoring chip market is currently highly competitive, and how to reduce the cost of IPC monitoring chips while maintaining the basic functions has become an increasingly important demand.

[0006] Commonly used technical terms in the prior art include:

[0007] System-in-a-Package (SIP) is a packaging solution that integrates multiple functional wafers, including processors and memory wafers, into a single package based on factors such as application scenarios and the number of layers on the packaging substrate, thereby achieving a basic and complete functional package.

[0008] A die, or wafer bare, is a very small unit within a silicon wafer, comprising a fully designed single chip and the scribe lines adjacent to the chip in the horizontal and vertical directions. A die is a small, irregularly shaped crystal that makes up a polycrystalline silicon wafer, and each die is sometimes composed of several sub-grains with slightly different orientations. The average diameter of a die is typically in the range of 0.015–0.25 mm, while the average diameter of a sub-grain is typically on the order of 0.001 mm.

[0009] RDL: an abbreviation for Redistribution Layer, refers to the ability to relocate solder pads to any reasonable location on a wafer die. Using RDL technology, traditional center-mounted solder pads can be redistributed to the periphery of the die.

[0010] IPC: an abbreviation for IP Camera. IP stands for Internet Protocol, and Camera is a type of camera or video camera. As the name suggests, IP Camera is a network camera, a new generation of camera that combines traditional camera technology with network technology.

[0011] PCB: An abbreviation for Printed Circuit Board, it is an important electronic component, serving as the support for electronic components and the carrier for their electrical connections. Because it is manufactured using electronic printing techniques, it is called a "printed" circuit board.

[0012] Memory PHY: The physical layer of memory. Common network card chips integrate the MAC and PHY into a single chip. However, many motherboards now include Ethernet MAC control functionality in their southbridge chips, but lack a physical layer interface. Therefore, an external PHY chip is needed to provide an Ethernet access channel. This type of PHY network chip is commonly known as a "software network card chip." Common PHY-enabled chips include the RTL8201BL and VT6103.

[0013] Bonding wire: A core material used in semiconductor packaging, it is a component that connects pins to silicon wafers and transmits electrical signals.

[0014] Wire bonding, also known as pressure bonding, is the process of using metal wires (gold wire, aluminum wire, etc.) and applying heat or ultrasonic energy to connect internal interconnects within solid-state circuits in microelectronic devices. It involves connecting a chip to a circuit or lead frame. It is commonly used in surface-mount packaging processes, such as COB (Chip-on-Board) technology. Summary of the Invention

[0015] To address the aforementioned issues, this method aims to provide a SiP packaging design approach that fully utilizes the die layout within the package and adjusts the signal distribution order of the main control die DDR PHY interface, eliminating the need for RDL. This will inevitably reduce the manufacturing cost of IPC monitoring chips, resulting in higher cost-effectiveness and greater competitiveness in the market.

[0016] Specifically, the present invention provides a SiP packaging design method for an IPC monitoring chip, the method comprising the following steps:

[0017] S1, determine the specifications of the chip SiP memory die;

[0018] S2 collects information on the location of each solder joint on the memory die;

[0019] S3, based on the information collected by S2, adjusts the solder joint position of the main controller die memory PHY interface during the back-end design of the main controller die, so that the solder joint position of the main controller die DDR memory PHY interface is consistent with the solder joint order of the memory die interface;

[0020] S4 places the main controller die and memory die on the same level on the substrate, and uses bonding wires to map the main controller die and memory PHY to the memory die one by one.

[0021] In S2, the positions of the signal solder joints on the memory die are the interface solder joints, including the positions of solder joints A0, A1, A2, A3, A4, A5, and A6.

[0022] In S3, the solder joints of the main controller die memory PHY interface include the positions of solder joints a0, a1, a2, a3, a4, a5, and a6.

[0023] In S3, the main control die and memory die are interconnected by bonding wires, and the solder joints are processed similarly.

[0024] In step S4, the substrate can be replaced by a frame, and the packaging substrate or frame is the carrier of each wafer die in the SiP package.

[0025] In S4, by utilizing the layout of the die in the package and adjusting the signal distribution order of the main controller die and the memory DDR PHY interface, the signal solder joints of the main controller die and the memory die are mapped one by one, so that the two are directly interconnected by bonding wires.

[0026] In the method described, the packaging substrate serves as the carrier for the wafer dies within the package. Other signals related to the main control die and memory die are wired to the packaging substrate via bonding wires and then connected to solder balls to form the chip package as seen. The main control die is the main signal processing unit of the IPC chip. The memory die is the DDR memory unit that runs on the IPC system. The DDR PHY interface solder joints are located at the edge of the main control die and are designed and arranged by the back end of the main control die to interact with the memory die. The bonding wires are the interconnecting wires between the DDR PHY interface solder joints of the main control die and the interface solder joints of the memory die.

[0027] Therefore, the advantage of this application is that: the embodiments of the present invention provide an IPC monitoring SiP chip and its packaging method, which makes full use of the die layout in the package and adjusts the signal distribution order of the main control die memory DDR PHY interface, eliminating the RDL, which will inevitably reduce the production cost of the IPC monitoring chip, making it more cost-effective and competitive in the market. Attached Figure Description

[0028] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.

[0029] Figure 1 This is a side view of the SiP package structure of commonly used IPC monitoring chips in the current market.

[0030] Figure 2 This is a top-view schematic diagram of an IPC monitoring chip DDR die RDL.

[0031] Figure 3 This is a side view schematic diagram of the SiP package structure of the IPC monitoring chip in an embodiment of the present invention.

[0032] Figure 4 This is a top view schematic diagram of the SiP package structure of the IPC monitoring chip in an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of the process of SiP packaging for the IPC monitoring chip in an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram illustrating the specific process of an embodiment of this method. Detailed Implementation

[0035] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.

[0036] This invention provides a SiP (System-in-Package) packaging design scheme for an IPC monitoring chip. The scheme includes: a packaging substrate and a main control die and a memory die 4 located on the packaging substrate, DDR PHY interface solder joints, and bonding wires. The packaging substrate is the carrier of the wafer dies within the package. Other signals related to the main control die and memory die are wired to the packaging substrate via bonding wires and then connected to solder balls to form the chip package. The main control die is the main signal processing unit of the IPC chip; the memory die is the DDR memory unit for the IPC system; the DDR PHY interface solder joints are located at the edge of the main control die, designed and arranged at the rear of the main control die, and interact with the memory die; the bonding wires are the interconnecting wires between the DDR PHY interface solder joints of the main control die and the interface solder joints of the memory die.

[0037] like Figure 6 As shown, the method of this application includes the following steps:

[0038] S1, determine the specifications of the SiP memory die4 chip;

[0039] S2 collects information on the location of each solder joint on memory die4;

[0040] S3, based on the information collected by S2, adjust the position of the main controller die memory PHY interface solder point 8 during the back-end design of the main controller die1, so that the position of the main controller die DDR memory PHY interface solder point 8 and the interface solder point 7 of the memory die are in the same order;

[0041] S4, place the main controller die 1 and memory die 4 on the same level on the substrate, and use bonding wire 3 to realize the one-to-one mapping of the main controller die memory PHY to the memory die.

[0042] In this embodiment of the invention, the specifications of the SiP memory die4 are first determined, and the location information of each solder joint on the memory die4 is studied (e.g., Figure 4 The locations of solder joints A0, A1, A2, A3, A4, A5, and A6 are shown in Figure 7. Other signals on memory die 4 are similar. Based on this, the location of solder joint 8 on the memory PHY interface of the main controller die 1 is adjusted during the back-end design (e.g., ...). Figure 4 The solder joint positions a0, a1, a2, a3, a4, a5, and a6 shown in Figure 8 are treated similarly to the other solder joints connecting the main controller die 1 and the memory die 4 via bonding wires, ensuring that the solder joint positions 8 of the main controller die's DDR memory PHY interface and the interface solder joint positions 7 of the memory die are in the same order. Figure 3 As shown, by placing the main controller die1 and memory die4 on the same level on the substrate, the main controller die and memory PHY can be mapped one-to-one to the memory die through bonding wire 3, thus eliminating the need for RDL 2 and achieving interconnection, thereby reducing the cost of the IPC monitoring chip.

[0043] Furthermore, such as Figure 5 As shown, first, the memory die specifications are determined; second, the positions of the signal solder joints on the memory die are studied; third, the main controller die and the memory die are placed on the same horizontal plane on the substrate; finally, the positions of the corresponding signal solder joints on the main controller die are adjusted so that they can be mapped one-to-one with the signal solder joints on the memory die.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A SiP packaging design method for an IPC monitoring chip, characterized in that, The method includes the following steps: S1, determine the specifications of the chip SiP memory die (4); S2, collect the location information of each solder joint on the memory die (4); the location of each solder joint on the memory die is the location of the interface solder joint (7), including solder joints A0, A1, A2, A3, A4, A5, and A6. S3, based on the information collected in S2, adjust the position of the main control die memory PHY interface solder joint (8) during the back-end design of the main control die (1) so that the order of the main control die memory PHY interface solder joint (8) and the memory die interface solder joint (7) is consistent; the main control die memory PHY interface solder joint (8) includes the positions of solder joints a0, a1, a2, a3, a4, a5, and a6; S4, place the main control die (1) and memory die (4) on the same level on the substrate, and realize the one-to-one mapping of the main control die and memory PHY to the memory die through bonding wire (3). That is, by utilizing the layout of the die in the package and adjusting the signal distribution order of the main control die and memory PHY interface, the signal solder joints of the main control die and memory die are mapped one-to-one, so that the two are directly interconnected by bonding wire, thereby eliminating the need for the RDL layer.

2. The SiP packaging design method for an IPC monitoring chip according to claim 1, characterized in that, In the S3, the main control die (1) and memory die (4) are interconnected by bonding wires, and the solder joints are processed similarly.

3. The SiP packaging design method for an IPC monitoring chip according to claim 1, characterized in that, In step S4, the substrate can be replaced by a frame, and the substrate or frame is the carrier of each wafer die in the SiP package.

4. The SiP packaging design method for an IPC monitoring chip according to claim 1, characterized in that, In the method described, the packaging substrate serves as the carrier for the wafer dies within the package. Other signals related to the main control die and memory die are wired to the packaging substrate via bonding wires and then connected to solder balls to form the chip package as seen. The main control die is the main signal processing unit of the IPC chip. The memory die is the DDR memory unit that runs on the IPC system. The memory PHY interface solder joints are located at the edge of the main control die and are designed and arranged by the back end of the main control die, interacting with the memory die. The bonding wires are the interconnecting wires between the main control die memory PHY interface solder joints and the memory die interface solder joints.

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