A chip packaging process based on a glass substrate and a multi-device integrated glass chip

Abstract

The present invention relates to a chip packaging process based on a glass substrate and a multi-device integrated glass chip, including the following steps: coating an HF-resistant etching resist film on the front surface of the glass; thinning the back surface of the glass substrate by back grinding; performing chemical mechanical polishing; subjecting the back surface of the glass substrate to isotropic etching with a mixed solution of HF acid and ammonia water in a certain proportion to form a bowl-shaped groove; then using ion beam etching to vertically conduct and form a deep groove that penetrates the glass substrate; depositing a TiN / Cu seed layer; forming slender protrusions by electroplating with glue; forming spheres again through a reflow soldering process; cutting through a scribe lane; and thermally welding and bonding the bare die of a single unit to a PCB. The advantages are as follows: a technique for opening holes in the back surface of a glass substrate 3 based on the TSV principle of a silicon substrate, and the 3D / TGV principle is to make copper wire connections on the back surface of the glass chip and weld the chip to the PCB board; thereby realizing device stacking, reducing the size and volume of the integrated chip, shortening the copper wire, reducing power consumption, and improving electrical performance.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging processes, and more specifically, to a chip packaging process based on a glass substrate and a multi-device integrated glass chip. Background Art

[0002] With the rapid development of the integrated circuit chip industry, it is now possible to effectively integrate multiple devices on a single chip, which will also lead to a very complex structure and circuit design on the chip, correspondingly increasing the chip size and power consumption.

[0003] As shown in the attached Figure 1 description, it is a relatively common copper trace structure in the current chip industry. After directly forming copper traces above the chip device, packaging is performed, and the traces are connected to the I / O; its structural size and volume are relatively large.

[0004] As shown in the attached Figure 2 description, it is a TSV (Through Silicon Via) process structure on a silicon substrate of some current multi-integrated chips. First, the back of the silicon wafer is thinned, and then RIE (Reactive Ion Etching) is performed for etching to form holes, copper plating, and welding to complete the chip packaging; it can effectively reduce the size and volume of the chip.

[0005] Currently, single-device chips can no longer meet the current chip market demand, and multi-device integrated chips have gradually emerged in people's vision. Therefore, designing a 3D / TGV (Through Glass Via) structure for glass substrate chips to improve the market competitiveness of multi-device integrated glass chips, enhance product electrical performance, reduce chip volume size, and meet the performance requirements of glass substrate products is the current research and development direction.

[0006] The foregoing description is provided to give general background information and does not necessarily constitute prior art. Summary of the Invention

[0007] The object of the present invention is to provide a chip packaging process based on a glass substrate and a multi-device integrated glass chip. The chip packaging process based on a glass substrate realizes device stacking to reduce the size and volume of the integrated chip, shorten the copper traces, reduce power consumption, and improve electrical performance.

[0008] The present invention provides a chip packaging process based on a glass substrate, including the following steps:

[0009] S1: Coat an HF-resistant corrosion-resistant film on the front of the glass and enter step S2;

[0010] S2: The glass substrate is ground and thinned on the back side and enters step S3;

[0011] S3: Perform chemical mechanical polishing and enter step S4;

[0012] S4: The back side of the glass substrate is isotropically etched with a mixed solution of HF acid and ammonia water in a certain proportion to form a bowl-shaped groove and enter step S5;

[0013] S5: Then use ion beam etching to vertically conduct and form a deep groove, etching through the glass substrate and enter step S6;

[0014] S6: Evaporate a TiN / Cu seed layer and enter step S7;

[0015] S7: Form slender protrusions through electroplating with glue and enter step S8;

[0016] S8: Again, form spheres through a reflow soldering process and enter step S9;

[0017] S9: Cut through the scribe lane and enter step S10;

[0018] S10: High-temperature weld and bond the die of a single unit to the PCB.

[0019] Further, in step S5, the slender protrusions are used for the connection leads between the die and the PCB.

[0020] Further, in step S6, forming spheres through the reflow soldering process is used to enhance lead contact.

[0021] The present invention also provides a multi-device integrated glass chip, which is processed by the above-mentioned chip packaging process based on a glass substrate for the multi-device integrated glass chip.

[0022] Further, the multi-device integrated glass chip includes a passivation layer, a device working area, a glass substrate, a circuit board, and copper wires; one side of the passivation layer is connected to the glass substrate, and the other side of the glass substrate is connected to the circuit board; a plurality of device working areas are provided on the glass substrate, the passivation layer covers the device working areas, two glass vias are provided on the glass substrate, a plurality of devices are connected to the copper wires, and both ends of the copper wires pass through the glass vias and the circuit board respectively for electrical connection.

[0023] Further, the side of the glass substrate connected to the circuit board is a smooth plane.

[0024] Further, the glass vias are cylindrical.

[0025] Further, an elongated protrusion is provided at the end of the copper wire, and the elongated protrusion is used to connect the die of a single unit to the circuit board.

[0026] Further, the elongated protrusion is provided with reflow solder balls, and the reflow solder balls are used to enhance the connection strength between the elongated protrusion and the circuit board.

[0027] The chip packaging process based on a glass substrate provided by the present invention realizes device stacking to reduce the size and volume of integrated chips, shorten copper traces, reduce power consumption, and improve electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of a copper trace structure that is relatively common in the current chip industry.

[0029] Figure 2 It is a schematic diagram of a TSV process structure of a silicon substrate on some current multi-integrated chips.

[0030] Figure 3 It is a flowchart of the chip packaging process based on a glass substrate provided by an embodiment of the present invention.

[0031] Figure 4 It is a schematic diagram of the structure of a multi-device integrated glass chip provided by an embodiment of the present invention.

[0032] Figure 5 For Figure 4 Another schematic diagram of the multi-device integrated glass chip in

[0033] The reference numerals and components involved in the drawings are as follows:

[0034] 1, Passivation layer

[0035] 2, Device working area

[0036] 3, Glass substrate

[0037] 4, Circuit board

[0038] 5, Copper wire

[0039] 6, Glass via hole

[0040] 7, Elongated protrusion

[0041] 8, Reflow solder ball

[0042] 9, Silicon substrate

[0043] 10, Ball planting

[0044] 11, Via hole DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The following will further describe in detail the specific implementation manners of the present invention in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0046] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0047] Embodiment 1

[0048] Figure 3 is a flowchart of the chip packaging process based on a glass substrate provided by an embodiment of the present invention. Please refer to Figure 3 , the chip packaging process based on a glass substrate provided by an embodiment of the present invention includes the following steps:

[0049] S1: Coat an HF-resistant corrosion-resistant film on the front side of the glass to prevent the subsequent HF mixed solution from corroding the chip surface and enter step S2;

[0050] S2: Grind and thin the back side of the glass substrate and enter step S3;

[0051] It should be noted that the TGV process is a process of drilling holes on the back after the wafer front-end process is completed, and it is similar to TSV.

[0052] S3: Perform chemical mechanical polishing and enter step S4;

[0053] S4: Perform isotropic etching on the back side of the glass substrate with a mixed solution of HF acid and ammonia water in a certain proportion to form a bowl-shaped groove and enter step S5;

[0054] S5: Use ion beam etching to vertically conduct and form a deep groove, etching through the glass substrate and enter step S6;

[0055] It should be noted that the actual proportion of the solution concentrations used in steps S4 and S5 is determined by the material of the glass.

[0056] S6: Evaporate and deposit a TiN / Cu seed layer and enter step S7;

[0057] S7: Form slender protrusions through electroplating with glue for connecting leads between the bare chip and the PCB and enter step S8;

[0058] S8: Through the reflow soldering process again, form spheres to enhance lead contact and enter step S9;

[0059] S9: Cut through the scribe lane and enter step S10;

[0060] S10: High-temperature weld and bond the bare chip of a single unit to the PCB.

[0061] It should be noted that the chip packaging process based on a glass substrate provided by the present invention is a technology for opening holes on the back of the glass substrate 3 based on the principle of TSV (Through Silicon Via) on a silicon substrate. The principle of 3D / TGV is to make copper wire connections on the back of the glass chip and weld the chip to the PCB board. Thereby, device stacking is achieved to reduce the size and volume of the integrated chip, shorten the copper wire, reduce power consumption, and improve electrical performance.

[0062] Figure 4 It is a schematic structural diagram of a multi-device integrated glass chip provided by an embodiment of the present invention. Figure 5 is Figure 4 Another schematic structural diagram of the multi-device integrated glass chip in Figure 3 , Figure 4 The present invention also provides a multi-device integrated glass chip, which is processed by the above-mentioned chip packaging process based on a glass substrate for the multi-device integrated glass chip.

[0063] The multi-device integrated glass chip of the present invention includes a passivation layer 1, a device working area 2, a glass substrate 3, a circuit board 4, and a copper wire 5; one side of the passivation layer 1 is connected to the glass substrate 3, and the other side of the glass substrate 3 is connected to the circuit board 4; a plurality of device working areas 2 are provided on the glass substrate 3, the passivation layer 1 covers the device working areas 2, two glass through holes 6 are provided on the glass substrate 3, a plurality of devices are connected to the copper wire 5, and both ends of the copper wire 5 pass through the glass through holes 6 and are electrically connected to the circuit board 4 respectively.

[0064] The side of the glass substrate 3 provided by the present invention that is connected to the circuit board 4 is a smooth plane; the glass through holes 6 are cylindrical, so as to shorten the copper wire, thereby reducing power consumption and improving electrical performance; a slender protrusion 7 is provided at the end of the copper wire 5, and the slender protrusion 7 is used to connect the die of a single unit to the circuit board 4; a reflow solder ball 8 is provided on the slender protrusion 7, and the reflow solder ball 8 is used to enhance the connection strength between the slender protrusion 7 and the circuit board 4.

[0065] Based on the above description, the advantages of the present invention are as follows:

[0066] 1. The chip packaging process based on a glass substrate provided by the present invention is a technology for opening holes on the back of the glass substrate 3 based on the principle of TSV (Through Silicon Via) on a silicon substrate. The principle of 3D / TGV is to make copper wire connections on the back of the glass chip and weld the chip to the PCB board; thereby, device stacking is achieved to reduce the size and volume of the integrated chip, shorten the copper wire, reduce power consumption, and improve electrical performance.

[0067] 2. The multi-device integrated glass chip provided by the present invention has been in the production experiment. Through the comparison between the TGV process and the conventional Via process, the chips manufactured by the TGV process have better electrical performance and higher reliability.

[0068] As mentioned above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip packaging process based on a glass substrate, characterized in that, It includes the following steps: S1: Coat an HF-resistant corrosion-resistant film on the front of the glass, and proceed to step S2; S2: Grind and thin the back of the glass substrate, and proceed to step S3; S3: Perform chemical mechanical polishing, and proceed to step S4; S4: Isotropically etch the back of the glass substrate with a mixed solution of HF acid and ammonia water in a certain proportion to form a bowl-shaped groove, and proceed to step S5; S5: Then use ion beam etching to vertically conduct and form a deep groove that penetrates the glass substrate, and proceed to step S6; S6: Evaporate and deposit a TiN / Cu seed layer, and proceed to step S7; S7: Form slender protrusions through electroplating with glue, and proceed to step S8; S8: Once again, form spheres through a reflow soldering process, and proceed to step S9; S9: Cut through the scribing lane, and proceed to step S10; S10: High-temperature weld and bond the die of a single unit to the PCB.

2. The chip packaging process based on a glass substrate according to claim 1, wherein In step S7, the slender protrusions are used for the connection leads between the die and the PCB.

3. The chip packaging process based on a glass substrate according to claim 1, wherein, In step S8, forming spheres through the reflow soldering process is used to enhance the lead contact.

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