Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, the substrate including a base, a metal gate on the substrate, and a first isolation structure transversely intersecting the metal gate, wherein a gate dielectric layer is formed between the first isolation structure and the metal gate; removing the first isolation structure of a first height to form a first isolation trench transversely intersecting the metal gate, the first isolation trench exposing the gate dielectric layer located on the sidewalls of the first isolation trench; removing the gate dielectric layer on the sidewalls of the first isolation trench to form a second isolation trench; and forming a second isolation structure that fills the second isolation trench. This method not only improves device performance but also simplifies the process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the feature size of integrated circuits continues to shrink. As the feature size decreases, the traditional gate dielectric layer becomes thinner and thinner, which increases the leakage current of transistors and causes excessive power consumption of semiconductor devices.

[0003] To address the aforementioned issues, existing technologies employ a method of replacing the polysilicon gate with a metal gate to form the gate. In this gate replacement process, a polysilicon dummy gate is first formed, followed by the formation of the corresponding device structure. After the device structure is formed, the polysilicon dummy gate is etched away to form a gate trench. A suitable metal material is then used to fill the gate trench to form the metal gate. This allows the metal gate to avoid the high-temperature processing required during device structure formation, preventing threshold voltage drift in the transistor and thus minimizing its performance impact.

[0004] However, devices manufactured using existing semiconductor processes do not perform well. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the electrical performance of the semiconductor structure.

[0006] To address the above problems, embodiments of the present invention provide a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate including a substrate, a metal gate located on the substrate, and a first isolation structure that crosses the metal gate, wherein a gate dielectric layer is formed between the first isolation structure and the metal gate;

[0008] The first isolation structure of the first height is removed to form a first isolation trench that crosses the metal gate, and the first isolation trench exposes the gate dielectric layer located on the sidewall of the first isolation trench;

[0009] Remove the gate dielectric layer from the sidewall of the first isolation trench to form a second isolation trench;

[0010] A second isolation structure is formed, and the second isolation structure fills the second isolation trench.

[0011] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising:

[0012] A substrate, the substrate comprising a substrate and a metal gate disposed on the substrate;

[0013] A first isolation structure is provided, which crosses the metal gate and has a height lower than the metal gate.

[0014] A gate dielectric layer is located between the first isolation structure and the metal gate;

[0015] The second isolation structure is transversely cut across the metal gate and covers a portion of the gate dielectric layer and the first isolation structure, wherein the top surface of the second isolation structure is flush with or higher than the top surface of the metal gate.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0017] The semiconductor structure formation method provided in this embodiment of the invention first forms a first isolation trench by removing a first isolation structure, then removes the gate dielectric layer on the sidewalls of the first isolation trench to form a second isolation trench, and finally fills the second isolation trench to form a second isolation structure that isolates the metal gate. It can be seen that, because the semiconductor structure formation method provided in this embodiment of the invention removes the gate dielectric layer on the sidewalls of the first isolation trench, there is no gate dielectric layer between the formed second isolation structure and the metal gate. This not only reduces the capacitance of the metal gates on both sides of the second isolation structure and improves the performance of the semiconductor device, but also simplifies the processing technology. Attached Figure Description

[0018] Figures 1-4 This is a schematic diagram of a method for forming a semiconductor structure.

[0019] Figures 5 to 19 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0020] As is known from the background technology, devices formed by existing semiconductor processes have poor performance. This paper analyzes the reasons for this poor performance using a semiconductor structure formation method.

[0021] Please refer to Figures 1-4 This is a method for forming semiconductor structures.

[0022] like Figure 1 As shown, a substrate 100 is provided, the substrate including a substrate 101, a dummy gate 107 located on the substrate, and an isolation opening 108 that crosses the dummy gate 107;

[0023] Next, as Figure 2 As shown, the isolation opening is filled to form an isolation structure 104 that isolates the dummy gate;

[0024] Next, refer to Figure 3 and Figure 4 The dummy gate is removed to form a gate dielectric layer 103 and a metal gate 102. The gate dielectric layer 103 conformally covers the sidewalls of the isolation structure 104 and the top and sidewalls of the fin 105. The metal gate 102 covers the gate dielectric layer 103 and exposes the isolation structure 104.

[0025] The gate dielectric layer 103 is used to isolate the substrate and the subsequently formed metal gate 102, reducing the possibility of leakage current from the subsequently formed metal gate 102. Therefore, before replacing the dummy gate with the metal gate 102, a gate dielectric layer 103 needs to be conformally covered on the top and sidewalls of the fin. Since the isolation structure 104 used to isolate the adjacent dummy gate 107 is formed after the dummy gate 107 is formed and before the metal gate 102 is formed, the gate dielectric layer 103 also conformally covers the isolation structure 104.

[0026] As can be seen, in the semiconductor structure formed by the above method, a gate dielectric layer is inevitably formed between the isolation structure 104 and the metal gate 102. The gate dielectric layer is usually a high-k dielectric material, which increases the capacitance of the metal gate on both sides of the isolation structure, resulting in poor performance of the semiconductor device.

[0027] To improve device performance, a common practice is to replace the dummy gate structure (e.g., a polysilicon gate) with a metal gate, followed by a manufacturing process that cuts the metal gate (e.g., through etching) to divide it into two or more portions. Each portion serves as the metal gate for a single transistor. An isolation material is then filled into trenches between adjacent portions of the metal gate to form an isolation structure, thus avoiding a gate dielectric layer between the isolation structure and the metal gate. However, while this method improves device performance, the process steps are cumbersome and complex.

[0028] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure. First, a first isolation trench is formed by removing a first isolation structure. Then, the gate dielectric layer on the sidewalls of the first isolation trench is removed to form a second isolation trench. Finally, the second isolation trench is filled to form a second isolation structure that isolates the metal gate. It can be seen that the semiconductor structure formation method provided by the embodiments of the present invention, on the one hand, reduces the capacitance of the metal gates on both sides of the second isolation structure and improves the performance of the semiconductor device because there is no gate dielectric layer between the second isolation structure and the metal gate. On the other hand, it avoids cutting the metal gate after forming the entire metal gate, simplifying the process.

[0029] To make the above-mentioned objectives, features and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 5 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention. The semiconductor structure provided by the embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] refer to Figures 5 to 12 Provide a base, such as Figure 12 As shown, the substrate includes a substrate 201, a metal gate 202 located on the substrate 201, and a first isolation structure 204 that crosses the metal gate 202. A gate dielectric layer 203 is formed between the first isolation structure 204 and the metal gate 202.

[0032] The substrate provides a process platform for subsequent semiconductor formation. The substrate 201 serves to provide support for other structures. In this embodiment, the substrate 201 may be made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be suitable for process requirements or easily integrated.

[0033] The semiconductor structure formed in this embodiment can be a FinFET, and correspondingly, the substrate includes a substrate 201 and fins 205 located on the substrate 201. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0034] In this embodiment, the fin 205 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0035] An isolation layer 206 is also provided between adjacent fins, which is used to isolate adjacent components. The material of the isolation layer 206 includes silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, etc. In this embodiment, the isolation layer 206 can be a shallow trench isolation (STI) structure. This isolation structure is formed by etching trenches in the substrate 201 and filling them with isolation material. Of course, in other embodiments, the isolation layer can be a film layer grown on the substrate.

[0036] The metal gate 202 spans the fin 205 and covers part of the top wall and part of the side wall of the fin 205.

[0037] The metal gate 202 is used to turn the channel on or off when the semiconductor structure is working.

[0038] In this embodiment, the metal gate 202 includes a work function layer (not shown) and a metal gate layer (not shown) located on the work function layer. When the semiconductor structure is operating, the work function layer is used to adjust the threshold voltage of the transistor.

[0039] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0040] Specifically, refer to Figures 5-12 This is the step of providing the base. Among them, Figure 6 It is a top view. Figure 5 It is along Figure 6 A cross-sectional view along the AA' direction. Figure 7 It is along Figure 6 A cross-sectional view along the BB' direction.

[0041] like Figures 5 to 8 As shown, an initial substrate 200 is provided, such as Figure 8 As shown, the initial substrate 200 includes a substrate 201, a dummy gate 207 located on the substrate 201, and a first isolation structure 204 that crosses the dummy gate 207.

[0042] The first isolation structure 204 is used to cut off the dummy gate 207 in the dummy gate extension direction, so as to isolate a plurality of corresponding device structures in the dummy gate extension direction.

[0043] In this embodiment, the material of the first isolation structure 204 is silicon nitride; in other embodiments, the material of the first isolation structure may also be one or a combination of at least two of silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide.

[0044] Specifically, a first isolation opening that cuts across the dummy gate can be formed through a series of semiconductor processes such as photolithography and etching. Combined with... Figures 5-8 The steps for forming the first isolation structure 204 include:

[0045] A patterned mask layer (not shown in the figure) is formed on the dummy gate. The dummy gate is etched using the mask layer as a mask to form a first isolation opening 208 that cuts across the dummy gate (shown in the figure). Figure 5 (in the middle), fill the first isolation opening 208 to form a first isolation structure 204 that cuts across the pseudo gate.

[0046] It is easy to understand that, in the process of forming device structures, to facilitate the simultaneous formation of multiple device structures, multiple parallel dummy gates are typically formed on the substrate simultaneously. This allows for simultaneous processing during the device formation process, thereby simplifying the process flow. The first isolation structure can transversely cut a dummy gate, or it can transversely cut multiple parallel dummy gates, meaning that the extension direction of the first isolation structure is perpendicular to the extension direction of the multiple parallel dummy gates (e.g., ...). Figure 6(As shown). Correspondingly, after the dummy gate is replaced with a metal gate, the first isolation structure transversely cuts multiple parallel metal gates.

[0047] The dummy gate 207 is a metal gate 202 formed in a subsequent process (shown in...). Figure 12 (The middle) occupies a spatial position. In this embodiment, the material of the dummy gate 207 can be polycrystalline silicon. In other embodiments, the material of the dummy gate can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0048] The dummy gate 207 has side structures formed on both sides. The side structures are used to provide isolation, support, and process space definition for the dummy gate 207 to form the corresponding device structure.

[0049] refer to Figure 6 and Figure 7 In this embodiment of the invention, the side structure may include sidewalls 214 located on both sides of the dummy gate, and the sidewalls 214 may define the formation regions of the source and drain doped layers. Further, in this embodiment of the invention, the side structure may further include an interlayer dielectric layer 213 located between adjacent sidewalls, the interlayer dielectric layer 213 being used to isolate different device structures and further define the process space for the device.

[0050] The sidewall 214 can be made of silicon nitride. In other embodiments of the present invention, the sidewall can also be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0051] The interlayer dielectric layer 213 is made of an insulating material. In this embodiment, the interlayer dielectric layer 213 is made of silicon oxide. In other embodiments, the interlayer dielectric layer 213 may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0052] Combination Figure 8 refer to Figure 9 Remove the dummy gate 207 to form a gate trench (not shown in the figure) that exposes the substrate;

[0053] The gate trench is used to provide space for the subsequent formation of the metal gate.

[0054] It is understandable that, during the removal of the dummy gate, since the material of the dummy gate is different from the material of other parts, the gate trench can be formed by selecting an etching process with a higher etching ratio for the dummy gate material based on the characteristics of the material, thereby reducing damage to other parts of the device structure.

[0055] refer to Figure 10A gate dielectric layer 203 is formed, which conformally covers the sidewall of the first isolation structure 204 and the substrate exposed by the gate trench;

[0056] When the fin 205 is present, the gate dielectric layer 203 conformally covers the sidewall of the first isolation structure 204 and the top and sidewall of the fin 205.

[0057] The gate dielectric layer 203 is used to isolate the substrate and the subsequently formed metal gate (shown in...). Figure 12 (In the middle), reducing the possibility of leakage current generated by the metal gate.

[0058] In this embodiment, the gate dielectric layer 203 can be made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. By selecting a high-k dielectric material for the gate dielectric layer, the possibility of gate leakage current can be reduced. In this embodiment, the gate dielectric layer 203 is made of HfO2. In other embodiments, the gate dielectric layer material can also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0059] like Figure 12 As shown, a metal gate 202 is formed in a gate trench in which a gate dielectric layer 203 is formed, the metal gate 202 covering the gate dielectric layer 203 and exposing the first isolation structure 204.

[0060] After the gate dielectric layer 203 is conformally covered in the gate trench, processes such as deposition and electroplating can be used to form a metal material in the gate trench where the gate dielectric layer 203 is formed, and the metal material outside the gate trench can be removed by a grinding process to form a metal gate 202 in the gate trench.

[0061] Specifically, refer to Figure 11 and Figure 12 The steps for forming the metal gate 202 include:

[0062] A metal gate material layer 202a is formed on the gate dielectric layer 203, and the metal gate material layer 202a covers the gate dielectric layer 203 and the first isolation structure 204.

[0063] Using the first isolation structure 204 as the etch stop layer, the metal gate material layer 202a is etched, and the remaining metal gate material layer is used as the metal gate 202.

[0064] Next, refer to Figures 12-15Remove the first isolation structure 204 of the first height H1 to form a first isolation trench (not shown in the figure) that crosses the metal gate, and expose the gate dielectric layer located on the sidewall of the first isolation trench.

[0065] It should be noted that the purpose of removing the first isolation structure with a first height H1 is to provide process space for removing the gate dielectric layer between the first isolation structure and the metal gate. If the first height H1 is too small, the height of the gate dielectric layer between the first isolation structure and the metal gate that can be removed will also be small, which may not have a significant effect on reducing the gate capacitance. Therefore, theoretically, completely removing the first isolation structure has the most significant effect on reducing the gate capacitance. However, if the first isolation structure is completely removed, it may damage the film layer below the first isolation structure. Therefore, in order to reduce the gate capacitance and avoid damage to the film layer below the first isolation structure, in this embodiment, the range of the first height H1 is 80% to 100% of the total height of the first isolation structure.

[0066] The process for removing the first isolation structure at the first height H1 can be a dry etching process, a wet etching process, or a combination of wet etching and dry etching.

[0067] Specifically, the step of removing the first isolation structure 204 of the first height H1 to form the first isolation trench transversely to the metal gate includes:

[0068] A shielding structure is formed, which covers the metal gate and exposes the first isolation structure;

[0069] The first isolation structure is etched using the shielding structure as a mask to form the first isolation trench.

[0070] It is easy to understand that, in addition to covering the metal gate, the shielding structure can also cover the interlayer dielectric layer between the metal gates.

[0071] like Figure 14 As shown, in this embodiment, to simplify the process, the shielding structure includes a cap layer 209. The cap layer 209 is used to protect the gate during the removal of the first isolation structure and the corresponding gate dielectric layer, as well as during the subsequent processing of the film layer above the gate. In other embodiments, the shielding structure can also be a hard mask layer, which is used to protect the gate during the removal of the first isolation structure and the corresponding gate dielectric layer. After the first isolation structure and the corresponding gate dielectric layer are removed, the hard mask layer is then removed.

[0072] In this embodiment, the capping layer 209 is made of silicon nitride. In other embodiments, the capping layer may also be made of one or a combination of at least two of silicon oxynitride, silicon carbonitride, and silicon boron carbonitride.

[0073] like Figure 13 and Figure 14 As shown, the steps for forming the cap layer 209 include:

[0074] The metal gate 202 at the second height H2 is etched back; a capping layer 209 is formed on the remaining metal gate 202, the capping layer 209 exposing the first isolation structure 204.

[0075] Specifically, a capping material layer (not shown in the figure) is deposited on the remaining metal gate 202, the capping material layer covering the first isolation structure 204, the capping material layer is planarized until the first isolation structure 204 is exposed, and the remaining capping material layer is used as the capping layer 209.

[0076] It should be noted that the size of the second height H2 cannot be too small or too large. If the size of the second height H2 is too small, the thickness of the subsequently formed capping layer will also be small, which may not be able to protect the metal gate during the removal of the first isolation structure and the gate dielectric layer. If the size of the second height H2 is too large, it is equivalent to removing too much of the metal gate film thickness, which will lead to an increase in the resistance of the metal gate. Therefore, in this embodiment, the range of the second height H2 is 5nm-50nm.

[0077] In this embodiment, a dry etching process is used to remove the metal gate 202 of the second height H2. Of course, in other embodiments, a wet etching process or a combination of dry and wet etching processes can also be used to remove part of the metal gate.

[0078] Continue to refer to Figure 16 After forming the first isolation trench, the gate dielectric layer on the sidewall of the first isolation trench is then removed to form the second isolation trench 210.

[0079] Specifically, the step of removing the gate dielectric layer from the sidewall of the first isolation trench to form the second isolation trench 210 includes:

[0080] Using the shielding structure as a mask, the gate dielectric layer on the sidewall of the first isolation trench is etched to form a second isolation trench. When the shielding structure includes a capping layer, the capping layer 209 is used as a mask to etch the gate dielectric layer on the sidewall of the first isolation trench to form a second isolation trench 210.

[0081] It is easy to understand that during the process of removing the gate dielectric layer from the sidewall of the first isolation trench, since the material of the gate dielectric layer is different from the material of other parts, an etching process with a higher etching ratio for the gate dielectric layer material can be selected according to the characteristics of the material, thereby reducing damage to the remaining first isolation structure.

[0082] In this embodiment, the process of removing the gate dielectric layer from the sidewall of the first isolation trench to form the second isolation trench is an isotropic etching process. In this embodiment, the process of removing the gate dielectric layer from the sidewall of the first isolation trench is a dry etching process, wherein the reactant gas is chlorine gas, the flow rate is 10 sccm to 1000 sccm, the reaction pressure is 2 mT to 200 mT, and the source power is 50 W to 1000 W.

[0083] Combination Figure 16 refer to Figure 17 When the shielding structure includes a cap layer 209, after forming the second isolation trench 210, it further includes:

[0084] The capping layer 209 is etched to form a first opening 211, which fully exposes the second isolation trench 210.

[0085] It is easy to understand that the first opening 211 completely exposes the second isolation trench 210, which means that in the direction of metal gate extension, the size of the first opening 211 is greater than or equal to the opening size of the second isolation trench 210.

[0086] The first opening 211 is used for subsequent filling of the second isolation structure 212 (shown in...) Figure 19 (In the middle) provide a process window to ensure that the second isolation structure completely fills the second isolation trench 210.

[0087] Next, a second isolation structure is formed, which fills the second isolation trench.

[0088] refer to Figure 18 and Figure 19 When the capping layer 209 is present, the step of filling the second isolation trench to form the second isolation structure 212 includes:

[0089] Fill the second isolation trench 210 (shown in) Figure 16 (in the middle) and the first opening 211 (shown in) Figure 16 (in the middle), forming a second isolation structure 212.

[0090] Specifically, such as Figure 18 and Figure 19 As shown, the step of filling the second isolation trench to form a second isolation structure, wherein the second isolation structure exposes the metal gate, includes:

[0091] A second insulating material layer 212a is formed, which fills the second insulating trench and covers the top of the cap layer 209;

[0092] Using the capping layer 209 as the etching stop layer, the second isolation material layer 212a is planarized, and the remaining second isolation material layer is used as the second isolation structure 212.

[0093] In this embodiment, the material of the second isolation structure 212 is silicon nitride. In other embodiments, the material of the second isolation structure may also be one or a combination of at least two of silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide.

[0094] After the second isolation structure is formed, the second isolation structure crosses the metal gate, and there is no gate dielectric layer between the second isolation structure and the metal gate.

[0095] The semiconductor structure formation method provided in this embodiment of the invention removes the gate dielectric layer on the sidewall of the first isolation trench, so that there is no gate dielectric layer between the formed second isolation structure and the metal gate. This not only reduces the capacitance of the metal gates on both sides of the second isolation structure and improves the performance of the semiconductor device, but also simplifies the processing technology.

[0096] Accordingly, embodiments of the present invention also provide a semiconductor structure. Please refer to... Figure 19 , Figure 19 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0097] refer to Figure 19 The semiconductor structure in this embodiment includes:

[0098] The substrate includes a substrate 201 and a metal gate 202 located on the substrate 201;

[0099] A first isolation structure 204 is provided, which is transversely cut across the metal gate 202, and the height of the first isolation structure 204 is lower than that of the metal gate 202.

[0100] A gate dielectric layer 203 is located between the first isolation structure 204 and the metal gate 202;

[0101] The second isolation structure 212 is transversely cut across the metal gate 202 and covers part of the gate dielectric layer 203 and the first isolation structure 204. The top surface of the second isolation structure 212 is flush with or higher than the top surface of the metal gate 202.

[0102] The substrate provides a process platform for subsequent semiconductor formation. The substrate 201 serves to provide support for other structures. In this embodiment, the substrate 201 may be made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be suitable for process requirements or easily integrated.

[0103] The semiconductor structure formed in this embodiment can be a FinFET, and correspondingly, the substrate includes a substrate 201 and fins 205 located on the substrate 201. In other embodiments, the semiconductor structure can also be a planar transistor (MOSFET).

[0104] In this embodiment, the fin 205 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0105] An isolation layer 206 is also provided between adjacent fins, which is used to isolate adjacent components. The material of the isolation layer 206 includes silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric materials, etc. In this embodiment, the isolation layer 206 can be a shallow trench isolation (STI) structure. This isolation structure is formed by etching trenches in the substrate 201 and filling them with isolation material. Of course, in other embodiments, the isolation layer can be a film layer grown on the substrate.

[0106] The metal gate 202 spans the fin 204 and covers part of the top wall and part of the side wall of the fin 204.

[0107] The metal gate 202 is used to turn the channel on or off when the semiconductor structure is working.

[0108] In this embodiment, the metal gate 202 includes a work function layer (not shown) and a metal gate layer (not shown) located on the work function layer. When the semiconductor structure is operating, the work function layer is used to adjust the threshold voltage of the transistor.

[0109] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of Co, Ru, and W.

[0110] When the fin 205 is present, the gate dielectric layer 203 conformally covers the sidewall of the first isolation structure 204 and the top and sidewall of the fin 205.

[0111] The gate dielectric layer 203 is used to isolate the substrate and the metal gate 202 to prevent leakage current from the metal gate.

[0112] In this embodiment, the gate dielectric layer 203 can be a high-k dielectric layer, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer 203 is made of HfO2. In other embodiments, the gate dielectric layer material can also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0113] It is easy to understand that both the first isolation structure 201 and the second isolation structure 212 are used to isolate the metal gate. Since there is no gate dielectric layer between the second isolation structure and the metal gate, the higher the second isolation structure is, the smaller the metal gate capacitance on both sides of the isolation structure is, given the limited film height. In this embodiment, in order to reduce the gate capacitance as much as possible, the ratio of the height of the first isolation structure 204 to the height of the second isolation structure 212 is less than or equal to 1:4.

[0114] In this embodiment, the material of the first isolation structure 204 can be one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide. The material of the second isolation structure 212 can be one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide. The materials of the first isolation structure 204 and the second isolation structure 212 can be the same or different.

[0115] The semiconductor structure provided in this embodiment of the invention further includes a capping layer 209, which covers the metal gate 202. The capping layer 209 has a second opening (not shown in the figure), and the second isolation structure fills the second opening. The top of the capping layer 209 is flush with the top of the second isolation structure.

[0116] In this embodiment of the invention, because the capping layer covers the metal gate and the top of the capping layer is flush with the top of the second isolation structure, the top surface of the second isolation structure 212 is higher than the top surface of the metal gate 202. In other embodiments, the top surface of the second isolation structure 212 may also be flush with the top surface of the metal gate 202.

[0117] In this embodiment of the invention, the capping layer 209 is made of silicon nitride. In other embodiments, the capping layer may also be made of one or a combination of at least two of silicon oxynitride, silicon carbonitride, and silicon boron carbonitride.

[0118] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising a substrate, a metal gate on the substrate, and a first isolation structure crossing the metal gate, a gate dielectric layer being formed between the first isolation structure and the metal gate; removing the first isolation structure by a first height to form a first isolation trench crossing the metal gate, the first isolation trench exposing the gate dielectric layer on the sidewall of the first isolation trench; removing the gate dielectric layer on the sidewall of the first isolation trench by an isotropic etching process to form a second isolation trench; forming a second isolation structure to fill the second isolation trench.

2. The method of forming a semiconductor structure of claim 1, wherein, The step of removing the first isolation structure by a first height to form a first isolation trench crossing the metal gate comprises: forming a shielding structure to cover the metal gate and expose the first isolation structure; etching the first isolation structure to form a first isolation trench by taking the shielding structure as a mask.

3. The method of forming a semiconductor structure of claim 2, wherein, The step of removing the gate dielectric layer on the sidewall of the first isolation trench to form a second isolation trench comprises: etching the gate dielectric layer on the sidewall of the first isolation trench to form a second isolation trench by taking the shielding structure as a mask.

4. The method of forming a semiconductor structure of claim 3, wherein, The shielding structure comprises a cap layer, and the step of forming the cap layer comprises: etching back the metal gate by a second height; forming a cap layer on the remaining metal gate, the cap layer exposing the first isolation structure.

5. The method of forming a semiconductor structure of claim 4, wherein, The second height ranges from 5 nm to 50 nm.

6. The method of forming a semiconductor structure of claim 4, wherein, After the step of forming a second isolation trench, the method further comprises: etching the cap layer to form a first opening, the first opening completely exposing the second isolation trench.

7. The method of forming a semiconductor structure of claim 6, wherein, The step of forming a second isolation structure comprises: filling the second isolation trench and the first opening to form a second isolation structure.

8. The method of forming a semiconductor structure of claim 6, wherein, The step of filling the second isolation trench and the first opening to form a second isolation structure comprises: forming a second isolation material layer to fill the second isolation trench and the first opening and cover the top of the cap layer; planarizing the second isolation material layer by taking the cap layer as an etching stop layer, and taking the remaining second isolation material layer as a second isolation structure.

9. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The step of providing a substrate comprises: providing an initial substrate, the initial substrate comprising a substrate, a dummy gate on the substrate, and a first isolation structure crossing the dummy gate; removing the dummy gate to form a gate trench exposing the substrate; forming a gate dielectric layer to cover the sidewall of the first isolation structure and the substrate exposed by the gate trench; forming a metal gate to cover the gate dielectric layer and expose the first isolation structure.

10. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The material of the first isolation structure is one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbinitride, silicon oxynitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide, and the material of the second isolation structure is one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbinitride, silicon oxynitride, silicon carbonitride, boron nitride, and boron nitride silicon carbide.

11. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The process for removing the gate dielectric layer of the first isolation trench sidewall is a dry etching process, wherein the reaction gas is chlorine, the flow rate is 10-1000sccm, the reaction pressure is 2-200mT, and the source power is 50-1000W.

12. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The first height ranges from 80% to 100% of the total height of the first isolation structure.

13. The method of forming a semiconductor structure according to any one of claims 4-8, wherein The material of the cap layer is one or a combination of at least two of silicon nitride, silicon oxynitride, silicon carbon nitride, and boron carbon silicon nitride.

14. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The process for removing the first isolation structure of the first height is a dry etching process, a wet etching process, or a combination of a wet etching process and a dry etching process.

15. The method of forming a semiconductor structure according to any one of claims 3-8, wherein The process for etching the gate dielectric layer of the first isolation trench sidewall to form the second isolation trench is an isotropic process.

16. The method of forming a semiconductor structure according to any one of claims 1 to 8, wherein The material of the gate dielectric layer is a high-k dielectric material.

17. A semiconductor structure, characterized in that, The method comprises: a substrate comprising a substrate and a metal gate on the substrate; a first isolation structure intersecting the metal gate and having a height lower than the metal gate; a gate dielectric layer between the first isolation structure and the metal gate; a second isolation structure intersecting the metal gate and covering part of the gate dielectric layer and the first isolation structure, the top surface of the second isolation structure being flush with or higher than the top surface of the metal gate.

18. The semiconductor structure of claim 17, wherein, The ratio of the height of the first isolation structure to the height of the second isolation structure is less than or equal to 1:

4.

19. The semiconductor structure of claim 17, wherein, The method further comprises: a cap layer covering the metal gate, the cap layer being provided with a second opening, and the second isolation structure further filling the second opening, the top of the cap layer being flush with the top of the second isolation structure.

20. The semiconductor structure of claim 17, wherein, The material of the first isolation structure is one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon carbon oxynitride, silicon oxynitride, silicon carbon nitride, boron nitride, and boron carbon silicon nitride, and the material of the second isolation structure is one or a combination of at least two of silicon nitride, silicon carbide, silicon oxynitride, silicon carbon oxynitride, silicon oxynitride, silicon carbon nitride, boron nitride, and boron carbon silicon nitride.

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