Packaging structure and packaging method

Abstract

The application discloses a packaging structure and a packaging method. The packaging method of the application firstly thins a chip, reduces the thickness of the chip, controls the thickness of the chip unit to be less than 60 microns, and then etches to form a via. The via obtained in this way is good in uniformity, and the coverage of an insulating layer on the inner wall of the via is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular, to a packaging structure and a packaging method. BACKGROUND

[0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology of packaging and testing an entire wafer and then cutting the wafer to obtain single finished chips. The chips packaged by the wafer level chip size packaging technology are highly miniaturized, and the chip cost is significantly reduced with the decrease of the chip size and the increase of the wafer size. The technology meets the market requirements for miniaturization, lightness, shortness, thinness and low price of microelectronic products, and thus becomes a hotspot and development trend in the current packaging field.

[0003] TSV (Through Silicon Via) is a latest technology of realizing interconnection between chips by making vertical vias between chips and between wafers. Unlike the previous IC packaging bonding and the stacking technology using bumps, TSV can maximize the density of chips stacked in three dimensions and minimize the size of the chips, greatly improving the performance of chip speed and low power consumption.

[0004] In the existing wafer level packaging method, when a chip is packaged, the thickness of the chip is 150 μm to 180 μm. A via exposing a solder pad is formed by etching the chip, and then an insulating layer is deposited in the via. However, due to the large thickness of the chip, the aspect ratio of the via formed by TSV exceeds 3:1. After etching, the uniformity of the via formed on the wafer is poor, the entire wafer is severely warped, the final packaging yield is very low, and the coverage of the insulating layer on the surface and the bottom of the via is low.

[0005] The information disclosed in this Background section is only for the purpose of increasing the understanding of the background of the application and should not be taken as an acknowledgement or any form of suggestion that this information forms prior art that is already known in this field. SUMMARY

[0006] The present application aims to provide a packaging structure and a packaging method, which can solve the problems of poor etching uniformity and low coverage of the insulating layer formed in the via in the prior art.

[0007] To achieve the above-mentioned purpose, an embodiment of the present application provides a packaging structure, comprising:

[0008] a chip unit comprising opposite first and second surfaces, the first surface having a sensing region and a solder pad, the solder pad being electrically coupled to the sensing region, the second surface of the chip unit being provided with a via penetrating through the chip unit, the via being used to expose the solder pad, the thickness of the chip unit being less than 60 μm;

[0009] a protective cover plate opposite to the first surface of the chip unit;

[0010] a substrate opposite to the second surface of the chip unit, the substrate having a through hole communicating with the via hole;

[0011] an insulating layer covering at least the inner wall of the via hole;

[0012] a solder bump disposed on the surface of the substrate away from the chip unit, the solder bump being electrically connected to the solder pad through a re-distribution layer disposed in the via hole and the through hole.

[0013] In one or more embodiments of the present application, the via hole is a through hole, and / or the through hole is a through hole.

[0014] In one or more embodiments of the present application, the depth of the via hole is less than the width of the via hole. In one or more embodiments of the present application, the width of the via hole is 40 μm to 60 μm.

[0015] In one or more embodiments of the present application, the substrate is bonded to the second surface of the chip unit.

[0016] In one or more embodiments of the present application, the insulating layer extends between the chip unit and the substrate.

[0017] In one or more embodiments of the present application, the substrate is bonded to the second surface of the chip unit.

[0018] In one or more embodiments of the present application, the substrate is made of glass.

[0019] In one or more embodiments of the present application, the thickness of the substrate is 100 μm to 120 μm.

[0020] In one or more embodiments of the present application, a support structure is further provided between the first surface of the chip unit and the protective cover plate, and the sensing area is located in a recess formed by the support structure and the protective cover plate.

[0021] To achieve the above object, an embodiment of the present application further provides a packaging method, comprising:

[0022] providing a chip unit, the chip unit comprising opposite first and second surfaces, the first surface having a sensing area and a solder pad, the solder pad being electrically coupled to the sensing area;

[0023] providing a protective cover plate, and combining the protective cover plate to the first surface of the chip unit;

[0024] thinning the second surface of the chip unit to control a thickness of the chip unit to be less than 60 μm;

[0025] forming a via through the chip unit on the second surface of the chip unit, the via exposing the solder pad;

[0026] forming an insulating layer covering sidewalls of the via;

[0027] providing a substrate, and bonding the substrate to the second surface of the chip unit;

[0028] forming a via hole on the substrate in communication with the via;

[0029] forming a solder bump on a surface of the substrate facing away from the chip unit, the solder bump being electrically connected to the solder pad through a redistribution layer disposed in the via and the via hole.

[0030] To achieve the above object, an embodiment of the present application further provides a packaging method, comprising:

[0031] providing a wafer, the wafer comprising a plurality of chip units arranged in an array, each of the chip units comprising opposite first and second surfaces, the first surface having a sensing region and a solder pad, the solder pad being electrically coupled to the sensing region;

[0032] providing a protective cover plate, and bonding the protective cover plate to the first surface of the chip unit;

[0033] thinning the second surface of the chip unit to control a thickness of the chip unit to be less than 60 μm;

[0034] forming a via through the chip unit on the second surface of the chip unit, the via exposing the solder pad;

[0035] forming an insulating layer covering sidewalls of the via;

[0036] providing a substrate, and bonding the substrate to the second surface of the chip unit;

[0037] forming a via hole on the substrate in communication with the via;

[0038] forming a solder bump on a surface of the substrate facing away from the chip unit, the solder bump being electrically connected to the solder pad through a redistribution layer disposed in the via and the via hole.

[0039] dividing the wafer through a cutting process to form a plurality of packaging structures of the chip units.

[0040] Compared with the prior art, the packaging method of the present invention first thins the chip to reduce the thickness of the chip and then etches to form vias. The vias thus obtained have good uniformity and the insulation layer has a high coverage rate on the inner wall of the via. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic diagram of a packaging structure according to embodiment 1 of the present invention;

[0042] Figures 2a to 2h is a schematic diagram of an intermediate structure of a packaging structure manufacturing process according to embodiment 2 of the present invention;

[0043] Figure 3 FIG. 1 is a top view of the structure of a wafer according to Example 3 of the present invention. DETAILED DESCRIPTION

[0044] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

[0045] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0046] Example 1

[0047] like Figure 1 As shown, a packaging structure 100 according to a preferred embodiment of the present invention includes a chip unit 10 , a protective cover 20 , a substrate 30 , an insulating layer 40 and solder bumps 50 . The chip unit 10 includes a first surface 11 and a second surface 12 relative to each other, the first surface having a sensing area 111 and a solder pad 112, the solder pad 112 being electrically coupled to the sensing area 111, and the second surface 12 of the chip unit 10 being provided with a via 13 passing through the chip unit 10, the via 13 being used to expose the solder pad 112; the protective cover 20 is opposite to the first surface 11 of the chip unit 10; the substrate 30 is opposite to the second surface 12 of the chip unit 10, and a through hole 31 connected to the via 13 is opened on the substrate 30; the insulating layer 40 covers at least the inner wall of the via 13; the soldering protrusion 50 is provided on the surface of the substrate 30 facing away from the chip unit 10, and the soldering protrusion 50 is electrically connected to the solder pad 112 through a redistribution layer 60 provided in the via 13 and the through hole 31.

[0048] In one embodiment, the sensing area 111 of the chip unit 10 is provided with a plurality of pixels arranged in an array. The chip unit 10 may be a capacitive sensing chip, such as a fingerprint recognition chip.

[0049] In another embodiment, the chip unit 10 can also be a photosensitive chip, at this time, in order to facilitate the photosensitive information of the sensing area 111, the protective cover plate 20 is made of transparent material, such as glass, which can be organic glass or inorganic glass. At this time, the chip unit 10 can be an image sensing chip.

[0050] If the chip unit 10 is too thick, such as greater than 60 μm, the via uniformity etched by TSV is poor, which causes the whole chip unit to be severely warped, and the final packaging yield is very low. In order to solve this problem, the thickness of the chip unit 10 in the embodiment can be controlled to be less than 60 μm by thinning, such as 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm. In theory, the smaller the thickness of the chip unit 10 is, the better, and the solder pad 112 is directly exposed. In the case that the thickness of the chip unit 10 is relatively small, the via uniformity formed by TSV etching is good.

[0051] In order to further improve the coverage of the insulating layer 40 in the via 13, the aspect ratio b / a of the via 13 is less than 1 in the embodiment, and in a preferred embodiment, the width (inner diameter) of the via 13 is 40 μm-60 μm, more preferably 40 μm-55 μm, such as 45 μm, 47 μm, 50 μm.

[0052] The via 13 is used to expose the solder pad 112, so as to facilitate the electrical connection between the solder bump 50 and the solder pad 112. In an embodiment, the via 13 is a straight-through hole, on the one hand, the axis of the straight-through hole is perpendicular to the surface where the chip unit is located, on the other hand, the via 13 has the same hole diameter along its axial direction. In other embodiments, the via 13 can also be a slanting-through hole, and the axial direction thereof forms a certain inclined angle with the plane where the chip unit is located. The shape of the via 13 can also be a horn shape with the upper width and the lower narrowness, and the inner diameter thereof gradually decreases from top to bottom. The shape of the via 13 can also be a triangular hole, a square hole, etc., which are only exemplary described in the embodiment.

[0053] After the thinning treatment, the mechanical strength of the chip unit 10 is weak, in order to further enhance the mechanical strength of the packaging structure, a substrate 30 with a certain hardness and thickness is arranged on the second surface 12 of the chip unit 10 in the embodiment, in an embodiment, the substrate 30 can be made of insulating material, preferably glass, which can be organic glass or inorganic glass. The arrangement of the substrate 30, on the one hand, guarantees the strength of the packaging, on the other hand, controls the thickness of the packaging, therefore, the thickness of the substrate 30 is 100 μm-120 μm, preferably 100 μm-110 μm, such as 103 μm, 105 μm, 108 μm.

[0054] The substrate 30 and the chip unit 10 are combined by bonding. In one embodiment, silicon-silicon bonding may be used.

[0055] The through hole 31 on the substrate 30 is connected to the via 13 for the rewiring layer 60 to pass through. The through hole 31 is preferably a straight through hole, and the axial direction of the through hole is perpendicular to the plane where the substrate 30 is located. In other embodiments, the through hole 31 can also be an oblique through hole. In one embodiment, the inner diameter of the through hole 31 is the same as the inner diameter of the via 13. In this embodiment, a step structure is formed between the through hole 31 and the top of the insulating layer 40; in one embodiment, the inner diameter of the through hole 31 is the same as the inner diameter of the insulating layer 40. In this way, the rewiring layer 60 can extend on the flat inner wall surface, and the bonding degree between the rewiring layer 60 and the inner wall surface of the through hole 31 and the via 13 is more firm; in another embodiment, the through hole 31 and the via 13 can form a double-layer step structure, and the average inner diameter of the through hole 31 is larger than the inner diameter of the via 13.

[0056] The insulating layer 40 also extends between the chip unit 10 and the substrate 30. The insulating layer 40 covers the inner wall surface of the via 13 and the exposed second surface of the chip unit. When the substrate 30 and the chip unit 10 are bonded, the insulating layer 40 can be clamped between the substrate 30 and the chip unit 10, thereby preventing the edges of the insulating layer 40 from warping. In one embodiment, the insulating layer is made of silicon dioxide.

[0057] The packaging structure 100 further includes a support structure 70 , which is located between the first surface 11 of the chip unit 10 and the protective cover 20 . The sensing area 111 is located in a groove formed by the support structure 70 and the protective cover 20 .

[0058] The package structure 100 further includes a solder mask layer 80 , which covers the redistribution layer 60 and the through hole 31 .

[0059] Example 2

[0060] Ginseng Figures 2a to 2h , a packaging method according to an embodiment of the present invention includes the following steps.

[0061] Step s101, reference Figure 2a A chip unit 10 is provided. The chip unit 10 includes a first surface 11 and a second surface 12 opposite to each other. The first surface has a sensing area 111 and a bonding pad 112 . The bonding pad 112 is electrically coupled to the sensing area 111 .

[0062] In one embodiment, the sensing area 111 of the chip unit 10 is provided with a plurality of pixels arranged in an array. The chip unit 10 may be a capacitive sensing chip, such as a fingerprint recognition chip. In another embodiment, the chip unit 10 may also be a photosensitive chip, such as an image sensor chip.

[0063] Step s102, referring to FIG. 1, a protective cover plate 20 is provided. Figure 2b

[0064] When the chip unit 10 is a photosensitive chip, in order to facilitate the photosensitive information of the sensing area 111, the protective cover plate 20 is made of transparent material, such as glass, which can be organic glass or inorganic glass.

[0065] Step s103, referring to FIG. 2, a support structure 70 is formed on the surface of the protective cover plate 20. Figure 2c

[0066] Step s104, referring to FIG. 3, the protective cover plate 20 is combined with the first surface 11 of the chip unit 10. The support structure 70 is located between the first surface 11 of the chip unit 10 and the protective cover plate 20, and the sensing area 111 is located in the groove 13 surrounded by the support structure 70 and the protective cover plate 20. Figure 2d

[0067] Step s105, referring to FIG. 4, the second surface 12 of the chip unit 10 is thinned to control the thickness of the chip unit 10 to be less than 60 μm. The thinning can be achieved by mechanical grinding or chemical etching. Figure 2e

[0068] Step s106, referring to FIG. 5, a via hole 13 is formed on the second surface 12 of the chip unit 10, which exposes the solder pad 112. Figure 2f

[0069] The aspect ratio b / a of the via hole 13 is less than 1. In a preferred embodiment, the width (inner diameter) of the via hole 13 is 40 μm to 60 μm, more preferably 40 μm to 55 μm, such as 45 μm, 47 μm, 50 μm. The via hole 13 is used to expose the solder pad 112 to facilitate the electrical connection between the solder bump 50 and the solder pad 112. In an embodiment, the via hole 13 is a straight hole, on the one hand, the axis of the straight hole is perpendicular to the surface of the chip unit, on the other hand, the via hole 13 has the same hole diameter along its axial direction.

[0070] Step s107, referring to FIG. 6, an insulating layer 40 is formed on the second surface 12 of the chip unit 10 and the sidewall of the via hole 13. Figure 2g

[0071] Step s108, referring to FIG. 7, a substrate 30 is provided, and a through hole 31 is formed on the substrate 30 to communicate with the via hole 13. Figure 2h The substrate 30 is combined with the second surface 12 of the chip unit 10 by bonding.

[0072] The substrate 30 is combined with the second surface 12 of the chip unit 10 by bonding.​​​​​​

[0073] The substrate 30 can be made of glass, which can be organic glass or inorganic glass. The substrate 30 is arranged to ensure the strength of the package and control the thickness of the package. Therefore, the thickness of the substrate 30 is 100 μm to 120 μm, preferably 100 μm to 110 μm, for example, 103 μm, 105 μm or 108 μm.

[0074] In step s109, the solder bump 50 is formed on the surface of the substrate 30 away from the chip unit 10, and the solder bump 50 is electrically connected to the solder pad 112 through the redistribution layer 60 arranged in the via hole 13 and the through hole. Finally, the anti-solder layer 80 is formed on the redistribution layer 60 and in the through hole 31. Figure 1 In step s103, the support structure 70 can be formed on the first surface 11 of the chip unit 10 first, and then the protective cover plate 20 is combined with the chip unit 10.

[0075] In step s103, the support structure 70 can be formed on the first surface 11 of the chip unit 10 first, and then the protective cover plate 20 is combined with the chip unit 10.

[0076] In step s108, the substrate 30 can be bonded with the chip unit 10 first, and then the through hole 31 is formed on the substrate 30.

[0077] Embodiment 3

[0078] In step s109, the solder bump 50 is formed on the surface of the substrate 30 away from the chip unit 10, and the solder bump 50 is electrically connected to the solder pad 112 through the redistribution layer 60 arranged in the via hole 13 and the through hole. Finally, the anti-solder layer 80 is formed on the redistribution layer 60 and in the through hole 31. Figure 3 And Figures 2a to 2h According to the packaging method of the embodiment of the present application, the method comprises the following steps.

[0079] In step s201, a wafer 200 is provided, and the wafer comprises a plurality of chip units 100 arranged in an array.

[0080] In step s202, the wafer 200 is divided into a plurality of chip units 10. Figure 2a In step s202, the wafer 200 is divided into a plurality of chip units 10. Figure 3 In step s202, the wafer 200 is divided into a plurality of chip units 10.

[0081] In an embodiment, the sensing area 111 of the chip unit 10 is provided with a plurality of pixels arranged in an array, and the chip unit 10 can be a capacitive sensing chip, for example, a fingerprint recognition chip. In another embodiment, the chip unit 10 can also be a photosensitive chip, for example, an image sensor chip.

[0082] In step s202, the wafer 200 is divided into a plurality of chip units 10. Figure 2b In step s202, the wafer 200 is divided into a plurality of chip units 10.

[0083] When the chip unit 10 is a light-sensing type chip, in order to facilitate the light-sensing information of the sensing area 111, the protective cover plate 20 is made of transparent material, such as glass, which can be organic glass or inorganic glass.

[0084] In step s203, referring to Figure 2c A support structure 70 is formed on the surface of the protective cover plate 20.

[0085] In step s204, referring to Figure 2d The protective cover plate 20 is combined with the first surface 11 of the chip unit 10. The support structure 70 is located between the first surface 11 of the chip unit 10 and the protective cover plate 20, and the sensing area 111 is located in the groove 13 surrounded by the support structure 70 and the protective cover plate 20.

[0086] In step s205, referring to Figure 2e The second surface 12 of the chip unit 10 is thinned to control the thickness of the chip unit 10 to be less than 60 μm. The thinning can be achieved by mechanical grinding or chemical etching.

[0087] In step s206, referring to Figure 2f A through hole 13 is formed on the second surface 12 of the chip unit 10, which exposes the solder pad 112.

[0088] The aspect ratio b / a of the through hole 13 is less than 1. In a preferred embodiment, the width (inner diameter) of the through hole 13 is 40 μm to 60 μm, more preferably 40 μm to 55 μm, such as 45 μm, 47 μm, 50 μm. The through hole 13 is used to expose the solder pad 112 to facilitate the electrical connection between the solder bump 50 and the solder pad 112. In an embodiment, the through hole 13 is a straight hole, on the one hand, the axis of the straight hole is perpendicular to the surface of the chip unit, on the other hand, the through hole 13 has the same hole diameter along its axial direction.

[0089] In step s207, referring to Figure 2g An insulating layer 40 is formed on the second surface 12 of the chip unit 10 and the sidewall of the through hole 13.

[0090] In step s208, referring to Figure 2h A substrate 30 is provided, and a through hole 31 is formed on the substrate 30 to communicate with the through hole 13.

[0091] The substrate 30 is combined with the second surface 12 of the chip unit 10 by bonding.

[0092] The substrate 30 can be made of glass, which can be organic glass or inorganic glass. The substrate 30 is designed to ensure the strength of the package and to control the thickness of the package. Therefore, the thickness of the substrate 30 is 100 μm to 120 μm, preferably 100 μm to 110 μm, for example, 103 μm, 105 μm, or 108 μm.

[0093] Step s209, reference Figure 1 A solder bump 50 is formed on the surface of the substrate 30 facing away from the chip unit 10. The solder bump 50 is electrically connected to the solder pad 112 through a redistribution layer 60 disposed within the via 13 and the through hole. Finally, a solder mask 80 is formed covering the redistribution layer 60 and the through hole 31.

[0094] Step s210, reference Figure 3 The wafer 200 is divided along the cutting channels 201 by a cutting process to form a packaging structure 100 of multiple chip units.

[0095] In step s203 , the support structure 70 may be manufactured on the first surface 11 of the chip unit 10 first, and then the protective cover 20 and the chip unit 10 may be combined.

[0096] In step s208 , the substrate 30 and the chip unit 10 may be bonded first, and then the through hole 31 may be formed on the substrate 30 .

[0097] The foregoing descriptions of specific exemplary embodiments of the present invention are for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise forms disclosed, and it is apparent that many variations and modifications are possible in light of the foregoing teachings. The exemplary embodiments have been selected and described for the purpose of explaining the specific principles of the invention and their practical application, thereby enabling those skilled in the art to realize and utilize a variety of exemplary embodiments of the invention and various options and modifications. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A packaging structure, characterized in that: include: A chip unit comprises a first surface and a second surface opposite to each other, the first surface having a sensing area and a solder pad, the solder pad being electrically coupled to the sensing area, the second surface of the chip unit being provided with a via hole penetrating the chip unit, the via hole being used to expose the solder pad, the chip unit having a thickness of less than 60 μm, and a depth of the via hole being less than a width of the via hole; a protective cover plate, opposite to the first surface of the chip unit; a substrate, opposite to the second surface of the chip unit, with a through hole in communication with the via hole formed on the substrate, the substrate being bonded to the second surface of the chip unit, and having a thickness of 100 μm to 120 μm; an insulating layer, covering at least an inner wall of the via hole; The soldering protrusion is arranged on a surface of the substrate facing away from the chip unit, and the soldering protrusion is electrically connected to the soldering pad via a redistribution layer arranged in the via hole and the through hole.

2. The packaging structure according to claim 1, wherein: The via hole is a straight through hole, and / or The through hole is a straight through hole.

3. The packaging structure according to claim 1, wherein: The width of the via hole is 40 μm to 60 μm.

4. The packaging structure according to claim 1, wherein: The material of the substrate is selected from glass.

5. The packaging structure according to claim 1, wherein: It also includes a supporting structure, which is located between the first surface of the chip unit and the protective cover. The sensing area is located in a groove surrounded by the supporting structure and the protective cover.

6. A packaging method, characterized in that: include: Providing a chip unit, the chip unit comprising a first surface and a second surface opposite to each other, the first surface having a sensing area and a soldering pad, the soldering pad being electrically coupled to the sensing area; Providing a protective cover, and bonding the protective cover to the first surface of the chip unit; Thinning the second surface of the chip unit to control the thickness of the chip unit to be less than 60 μm; forming a via hole penetrating the chip unit on the second surface of the chip unit, wherein the via hole exposes the pad, and a depth of the via hole is smaller than a width of the via hole; forming an insulating layer covering the sidewalls of the via hole; Providing a substrate, bonding the substrate to the second surface of the chip unit, wherein the thickness of the substrate is 100 μm to 120 μm; forming a through hole on the substrate that communicates with the via hole; A welding protrusion is formed on a surface of the substrate away from the chip unit, and the welding protrusion is electrically connected to the welding pad through a redistribution layer arranged in the via hole and the through hole.

7. A packaging method for manufacturing the packaging structure according to any one of claims 1 to 5, characterized in that: include: A wafer is provided, wherein the wafer includes a plurality of chip units arranged in an array, each of the chip units includes a first surface and a second surface opposite to each other, the first surface has a sensing area and a bonding pad, and the bonding pad is electrically coupled to the sensing area; Providing a protective cover, and bonding the protective cover to the first surface of the chip unit; Thinning the second surface of the chip unit to control the thickness of the chip unit to be less than 60 μm; forming a via hole penetrating the chip unit on the second surface of the chip unit, wherein the via hole exposes the pad, and a depth of the via hole is smaller than a width of the via hole; forming an insulating layer covering the sidewalls of the via hole; Providing a substrate, bonding the substrate to the second surface of the chip unit, wherein the thickness of the substrate is 100 μm to 120 μm; forming a through hole on the substrate that communicates with the via hole; Making a soldering bump on a surface of the substrate away from the chip unit, wherein the soldering bump is electrically connected to the soldering pad via a redistribution layer provided in the via hole and the through hole; The wafer is divided by a cutting process to form a packaging structure of multiple chip units.

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