Ultra-wideband wafer-level packaging matching structure

Abstract

The present application relates to an ultra-wideband wafer-level packaging matching structure, comprising: a chip wafer-level packaging portion and a PCB portion. The chip wafer-level packaging portion comprises: a packaging substrate, a chip, a first passivation layer, an RDL, a second passivation layer, an UBM, and solder balls. The chip comprises: a functional surface, a bottom surface, and a chip pad; the bottom surface of the chip is embedded in the packaging substrate, with the functional surface of the chip exposed; the first passivation layer comprises: a first passivation layer metal via; the first passivation layer is disposed outside the functional surface of the chip, and the center of the first passivation layer metal via is aligned with the center of the chip pad; the RDL comprises: an RDL signal line and an RDL metal ground; the RDL is disposed outside the first passivation layer; the UBM comprises: a signal UBM and a ground UBM; the UBM is disposed in the second passivation layer; the second passivation layer is disposed outside the RDL; the chip is vertically interconnected with the PCB portion via solder balls; wherein the RDL signal line is provided with a matching node for adjusting the impedance mismatch between the first passivation layer metal via and the signal UBM.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to an ultra-wideband wafer-level packaging matching structure. Background Art

[0002] With the continuous advancement of semiconductor technology, various wireless devices are moving towards higher frequencies and smaller sizes. The integrated chip industry is also experiencing rapid growth. To meet the demands for high integration, high reliability, low cost, and easy assembly, various chip packaging methods have become the preferred method. Wafer-level packaging (WLP) offers stable chip units, high integration, strong reliability, excellent mechanical protection, and a high cost-performance ratio. It effectively meets the packaging needs of the industry and has become the mainstream technology for IC chip packaging. Wafer-level packaging is generally defined as a packaging method in which most or all of the process steps to form the package are completed on intact, uncut wafers. Unlike the traditional process of dicing followed by packaging and testing, WLP performs the entire packaging process, including packaging and bumping, directly on the wafer after the previous wafer preparation process has been completed. Products produced using wafer-level packaging technology, such as processors, sensors, and communication modules, have gained a significant market share. The terminals of wafer-packaged chips are primarily connected vertically to the printed circuit board (PCB) substrate via ball grid array (BGA) solder balls, achieving three-dimensional vertical interconnection. The chip and PCB are interconnected through solder balls. At low frequencies, there is no need to worry too much about signal leakage and reflection. However, the packaging of high-speed and high-resolution RF chips in the existing technology is constantly improving. When the frequency reaches the millimeter wave level, the mismatch between the impedance of the solder balls and the impedance on the PCB board cannot be ignored. Severe mismatch will cause RF signal reflection, thereby damaging the quality of the transmitted signal. Summary of the Invention

[0003] In order to at least to some extent overcome the problem in the related art that severe impedance mismatch may cause RF signal reflection and thus damage the quality of the transmitted signal, the present application provides an ultra-wideband wafer-level packaging matching structure.

[0004] The scheme of this application is as follows:

[0005] An ultra-wideband wafer-level packaging matching structure, comprising:

[0006] Chip wafer level packaging part and PCB part;

[0007] The chip wafer-level packaging part includes: a packaging substrate, a chip, a first passivation layer, a redistribution layer (RDL), a second passivation layer, an under bump metallurgy (UBM) and solder balls;

[0008] The chip comprises: a functional surface, a bottom surface and a chip pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed;

[0009] The first passivation layer includes: a first passivation layer metal through hole; the first passivation layer is arranged outside the functional surface of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip pad;

[0010] The RDL includes: an RDL signal line and an RDL metal ground; the RDL is arranged outside the first passivation layer;

[0011] The UBM includes: a signal UBM and a ground UBM; the UBM is arranged in the second passivation layer;

[0012] The second passivation layer is disposed outside the RDL;

[0013] The chip is vertically interconnected with the PCB portion via the solder balls;

[0014] The RDL signal line is provided with a matching node for adjusting the impedance mismatch between the first passivation layer metallization through hole and the signal UBM.

[0015] Preferably, in one achievable manner of the present application, the PCB portion includes: a PCB pad, a high-resistance line, a Klopfenstein gradient line, a microstrip line, and a dielectric substrate;

[0016] The PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line are arranged on the dielectric substrate;

[0017] The chips are vertically interconnected via the solder balls and the PCB pads;

[0018] The PCB pad is connected to the high-resistance line;

[0019] The Klopfenstein gradient lines are respectively connected to the high-resistance line and the microstrip line.

[0020] Preferably, in an achievable manner of the present application, the RDL metal grounding is symmetrically distributed on both sides of the RDL signal line.

[0021] Preferably, in one achievable manner of the present application, the RDL metal ground is provided with an opening avoidance above the microstrip line; and the size of the opening avoidance is adjustable.

[0022] Preferably, in an achievable manner of the present application, the ratio of the radius of the opening avoidance to the radius of the UBM is 1.5:1.

[0023] Preferably, in an achievable manner of the present application, the ratio of the radius of the solder ball to the radius of the UBM is 0.8:1;

[0024] The ratio between the radius of the PCB pad and the radius of the solder ball is 1.2:1.

[0025] Preferably, in one implementable manner of the present application, the ground UBM is distributed around the signal UBM in a quasi-coaxial manner.

[0026] Preferably, in one achievable manner of the present application, the solder balls include: signal solder balls and ground solder balls;

[0027] The ground solder balls are distributed around the signal solder balls in a quasi-coaxial manner.

[0028] Preferably, in an achievable method of the present application, the dielectric substrate includes: a substrate surface layer and an underlying metal ground layer; the substrate surface layer is arranged on both sides of the PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line, and there is a gap to avoid them.

[0029] Preferably, in one achievable manner of the present application, the size of the matching section and the parameters of the Klopfenstein gradient line have a preset corresponding relationship.

[0030] The technical solution provided by this application may have the following beneficial effects: The ultra-wideband wafer-level packaging matching structure of this application includes: a chip wafer-level packaging portion and a PCB portion, wherein the chip wafer-level packaging portion includes: a packaging substrate, a chip, a first passivation layer, an RDL, a second passivation layer, an UBM, and solder balls. The chip includes: a functional surface, a bottom surface, and a chip pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed; the first passivation layer includes: a first passivation layer metal via; the first passivation layer is arranged outside the functional surface of the chip, and the center of the first passivation layer metal via is aligned with the center of the chip pad; the RDL includes: an RDL signal line and an RDL metal ground; the RDL is arranged outside the first passivation layer; the UBM includes: a signal UBM and a ground UBM; the UBM is arranged in the second passivation layer; the second passivation layer is arranged outside the RDL; the chip is vertically interconnected with the PCB portion via the solder balls; wherein the RDL signal line is provided with a matching node for adjusting the impedance mismatch between the first passivation layer metal via and the signal UBM. In this application, since the RDL signal line is provided with a matching node, the impedance mismatch between the first passivation layer metallized through hole and the signal UBM can be adjusted, thereby preliminarily achieving impedance matching between the core pad and the UBM and improving signal transmission performance.

[0031] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0033] Figure 1 This is a structural diagram of an ultra-wideband wafer-level packaging matching structure provided by an embodiment of the present application;

[0034] Figure 2 This is a schematic structural diagram of a chip wafer-level packaging portion in an ultra-wideband wafer-level packaging matching structure provided by one embodiment of the present application;

[0035] Figure 3 This is a structural schematic diagram of the PCB portion of an ultra-wideband wafer-level packaging matching structure provided by an embodiment of the present application.

[0036] Figure 1: Chip wafer-level packaging part-100; packaging substrate-110; chip-120; first passivation layer-131; second passivation layer-132; RDL-140; functional surface of the chip-150; chip pad-152; UBM-160; solder ball-170; PCB part-200; PCB pad-210; high-resistance line-220; Klopfenstein gradient line-230; microstrip line-240. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0038] An ultra-wideband wafer-level packaging matching structure, referring to Figure 1-Figure 2 ,include:

[0039] Chip 120 wafer level packaging part 100 and PCB part 200;

[0040] The wafer-level packaging part 100 of the chip 120 includes: a packaging substrate 110 , a chip 120 , a first passivation layer 131 , an RDL 140 , a second passivation layer 132 , a UBM 160 and solder balls 170 ;

[0041] The chip 120 includes a functional surface, a bottom surface, and a chip pad 152. The bottom surface of the chip 120 is embedded in the package substrate 110, and the functional surface 150 of the chip is exposed.

[0042] The first passivation layer 131 includes: a first passivation layer metal through hole; the first passivation layer 131 is arranged outside the functional surface 150 of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip pad 152;

[0043] The RDL 140 includes: an RDL signal line and an RDL metal ground; the RDL 140 is disposed outside the first passivation layer 131;

[0044] The UBM 160 includes a signal UBM and a ground UBM; the UBM 160 is disposed in the second passivation layer 132;

[0045] The second passivation layer 132 is disposed outside the RDL 140 ;

[0046] Chip 120 is vertically interconnected via solder balls 170 and PCB portion 200;

[0047] The RDL signal line is provided with a matching node for adjusting the impedance mismatch between the metallized through hole of the first passivation layer 131 and the signal UBM.

[0048] In this embodiment, the second passivation layer 132 is mainly used to protect the RDL 140 layer.

[0049] The ultra-wideband wafer-level packaging matching structure in this embodiment includes: a chip 120 wafer-level packaging part 100 and a PCB part 200. The chip 120 wafer-level packaging part 100 includes: a packaging substrate 110, a chip 120, a first passivation layer 131, an RDL 140, a second passivation layer 132, a UBM 160 and solder balls 170. The chip 120 includes: a functional surface, a bottom surface and a chip pad 152; the bottom surface of the chip 120 is embedded in the package substrate 110, and the functional surface 150 of the chip is exposed; the first passivation layer 131 includes: a first passivation layer metal through hole; the first passivation layer 131 is arranged outside the functional surface 150 of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip pad 152; the RDL 140 includes: an RDL signal line and an RDL metal ground; the RDL 140 is arranged outside the first passivation layer 131; the UBM 160 includes: a signal UBM and a ground UBM; the UBM 160 is arranged in the second passivation layer 132; the second passivation layer 132 is arranged outside the RDL 140; the chip 120 is vertically interconnected with the PCB part 200 through the solder ball 170; wherein, the RDL signal line is provided with a matching node for adjusting the impedance mismatch between the metallized through hole of the first passivation layer 131 and the signal UBM. In this embodiment, since the RDL signal line is provided with a matching node, the impedance mismatch between the metallized through hole of the first passivation layer 131 and the signal UBM can be adjusted, thereby preliminarily achieving impedance matching between the core pad and the UBM 160 and improving signal transmission performance.

[0050] In some embodiments, the ultra-wideband wafer-level packaging matching structure is described with reference to Figure 3 The PCB portion 200 includes: a PCB pad 210, a high-resistance line 220, a Klopfenstein gradient line 230, a microstrip line 240 and a dielectric substrate;

[0051] The PCB pad 210, the high-resistance line 220, the Klopfenstein gradient line 230 and the microstrip line 240 are arranged on a dielectric substrate;

[0052] Chip 120 is vertically interconnected via solder balls 170 and PCB pads 210;

[0053] The PCB pad 210 is connected to the high resistance line 220;

[0054] The Klopfenstein gradient line 230 connects the high-resistance line 220 and the microstrip line 240 .

[0055] Preferably, the PCB pad 210 may be, but is not limited to, a circular PCB pad 210 .

[0056] Preferably, the microstrip line 240 may be, but is not limited to, a 50-ohm microstrip line.

[0057] The high-resistance line 220 in this embodiment is used to match the capacitive effect brought by the PCB pad 210 .

[0058] The Klopfenstein gradient line 230 is used to connect the high-resistance line 220 and the 50-ohm microstrip line 240 to achieve broadband impedance transformation.

[0059] Preferably, in this embodiment, the dielectric substrate is a Rogers 3003 substrate with a thickness of 0.127 mm, and the corresponding microstrip line 240 has a width of about 0.3 mm.

[0060] In the ultra-wideband wafer-level packaging matching structure in some embodiments, the RDL metal grounding is symmetrically distributed on both sides of the RDL signal line.

[0061] In this embodiment, the RDL metal grounding is symmetrically distributed on both sides of the RDL signal line to form a coplanar waveguide transmission line.

[0062] In the ultra-wideband wafer-level packaging matching structure in some embodiments, an RDL metal ground is provided with an opening above the microstrip line 240 ; and the size of the opening is adjustable.

[0063] In this embodiment, the RDL metal ground is provided with an opening above the microstrip line 240 to avoid the spatial radiation of the microstrip line 240 of the PCB part 200 from being reflected, which significantly improves the signal transmission performance.

[0064] Furthermore, the radius of the opening avoidance is compared to that of the UBM160 at a ratio of 1.5:1;

[0065] The radius of the solder ball 170 and the radius of the UBM 160 have a ratio of 0.8:1;

[0066] The ratio between the radius of the PCB pad 210 and the radius of the solder ball 170 is 1.2:1.

[0067] Preferably, the radius of the UBM 160 is 100 μm, the radius of the opening avoidance is 150 μm, the radius of the solder ball 170 is 125 μm, and the radius of the PCB pad 210 is 50 μm.

[0068] In the ultra-wideband wafer-level packaging matching structure of some embodiments, the ground UBM is distributed around the signal UBM in a quasi-coaxial manner.

[0069] Furthermore, the solder balls 170 include: signal solder balls and ground solder balls;

[0070] The ground solder balls are distributed around the signal solder balls in a quasi-coaxial manner.

[0071] In this embodiment, the UBM 160 layer and the solder balls 170 are in a similar distributed structure, which is used for interconnecting the RDL signal lines, the RDL metal grounding and the solder balls 170 .

[0072] The ground solder balls are distributed in a quasi-coaxial manner around the signal solder balls, which can greatly restrain the signal and prevent leakage, and play a great role in improving the transmission characteristics of the signal in the millimeter wave frequency band.

[0073] For the sake of PCB processability, some changes can be made to the quasi-coaxial structure in this embodiment during specific implementation, and it does not need to be evenly distributed.

[0074] In this embodiment, the chip 120 is soldered to the PCB pad 210 via signal solder balls.

[0075] In some embodiments of the ultra-wideband wafer-level packaging matching structure, the dielectric substrate includes: a substrate surface layer and an underlying metal ground layer; the substrate surface layer is arranged on both sides of the PCB pad 210, the high-resistance line 220, the Klopfenstein gradient line 230 and the microstrip line 240, and there is a gap to avoid them.

[0076] Preferably, refer to Figure 3 The avoidance radius of the substrate surface of the PCB pad 210 is 300 μm; the avoidance distance from the substrate surface to the axis 2 is 400 μm; the length of the high-resistance line 220 is 200 μm and the width is 150 μm.

[0077] In some embodiments of the ultra-wideband wafer-level packaging matching structure, the size of the matching section has a preset corresponding relationship with the parameters of the Klopfenstein gradient line 230 .

[0078] Specifically, the calculation formula for the size of the Klopfenstein gradient line 230 is as follows:

[0079]

[0080] Among them, Z L and Z0 are the load impedance and source impedance of the gradient line, I1(x) is the modified Bessel function, Γ m Is the maximum reflection coefficient in the passband. In actual design, the N-segment impedance matching section transformer is infinitely close to the Klopfenstein tapered line. When Z is given L , Z0, N and Γ m When the Klopfenstein gradient line 230 is required, the required size can be accurately calculated through MATLAB programming.

[0081] Preferably, in this embodiment, N is set to 20, Γ m The impedance distribution is 30 dB. Based on the above formula, the detailed impedance distribution is calculated by MATLAB programming. Finally, the length of the Klopfenstein gradient line 230 is about 700 μm.

[0082] In this embodiment, when the Klopfenstein gradient line 230 defines the maximum reflection coefficient specification within the passband, the Klopfenstein gradient line 230 may provide the shortest matching section.

[0083] In summary, the ultra-wideband wafer-level packaging matching structure in this embodiment greatly improves the parasitic effects brought by the interconnection structure of the solder ball 170 by setting a matching node on the RDL140 layer, adjusting the opening avoidance radius of the RDL metal grounding, setting a quasi-coaxially distributed solder ball 170, and setting a high-resistance line 220 Klopfenstein tapered gradient line on the PCB. Compared with the traditional quarter-wavelength impedance transformation node matching structure, wide-band matching is achieved through the impedance gradient line.

[0084] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0085] It should be noted that, in the description of this application, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0086] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0087] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0088] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0089] In addition, the functional units in the various embodiments of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into a module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0090] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0091] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0092] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An ultra-wideband wafer-level packaging matching structure, characterized in that: include: Chip wafer level packaging part and PCB part; The chip wafer level packaging part includes: a packaging substrate, a chip, a first passivation layer, an RDL, a second passivation layer, a UBM and solder balls; The chip comprises: a functional surface, a bottom surface and a chip pad; the bottom surface of the chip is embedded in the packaging substrate, and the functional surface of the chip is exposed; The first passivation layer includes: a first passivation layer metal through hole; the first passivation layer is arranged outside the functional surface of the chip, and the center of the first passivation layer metal through hole is aligned with the center of the chip pad; The RDL includes: an RDL signal line and an RDL metal ground; the RDL is arranged outside the first passivation layer; The UBM includes: a signal UBM and a ground UBM; the UBM is arranged in the second passivation layer; The second passivation layer is disposed outside the RDL; The chip is vertically interconnected with the PCB portion via the solder balls; The RDL signal line is provided with a matching node for adjusting the impedance mismatch between the first passivation layer metallized through hole and the signal UBM; The PCB part includes: PCB pads, high-resistance lines, Klopfenstein gradient lines, microstrip lines and dielectric substrates; The PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line are arranged on the dielectric substrate; The chips are vertically interconnected via the solder balls and the PCB pads; The PCB pad is connected to the high-resistance line; The Klopfenstein gradient lines are connected to the high-resistance line and the microstrip line respectively; The RDL metal ground is symmetrically distributed on both sides of the RDL signal line; The RDL metal ground is provided with an opening above the microstrip line; the size of the opening is adjustable; The ground UBM is distributed around the signal UBM in a quasi-coaxial manner; The solder balls include: signal solder balls and ground solder balls; The ground solder balls are distributed around the signal solder balls in a quasi-coaxial manner.

2. The ultra-wideband wafer-level packaging matching structure according to claim 1, wherein: The ratio between the radius of the opening avoidance and the radius of the UBM is 1.5:

1.

3. The ultra-wideband wafer-level packaging matching structure according to claim 1, wherein: The ratio between the radius of the solder ball and the radius of the UBM is 0.8:1; The ratio between the radius of the PCB pad and the radius of the solder ball is 1.2:

1.

4. The ultra-wideband wafer-level packaging matching structure according to claim 1, wherein: The dielectric substrate includes: a substrate surface layer and a bottom metal ground layer; the substrate surface layer is arranged on both sides of the PCB pad, the high-resistance line, the Klopfenstein gradient line and the microstrip line, and there is a gap to avoid them.

5. The ultra-wideband wafer-level packaging matching structure according to claim 1, wherein: The size of the matching section and the parameters of the Klopfenstein gradient line have a preset corresponding relationship.

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