Semiconductor structure with vertical gate transistors and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for fabricating the same. The semiconductor structure includes: a substrate, a unit cell capacitor, a channel structure, a pad material, a word line, and a bit line. The unit cell capacitor is disposed on the substrate. The channel structure is disposed on the unit cell capacitor, wherein the channel structure includes a horizontal component and at least two vertical components extending from the horizontal component and separated by a channel on the horizontal component. The pad material surrounds each vertical component. The word line surrounds the at least two vertical components and partially fills the channel. The bit line is disposed on the channel structure.

Description

[0001] Cross-references

[0002] This disclosure claims priority and benefits to U.S. Official Application No. 17 / 079,943, filed October 26, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor structure and a method for fabricating the same. In particular, it relates to a semiconductor structure having a vertical gate transistor (VGT) and a method for fabricating the same. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a semiconductor configuration for storing multiple bits of data in multiple individual cell capacitors (cell capacitors) located within an integrated circuit. DRAM typically takes the form of multiple trench capacitor DRAM cells and multiple stacked capacitor DRAM cells. In the stacked capacitor DRAM cell, the cell capacitors are formed on multiple read / write transistors. An advanced method for manufacturing the read / write transistors uses a buried gate electrode comprising a gate electrode and a word line, wherein the gate electrode and the word line are constructed in a gate trench within an active region.

[0005] Over the past few decades, with the continuous advancement of semiconductor manufacturing technology, the size of electronic components has shrunk accordingly. As the size of a single-cell transistor shrinks to a few nanometers, short-channel effects may occur, which can lead to a significant decrease in the performance of the single-cell transistor.

[0006] To overcome performance issues, there is a great need to improve the manufacturing methods of the transistors in semiconductor structures.

[0007] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0008] One embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate, a unit cell capacitor, a channel structure, a pad material, a word line, and a bit line. The unit cell capacitor is disposed on the substrate. The channel structure is disposed on the unit cell capacitor, wherein the channel structure includes a horizontal component and at least two separate vertical components extending from the horizontal component. The pad material is disposed around at least one vertical component. The word line is disposed surrounding the at least two vertical components. The bit line is disposed on the channel structure.

[0009] In some embodiments, the channel structure includes amorphous silicon, doped silicon, indium oxide (In2O3), gallium oxide (Ga2O3), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO).

[0010] In some embodiments, the padding material comprises dense silicon oxide (SiO2) or silicon nitride (Si3N4).

[0011] In some embodiments, the channel structure is generally a U-shaped structure.

[0012] In some embodiments, the at least two vertical components extend along a first direction, and the character line extends along a second direction orthogonal to the first direction, wherein the character line extends along the first direction.

[0013] In some embodiments, the padding material is inserted between the character line and the channel structure.

[0014] In some embodiments, the character line passes through the at least two vertical components of the channel structure.

[0015] In some embodiments, the word line and the bit line form a memory array, wherein the memory array has four square feature sizes (4F). 2 (A layout)

[0016] In some embodiments, the semiconductor structure further includes: a first oxide disposed between the at least two vertical components; and a second oxide disposed on the first oxide and between the at least two vertical components.

[0017] In some embodiments, the first oxide and the second oxide comprise silicon oxide (SiO2).

[0018] In some embodiments, the padding material partially covers the first oxide, and the second oxide partially covers the padding material.

[0019] In some embodiments, a portion of the character line is sandwiched between the first oxide and the second oxide, and between the at least two vertical components surrounded by the padding material.

[0020] In some embodiments, the second oxide is inserted between the at least two vertical components of the channel structure.

[0021] In some embodiments, the at least two vertical components include a first portion and a second portion disposed above and below the padding material, respectively.

[0022] In some embodiments, the first portion is electrically connected to the bit line, and the second portion is electrically connected to the cell capacitor via the horizontal component.

[0023] In some embodiments, the character line is inserted between the first portion and the second portion and is electrically coupled to the character line and the cell capacitor via the channel structure.

[0024] Another embodiment of this disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate, a bit line, a channel structure, a pad material, a word line, and a unit cell capacitor. The bit line is disposed on the substrate. The channel structure is disposed on the bit line, wherein the channel structure includes a horizontal component and at least two separate vertical components extending from the horizontal component. The pad material is disposed around the at least two vertical components. The word line is disposed surrounding the at least two vertical components. The unit cell capacitor is disposed on the channel structure.

[0025] Another embodiment of this disclosure provides a method for fabricating a semiconductor structure. The method includes: providing a substrate; forming a unit cell capacitor on the substrate; forming a channel material on the unit cell capacitor; cutting the channel material to form a channel structure, wherein the channel structure includes a horizontal component and at least two vertical components, the at least two vertical components being separated by a channel on the horizontal component; forming a pad material on each sidewall of the at least two vertical components; forming a word line to surround the at least two vertical components surrounded by the pad material and partially fill the channel; and forming a bit line on the channel structure.

[0026] In some embodiments, after the character line is formed, a second oxide is formed on the character line located in the channel and on the first oxide.

[0027] In some embodiments, after the character line is formed, a second oxide is formed on the character line located in the channel and on the first oxide.

[0028] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0029] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0030] Figure 1A Examples of some embodiments of this disclosure have 6F 2 A top view schematic diagram of a portion of the first memory array layout.

[0031] Figure 1B Examples of some embodiments of this disclosure have 4F 2 A top view schematic diagram of a portion of a second memory array layout.

[0032] Figure 2A A three-dimensional schematic diagram illustrating a first semiconductor structure according to some embodiments of the present disclosure is shown.

[0033] Figure 2B A cross-sectional schematic diagram illustrating some embodiments of the present disclosure of a second semiconductor structure is shown.

[0034] Figure 3 Examples of some embodiments of this disclosure are shown in Figure 2A A schematic flowchart of the fabrication method of the first semiconductor structure is shown.

[0035] Figures 4 to 5 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0036] Figure 6A Examples of some embodiments of this disclosure Figure 5 A three-dimensional schematic diagram.

[0037] Figure 6B Examples of other embodiments of this disclosure Figure 5 A three-dimensional schematic diagram.

[0038] Figures 7 to 9 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0039] Figure 10A Examples of some embodiments of this disclosure Figure 9 A three-dimensional schematic diagram.

[0040] Figure 10B Examples of other embodiments of this disclosure Figure 9 A three-dimensional schematic diagram.

[0041] Figure 11 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0042] Figure 12 Examples of some embodiments of this disclosure Figure 11 A plan view.

[0043] Figures 13 to 14 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0044] Figure 15 Examples of some embodiments of this disclosure Figure 14 A plan view.

[0045] Figure 16 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0046] Figure 17 Examples of some embodiments of this disclosure Figure 16 A plan view.

[0047] Figures 18A to 18C A plan view illustrating a multi-channel structure coupled by a single character line in some embodiments of this disclosure is shown.

[0048] Figure 19 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0049] Figure 20 Examples of some embodiments of this disclosure Figure 19 A plan view.

[0050] Figure 21 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0051] Figure 22 Examples of some embodiments of this disclosure are shown below. Figure 21 Another cross-sectional view shown from a second direction.

[0052] Figure 23 Examples of some embodiments of this disclosure Figure 21 A three-dimensional schematic diagram.

[0053] Figure 24 A cross-sectional schematic diagram illustrating some embodiments of the present disclosure of a second semiconductor structure is shown.

[0054] Explanation of reference numerals in the attached figures:

[0055] 100: Base

[0056] 110: Unit cell capacitor

[0057] 112: Upper electrode

[0058] 114: Capacitor dielectric

[0059] 116: Lower electrode

[0060] 120: Channel Structure

[0061] 120A: Channel material

[0062] 122: Horizontal Component

[0063] 124: Vertical Components

[0064] 126: Part One

[0065] 128: Part Two

[0066] 130: First oxide

[0067] 140: Padding material

[0068] 150: Character Line

[0069] 150P: Partial

[0070] 152: Gate section

[0071] 160: Second oxide

[0072] 170: Bitline

[0073] 180: Unit cell transistor

[0074] 200: First semiconductor structure

[0075] 300: Second semiconductor structure

[0076] 400: Preparation method

[0077] A1: First memory array

[0078] A2: Second memory array

[0079] AA1: Active Zone

[0080] AA2: Active Zone

[0081] BL1: Bitline

[0082] BL2: Bitline

[0083] D1: First Direction

[0084] D2: Second Direction

[0085] D3: Third direction

[0086] hv1: Radiation

[0087] MA: Photomask

[0088] O1: Opaque area

[0089] P1: Pitch

[0090] PR1: Photoresist layer

[0091] PR2: Photoresist pattern

[0092] R1: Ditch

[0093] S101: Steps

[0094] S103: Steps

[0095] S105: Steps

[0096] S107: Steps

[0097] S109: Steps

[0098] S111: Steps

[0099] S113: Steps

[0100] S115: Steps

[0101] S117: Steps

[0102] T1: Transparent area

[0103] WL1: Bitline

[0104] WL2: Bitline

[0105] θ: Predetermined angle Detailed Implementation

[0106] Embodiments or examples of the present disclosure shown in the accompanying drawings will now be described using specific language. It should be understood that the scope of this disclosure is not intended to be limited thereto. Any modifications or improvements to the described embodiments, and any further applications of the principles described herein, will be considered commonplace by those skilled in the art. Component numbers may be repeated throughout the embodiments, but this does not necessarily mean that a feature of one embodiment is applicable to another embodiment, even if they share the same component numbers.

[0107] It should be understood that while the terms “first,” “second,” “third,” etc., may be used in this text to describe different elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish an element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, the terms “first element,” “component,” “region,” “layer,” or “section” discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this text.

[0108] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0109] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0110] Dynamic Random Access Memory (DRAM) has been developed to overcome inherent scaling limitations and improve the cost-effectiveness of mass production. DRAM scaling has made significant progress through the use of a trench capacitor structure and a stacked capacitor structure. The size of a single memory cell, having one cell transistor and one cell capacitor, has been reduced through the evolution of a memory array layout from a hexagonal feature size (6F). 2 It evolved into a square feature size (4F) 2 In particular, the minimum feature size F shrinks with each new generation, and when the unit cell size is generally αF... 2 In this case, α is a coefficient that decreases as generations progress.

[0111] 6F 2 With 4F 2 The main difference between the layouts is that the 4F 2 The unit cell structure is implemented using a vertical transistor, while 6F 2 The unit cell structure is implemented using buried channel array transistors (BCAT). Because of the minimum area of ​​the unit cell, 4F... 2 The cell architecture is a promising architecture for cost-effective and scalable DRAM chips. Due to its vertical transistor design, 4F... 2 A single cell can be larger than 6F 2 This is achieved with a 33% smaller area; therefore, it reduces the area of ​​the memory cell array. The vertical transistors exhibit excellent retention characteristics in static mode. Even in pillar-type channels, floating-body effects can be reduced by using a gradient junction profile. However, 4F 2 DRAM cell has significant drawbacks: the complex integration process required for structure formation and the floating-body effect (FBE) caused by the vertical transistors.

[0112] In silicon-on-insulator (SOI) technology, a threshold voltage (FBE) is a critical voltage (V) of the transistor. thThe phenomenon of voltage fluctuations occurs because the body of a transistor does not have a specific fixed voltage value during operation. When the gate of the transistor is turned off, a potential well is formed in the body region. Electron / hole pairs are generated by gate-induced drain leakage (GIDL) in the junction region, and the generated holes accumulate in the body potential well. In other words, the critical voltage of a transistor depends on its bias voltage and the history of carrier recombination. FBE is a voltage fluctuation that causes voltage fluctuations in the body region of an SOI metal-oxide-semiconductor field-effect transistor (MOSFET), which adversely affects the operation of SOI devices. The most common of these adverse effects are the kink effect and the bipolar effect. As the channel region of the device is partially depleted and a high drain voltage is applied, an electric field generated in the device leads to impact ionization near the drain region.

[0113] To avoid free beam overlap (FBE) and reduce leakage current in transistors in low-power applications, non-silicon-based materials are used in 4F... 2 Unit cell structures exhibit great potential due to their inherently high band gap. However, several high-temperature processes can affect the electronic properties of non-silicon-based materials. For example, many non-silicon-based materials are heat-sensitive and may decompose under these high-temperature processes. The fabrication of a unit cell capacitor typically involves numerous high-temperature processes.

[0114] Therefore, when the thermosensitive non-silicon-based material is used in the fabrication of the unit cell transistor, the processes for the unit cell capacitor and the unit cell transistor should be separate, and a capacitor-first process should be employed. However, practical application is not easy because at 4F... 2 There are technical difficulties in DRAM, as the unit cell transistors must be of a vertical type. Therefore, there is still a great need to improve the manufacturing method of vertical transistors.

[0115] Figure 1A Examples of some embodiments of this disclosure have 6F 2 A top view schematic diagram of a portion of the layout of a first memory array A1. Figure 1AIn this configuration, multiple character lines WL1 are orthogonal to multiple bit lines BL1. In some embodiments, the width of each character line WL1 and the width of each bit line BL1 are 1F, where F is a minimum feature size. In some embodiments, the distance between any two adjacent character lines WL1 and the distance between any two adjacent bit lines BL1 are also 1F. (In 6F) 2 In the layout, an active region AA1 is orthogonally positioned relative to the extension direction of word line WL1 or bit line BL1. Within the active region AA1, multiple memory cells (not shown) located at the intersection of word line WL1 and bit line BL1 are electrically coupled to both word line WL1 and bit line BL1. Therefore, in Figure 1A The area of ​​the memory cell in the image is approximately 3F × 2F = 6F. 2 As shown by the dashed rectangle.

[0116] Figure 1B Examples of some embodiments of this disclosure have 4F 2 A top view schematic diagram of a portion of a second memory array A2 in the layout. Figure 1B In this configuration, multiple character lines WL2 are orthogonal to multiple bit lines BL2. In some embodiments, the width of each character line WL2 and the width of each bit line BL2 are 1F. In some embodiments, the distance between any two adjacent character lines WL2 and the distance between any two adjacent bit lines BL2 are also 1F. (4F) 2 In the layout, an active region AA2 is located at the intersection of word line WL2 and bit line BL2. Furthermore, a memory cell (not shown) is located within the active region AA2 and electrically coupled to word line WL2 and bit line BL2. Therefore, in Figure 1B The area of ​​the memory cell in the image is approximately 2F × 2F = 4F. 2 As shown by the dashed rectangle.

[0117] One object of this disclosure is to provide a first semiconductor structure. Figure 2AA perspective view of a first semiconductor structure 200 illustrating some embodiments of the present disclosure is shown. In some embodiments, the first semiconductor structure 200 has a vertical gate transistor (VGT). In particular, the first semiconductor structure 200 has a substrate 100, a cell capacitor 110, a channel structure 120, a first oxide 130, a pad material 140, a word line 150, a second oxide 160, and a bit line 170. The cell capacitor 110 is disposed on the substrate 100. The channel structure 120 is disposed on the cell capacitor 110, wherein the channel structure 120 is generally a U-shaped structure and includes a horizontal component 122 and a pair of vertical components 124 located on the horizontal component 122. A channel R1 separates the pair of vertical components 124 and extends along a first direction D1. In some embodiments, the pair of vertical components 124 extends in the same direction as the channel R1. A first oxide 130 is disposed on the horizontal assembly 122 and located between the pair of vertical assemblies 124 of the channel structure 120. A liner material 140 surrounds a portion of each vertical assembly 124 and partially covers the first oxide 130. A character line 150 surrounds the portion of each vertical assembly 124 surrounded by the liner material 140 and partially fills the channel R1. The character line 150 is disposed to cover the first oxide 130 and partially fill the channel R1.

[0118] Furthermore, character line 150 passes through the vertical assembly 124 and extends along a second direction D2, which is substantially orthogonal to the first direction D1. A second oxide 160 is disposed on the character line 150 located in the channel R1 and on the first oxide 130 located within the channel structure 120. The second oxide 160 also covers a portion of the padding material 140 located in the channel R1. A portion of the character line 150 is sandwiched between the first oxide 130 and the second oxide 160, and between the pair of vertical assemblies 124 surrounded by the padding material 140. Bit line 170 is disposed on the channel structure 120 and extends along the first direction D1.

[0119] Please refer to the following: Figure 2A In the first semiconductor structure 200, the vertical component 124 of the channel structure 120 has a first portion 126 and a second portion 128, which are respectively disposed above and below the pad material 140. In some embodiments, the first portion 126 can be used as a source or drain terminal, and the second portion 128 can be used as a source or drain terminal. That is, when the first portion 126 is used as a source terminal, the second portion 128 is used as a drain terminal, and so on. In addition, a portion of the word line 150 can be used as a gate terminal. Therefore, the first portion 126, the second portion 128, and a portion of the word line 150 can form a vertical transistor.

[0120] Furthermore, the pad material 140 can serve as a gate dielectric layer, separating the vertically oriented transistor from its underlying source and drain terminals. The first portion 126 is electrically connected to the bit line 170, and the second portion 128 is electrically connected to the cell capacitor 110 via the horizontal assembly 122. Additionally, the word line 150 is interposed between the first portion 126 and the second portion 128, and is electrically coupled to the bit line 170 and the cell capacitor 110 via the channel structure 120. The word line 150 and the bit line 170 can form a memory array having four square feature sizes (4F). 2 (A layout)

[0121] Another objective of this disclosure is to provide a second semiconductor structure. Figure 2B A cross-sectional schematic diagram of a second semiconductor structure 300 is shown, illustrating some embodiments of the present disclosure. In some embodiments, the second semiconductor structure 300 also has a VGT. The second semiconductor structure 300 is similar to the first semiconductor structure 200, except that the bit line 170 is formed before the unit cell capacitor 110 is formed. At this time, the bit line 170 is formed on the substrate 100, and the unit cell capacitor 110 is located at the intersection of the word line 150 and the bit line 170.

[0122] Another object of this disclosure is to provide a method for fabricating a semiconductor structure. Figure 3 Examples of some embodiments of this disclosure are shown in Figure 2A A schematic flowchart of the fabrication method 400 for the first semiconductor structure 200 is shown. In some embodiments, the fabrication method 400 is a capacitor-first process, for example, a unit cell capacitor is formed before a bit line is formed. Figures 4 to 5 , Figures 7 to 9 , Figure 11 , Figures 13 to 14 , Figure 16 , Figure 19 as well as Figure 21 Some embodiments of this disclosure are illustrated in the following: Figure 3 The diagram shows the sequential cross-sectional views of each manufacturing stage in the preparation method described above.

[0123] Please refer to Figure 4 ,in accordance with Figure 3 Step S101 involves providing a substrate 100. In some embodiments, the substrate 100 may be a single-crystal silicon substrate, a polycrystalline silicon substrate, a compound semiconductor substrate, or any other suitable substrate, and the compound semiconductor substrate may be, for example, a silicon germanium (SiGe) substrate, a gallium arsenide (GaAs) substrate, or a silicon-on-insulator (SOI) substrate.

[0124] Please refer to the following: Figure 4 ,in accordance with Figure 3 In step S103, a unit cell capacitor 110 is formed on the substrate 100. The unit cell capacitor 110 is used to store a charge, which is a bit representing data. In some embodiments, the unit cell capacitor 110 is electrically coupled to the substrate 100 via a plurality of landing pads (not shown). Furthermore, the material of the landing pads includes, but is not limited to, tungsten, copper, aluminum, or alloys thereof.

[0125] It should be understood that Figure 4 The unit cell capacitor 110 shown is for illustrative purposes only and does not depict a detailed structure. In some embodiments, the unit cell capacitor 110 includes at least an upper electrode 112, a capacitor dielectric material 114, and a lower electrode 116. The capacitor dielectric material 114 is enclosed by the upper electrode 112 and the lower electrode 116. In some embodiments, the upper electrode 112 and the lower electrode 116 may be a conductor, such as a metal, alloy, or polycrystalline silicon. The capacitor dielectric material 114 may comprise one or more high-k dielectric materials, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide, or the like. In some embodiments, the unit cell capacitor 110 may be a capacitor of any shape known in the art. For example, the unit cell capacitor 110 may have a simple or complex shape; a simple shape is, for example, a rectangle, and a complex shape is, for example, multiple concentric cylinders or multiple stacked discs.

[0126] In some embodiments, capacitor 110 may be surrounded by an interlayer dielectric (not shown) deposited on substrate 100. In some embodiments, the interlayer dielectric primarily comprises oxides, such as silicon oxide, tetraethylorthosilicate (TEOS), boron phosphorus silicate glass (BPSG), undoped silicate glass (USG), or other suitable materials. In some embodiments, the interlayer dielectric may be formed sequentially with the steps of fabrication method 200, depending on actual process requirements. Furthermore, the height of the interlayer dielectric can be controlled to selectively expose a device. For clarity, the interlayer dielectric is not shown in the figures in this disclosure.

[0127] Please refer to Figure 5 ,in accordance with Figure 3In step S105, a channel material 120A is formed on the unit cell capacitor 110. Specifically, the fabrication technology used for the channel material 120A is, for example, a sputtering process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process. In some embodiments, the channel material 120A includes amorphous silicon, doped silicon, and a metal oxide semiconductor, wherein the metal oxide semiconductor is, for example, indium oxide (In2O3), gallium oxide (Ga2O3), zinc oxide (ZnO), indium zinc oxide (IZO), indium tin oxide (ITO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide (IGZO), but is not limited thereto.

[0128] Figure 6A Examples of some embodiments of this disclosure Figure 5 A three-dimensional schematic diagram. In some embodiments, the channel material 120A is shaped as a square column, a rectangular column, or a polygonal column. For example... Figure 6A The channel material 120A shown is a cover cell capacitor 110, which is interposed between the channel material 120A and the substrate 100. In other embodiments, such as Figure 6B As shown, the channel material 120A can be in the shape of a cylinder.

[0129] Please refer to Figures 7 to 9 ,in accordance with Figure 3 In step S107, a recess formation process is performed on the channel material 120A. Please refer to... Figure 7 A photoresist layer PR1 is formed on the channel material 120A. In some embodiments, the photoresist layer PR1 is a positive tone photoresist, characterized by the removal of multiple exposed regions using a developing agent. In some embodiments, the photoresist layer PR1 comprises a chemical amplifier (CA) photoresist. The CA photoresist includes a photoacid generator (PAG), which can be decomposed to form various acids during a photolithography exposure process. Further acid can be generated due to a catalytic reaction.

[0130] Please refer to the following: Figure 7 A photolithography process is performed on the photoresist layer PR1. The photoresist layer PR1 is exposed to radiation hv1 using a photomask MA and a photolithography system (not shown). In some embodiments, the radiation hv1 may include deep ultraviolet (DUV) radiation, but is not limited thereto. The photomask MA includes a transparent portion T1 and an opaque portion O1. In some embodiments, the photomask MA may be a binary mask, a phase shift mask, or any type of mask suitable for use in a photolithography system. The exposure includes a photochemical reaction that alters the chemical properties of some portions of the photoresist layer PR1. For example, it exposes portions of the photoresist layer PR1 corresponding to the transparent portion T1, making them more reactive to a development process. In some embodiments, a post-exposure baking (PEB) may be performed after the exposure of the photoresist layer PR1.

[0131] Next, please refer to Figure 8 The exposed photoresist layer PR1 is rinsed with a suitable developer. In some embodiments, the exposed portion of the photoresist layer PR1 reacts with the developer and can be easily removed. After the exposed photoresist layer PR1 is developed, a photoresist pattern PR2 is formed on the channel material 120A.

[0132] Next, please refer to Figure 9 The photoresist pattern PR2 is used as an etching mask to etch the channel material 120A. In some embodiments, the etching process is a RIE process, which vertically removes a portion of the channel material. During this process, a channel R1 is formed to cut the channel material 120A, thus forming a channel structure 120. The photoresist pattern PR2 is then removed using, for example, an ashing process or a wet stripping process. In some embodiments, the channel structure 120 is generally a U-shaped structure, including a horizontal component 122 and a pair of vertical components 124, the pair of vertical components 124 being located on the horizontal component 122. Furthermore, the channel R1 is also included in the channel structure 120. In some embodiments, the vertical components 124 and the channel R1 extend along a first direction D1.

[0133] Figure 10A Examples of some embodiments of this disclosure Figure 9 A three-dimensional schematic diagram. In some embodiments, the vertical components 124, separated by channels R1, are substantially rectangular columns. In other embodiments, when in such... Figure 6BWhen a recess-forming process is performed on the cylindrical channel material 120A as shown, the resulting vertical assembly 124 will be nearly semicircular columns separated by channels R1, such as... Figure 10B As shown. In some embodiments, the channel R1 is uniformly divided into two vertical components 124, for example, the two vertical components 124 are of the same size. In other embodiments, the two vertical components 124 may be of different sizes.

[0134] Please refer to Figure 11 ,in accordance with Figure 3 In step S109, a first deposition process is performed on the channel structure 120. In some embodiments, a first oxide 130 is formed to partially fill the channel R1. In particular, the first oxide 130 is deposited on the horizontal component 122 and located between the vertical components 124 of the channel structure 120. The fabrication technique of the first oxide 130 may include a low-pressure chemical vapor deposition (LPCVD) process or a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, the first oxide 130 is silicon oxide. In some embodiments, the first oxide 130 provides additional oxygen atoms to the channel structure 120 via multiple metal-oxygen (MO) bonds between the first oxide 130 and the channel structure 120.

[0135] Figure 12 Examples of some embodiments of this disclosure Figure 11 A plan view. In some embodiments, the first oxide 130 is a rectangular column located at the center of the channel structure 120. The first oxide 130 is aligned with the vertical component 124. Figure 12 In the diagram, the unit cell capacitor 110 is inserted between the channel structure 120 and the substrate 100, and therefore is not shown in the plan view.

[0136] Please refer to Figures 13 to 14 ,in accordance with Figure 3 In step S111, a lining process is performed on the channel structure 120. Please refer to... Figure 13 In some embodiments, a pad material 140 is first formed to conformally cover the vertical component 124 and the first oxide 130. In some embodiments, the pad material 140 may be fabricated using a CVD process. Preferably, the pad material 140 is fabricated using an atomic layer deposition (ALD) process to allow the formation of a highly conformal pad material with a more uniform thickness. In some embodiments, the pad material 140 comprises dense silicon oxide (SiO2) or silicon nitride (Si3N4).

[0137] Next, please refer to Figure 14Some portions of the padding material 140 are removed to expose the upper portion of the vertical assembly 124. As a result, the formed padding material 140 is applied to the sidewalls of the vertical assembly 124 of the channel structure 120. Furthermore, the padding material 140 surrounds a portion of the vertical assembly 124 and partially covers the first oxide 130. In some embodiments, the vertical assembly 124 includes a first portion 126 and a second portion 128, respectively disposed above and below the padding material 140.

[0138] Figure 15 Examples of some embodiments of this disclosure Figure 14 A plan view. In some embodiments, the padding material 140 is a hollow cylinder surrounding a waist of the vertical assembly 124. In some embodiments, the lower surface of the padding material 140 is coplanar with the upper surface 130 of the first oxide 130. Figure 15 In the diagram, a portion of the first oxide 130 is covered by the padding material 140 and is therefore not shown in the plan view.

[0139] Please refer to Figure 16 ,in accordance with Figure 3 In step S113, a character line formation process is performed on the channel structure 120. The character line formation process may include at least one photolithography process, an etching process, and a deposition process well known in the art. In some embodiments, a character line 150 is formed to surround a portion of the vertical assembly 124 surrounded by the pad material 140. The character line 150 is disposed to cover the first oxide 130 and partially fill the channel R1. In some embodiments, the character line 150 extends along a second direction D2, which is substantially orthogonal to the first direction D1. In some embodiments, the width of the character line 150 is substantially 1F, where F is a minimum feature size. Furthermore, the distance from a center of the character line 150 to a center of an adjacent character line (not shown) located on the substrate 100 is substantially 2F. The fabrication technique of the character line 150 may include a PVD process, a CVD process, a sputtering process, or an electroplating process. In some embodiments, the character line 150 comprises aluminum, copper, tungsten, titanium, or titanium nitride (TiN). Furthermore, the character line 150 may be electrically coupled to the unit cell capacitor 110. In some embodiments, an upper surface of the character line 150 is coplanar with an upper surface of the pad material 140. Furthermore, a lower surface of the character line 150 is coplanar with a lower surface of the pad material 140 and an upper surface of the first oxide 130. Figure 16 In the section view, one side wall of the padding material 140 is covered by the character line 150 and is therefore not shown.

[0140] Figure 17 Examples of some embodiments of this disclosure Figure 16A plan view is provided. In some embodiments, a pad material 140 is inserted between the word line 150 and the channel structure 120. Furthermore, the word line 150 passes through the vertical component 124 of the channel structure 120. In some embodiments, the dense silicon oxide or silicon nitride of the pad material 140 prevents leakage current from the word line 150 to the channel structure 120 when a voltage is applied to the word line 150.

[0141] Figures 18A to 18C A schematic plan view illustrating a plurality of channel structures 120 coupled via character lines 150, according to some embodiments of this disclosure. Figures 18A to 18C The figure only shows the vertical component 124, the channel R1, and the character line 150 of the channel structure 120; other elements are omitted for clarity. In some embodiments, a plurality of channel structures 120 are disposed on the substrate 100, wherein each channel structure 120 has a channel R1 therein. Furthermore, the character lines 150 are configured to partially surround the sidewalls of the channel structures 120.

[0142] Please refer to Figure 18A It is similar to Figure 17 The character line 150 passes through each pair of vertical components 124 and extends along the second direction D2. In some embodiments, a pitch P1 exists between the channel structures 120, wherein the pitch P1 is equal to the distance from a center of one channel structure 120 to a center of an adjacent channel structure 120. In some embodiments, the pitch P1 is equal to 2F, where F is approximately the width of a character line to be formed subsequently.

[0143] Figure 18B Similar to Figure 18A The only difference is that the channel R1 extends along the second direction D2 instead of along the first direction D1. Specifically, the character line 150 is configured to be parallel to the channel R1. In some embodiments, such as Figure 18B The configuration can be adjusted Figure 3 The recess is formed in step S107. For example, when a recess forming process is performed to form the channel structure 120 in FIG10, in Figure 9 The channel material 120A can be cut at an orthogonal angle. In other embodiments, such as Figure 18B The configuration can also be adjusted. Figure 3 This is formed by step S113. For example, in... Figure 16 The character line 150 is formed along the first direction D1, replacing the second direction D2.

[0144] Please refer to Figure 18C It is similar to Figure 18A and Figure 18BIn some embodiments, the channel R1 may extend on the substrate 100 in any direction. For example, the channel R1 may be configured to extend along a third direction D3, which is substantially different from the first direction D1 and the second direction D2. In some embodiments, the third direction D3 forms a predetermined angle θ relative to the second direction D2, wherein the predetermined angle θ is less than 90 degrees. In some embodiments, in Figure 18C The configuration can be adjusted in Figure 3 It is formed by step S107 or step S113 in the process.

[0145] Please refer to Figure 19 ,in accordance with Figure 3 In step S115, a second deposition process is performed on the channel structure 120. In some embodiments, a second oxide 160 is formed to fill the channel R1. In particular, the second oxide 160 is deposited on a portion of the word line 150 located in the channel R1 and on the first oxide 130 located within the channel structure 120. After filling the channel R1, a chemical mechanical polishing (CMP) process is performed on the second oxide 160 to ensure that the upper surface of the second oxide 160 does not protrude from the upper surface of the vertical assembly 124. In some embodiments, the upper surface of the second oxide 160 is coplanar with the upper surface of the channel structure 120. The fabrication technique of the second oxide 160 may include an LPCVD process or a PECVD process. In some embodiments, the second oxide 160 is silicon oxide. In some embodiments, the second oxide 160 provides additional oxygen atoms to the channel structure 120 via multiple metal-oxygen (MO) bonds between the second oxide 120 and the second oxide 160.

[0146] Figure 20 Examples of some embodiments of this disclosure Figure 19 A plan view. In some embodiments, the second oxide 160 is inserted between the vertical components 124 of the channel structure 120. Furthermore, the second oxide 160 covers a portion of the padding material 140 located in the channel R1. At this time, a portion 150P of the character line 150 is sandwiched between the first oxide 130 and the second oxide 160. Moreover, this portion 150P is sandwiched between the vertical components 124 surrounded by the padding material 140.

[0147] Please refer to Figure 21 ,in accordance with Figure 3In step S117, a bit line formation process is performed on the channel structure 120. The bit line formation process may include at least one photolithography process, an etching process, and a deposition process well known in the art. In some embodiments, a bit line 170 is formed on the channel structure 120. Furthermore, the bit line 170 completely covers the second oxide 160 located within the channel R1. In some embodiments, the bit line 170 extends along a first direction D1. That is, the bit line 170 is configured to be parallel to the channel R1 and orthogonal to the word line 150. The fabrication technique of the bit line 170 may include a PVD process, a CVD process, a sputtering process, or an electroplating process. In some embodiments, the bit line 170 comprises various conductive materials, such as metals or polysilicon. Preferably, the bit line 170 is a metal alloy, such as tungsten silicide (WSi). Furthermore, the bit line 170 may be electrically coupled to the word line 150 and the unit cell capacitor 110. Bit line 170 can be used to transmit a signal to unit cell capacitor 110 so that data stored in unit cell capacitor 110 can be read, or the signal can be stored as data and written to unit cell capacitor 110. In this case, a first semiconductor structure 200 is typically formed.

[0148] Figure 22 Examples of some embodiments of this disclosure are shown below. Figure 21 Another cross-sectional view taken in the second direction D2. In some embodiments, the first portion 126 and the second portion 128 of the vertical component 124 of the channel structure 120 can be used as a source or drain terminal of a vertical transistor. That is, when the first portion 126 is used as a source terminal, the second portion 128 is used as a drain terminal, and so on. In some embodiments, the word line 150 has a gate portion 152 disposed on the pad material 140. The gate portion 152 can be used as a gate terminal of a transistor. In some embodiments, the first portion 126, the second portion 128, and the gate portion 152 can form a unit cell transistor 180, which is used to control the word line 150. Furthermore, the pad material between the gate portion 152 and the vertical component 124 can be used as a gate dielectric layer to separate the gate terminal of the unit cell transistor 180 from its underlying source and drain terminals. In addition, the gate dielectric layer can prevent leakage current from the gate terminal. In some embodiments, the unit cell transistor 180 is a VGT or a vertical pillar transistor (VPT).

[0149] Figure 23 Examples of some embodiments of this disclosure Figure 21A three-dimensional schematic diagram. In some embodiments, the cell capacitor 110 is located below the intersection of the word line 150 and the bit line 170. The cell transistor 180 acts as a switch for the cell capacitor 110. That is, the cell transistor 180 controls the charging and discharging of the cell capacitor 110. In some embodiments, a first portion 126 is electrically connected to the bit line 170, and a second portion 128 is electrically connected to the cell capacitor 110 via a horizontal component 122. Therefore, the word line 150, interposed between the first portion 126 and the second portion 128, is electrically coupled to the bit line 170 and the cell capacitor 110 via a channel structure 120. In some embodiments, a plurality of word lines 150 and a plurality of bit lines 170 orthogonal to the word lines 150 form a memory array. The memory array is generally formed with a 4F 2 A layout of dynamic random access memory (DRAM).

[0150] In some embodiments, a capacitor-last process can be performed based on an improvement to the fabrication method 200. Figure 24 A cross-sectional schematic diagram of a second semiconductor structure 300, illustrating some embodiments of the present disclosure, is shown. The second semiconductor structure 300 is similar to the first semiconductor structure 200, except that the bit line 170 is formed before the unit cell capacitor 110. At this time, the bit line 170 is formed on the substrate 100, and the unit cell capacitor 110 is located at the intersection of the word line 150 and the bit line 170.

[0151] In some embodiments, the first semiconductor structure 200 and the second semiconductor structure 300 may be encapsulated by an interlayer dielectric. In some embodiments, the interlayer dielectric does not need to be fully formed in one step. For example, the formation of the interlayer dielectric may include, but is not limited to, the following steps: First, after the unit cell capacitor 110 is formed, the interlayer dielectric may be deposited on a bit facet, which is coplanar with the upper surface of the unit cell capacitor 110. Next, after the channel structure 120 is formed, the interlayer dielectric may be deposited on a bit facet, which is coplanar with the first oxide 130. Following this, after the word line 150 is formed, the interlayer dielectric may be deposited on a bit facet, which is coplanar with the channel structure 120.

[0152] This disclosure provides a semiconductor structure having a channel structure. The channel structure, together with a word line, forms a VGT within the semiconductor structure. The semiconductor structure includes non-silicon-based materials, such as ZnO, IZO, ITZO, IGZO, and the like, which have higher band gaps than pure silicon. Typically, non-silicon-based materials are oxygen-rich to provide a large number of oxygen vacancies. These oxygen vacancies supply the required number of free carriers for electrical interconnection in a metal-oxide-semiconductor. However, multiple high-temperature processes can reduce the oxygen vacancies content and further affect the electronic properties of the metal-oxide-semiconductor.

[0153] Therefore, the channel structure in this disclosure is formed having a horizontal component and a pair of vertical components, with a channel separating the pair of vertical components. Silicon dioxide is deposited in the channel to contact the channel structure. When the channel structure undergoes the high-temperature process and loses its oxygen vacancies, the silicon dioxide can replenish the lost oxygen vacancies via the channel structure and the multiple metal-oxygen bonds formed between the additional oxygen atoms. Furthermore, by increasing the number of oxygen atoms, the thermal stability of the channel structure can be improved.

[0154] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0155] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the content of this disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this disclosure.

Claims

1. A semiconductor structure, comprising: One base; A single-cell capacitor is disposed on the substrate; A channel structure is disposed on the unit cell capacitor, wherein the channel structure includes a horizontal component and at least two separate vertical components extending from the horizontal component. A padding material is arranged around at least one vertical component; A single character line surrounds the at least two separate vertical component settings; and One element line is set on this channel structure.

2. The semiconductor structure of claim 1, wherein the channel structure comprises amorphous silicon, doped silicon, indium oxide, gallium oxide, zinc oxide, indium zinc oxide, indium tin oxide, indium tin zinc oxide, or indium gallium zinc oxide.

3. The semiconductor structure of claim 1, wherein the pad material comprises dense silicon oxide or silicon nitride.

4. The semiconductor structure of claim 1, wherein the channel structure is generally a U-shaped structure.

5. The semiconductor structure of claim 1, wherein the at least two separate vertical components extend along a first direction, and the word line extends along a second direction orthogonal to the first direction, wherein the bit line extends along the first direction.

6. The semiconductor structure of claim 1, wherein the pad material is inserted between the character line and the channel structure.

7. The semiconductor structure of claim 1, wherein the character line passes through the at least two separate vertical components of the channel structure.

8. The semiconductor structure of claim 1, wherein the word line and the bit line form a memory array, wherein the memory array has four square feature sizes (4F). 2 (A layout) 9. The semiconductor structure of claim 1, further comprising: A first oxide is disposed between the at least two separate vertical components; as well as A second oxide is disposed on the first oxide and between the at least two separate vertical components.

10. The semiconductor structure of claim 9, wherein the first oxide and the second oxide comprise silicon oxide.

11. The semiconductor structure of claim 9, wherein the pad material partially covers the first oxide and the second oxide partially covers the pad material.

12. The semiconductor structure of claim 9, wherein a portion of the character line is sandwiched between the first oxide and the second oxide, and between the at least two separate vertical components surrounded by the padding material.

13. The semiconductor structure of claim 9, wherein the second oxide is interposed between the at least two separate vertical components of the channel structure.

14. The semiconductor structure of claim 9, wherein the at least two separate vertical components include a first portion and a second portion disposed above and below the pad material, respectively.

15. The semiconductor structure of claim 14, wherein the first portion is electrically connected to the bit line, and the second portion is electrically connected to the cell capacitor via the horizontal component.

16. The semiconductor structure of claim 15, wherein the word line is inserted between the first portion and the second portion and is electrically coupled to the bit line and the cell capacitor via the channel structure.

17. A semiconductor structure comprising: One base; A single-element line is set on this substrate; A channel structure is provided on the bit line, wherein the channel structure includes a horizontal component and at least two separate vertical components extending from the horizontal component. A padding material is provided around the at least two separate vertical components; A single character line surrounds the at least two separate vertical component settings; as well as A single-cell capacitor is disposed on the channel structure.

18. A method for fabricating a semiconductor structure, comprising: Provide a base; A unit cell capacitor is formed on the substrate; A channel material is formed on the unit cell capacitor; The channel material is cut to form a channel structure, wherein the channel structure includes a horizontal component and at least two vertical components, the at least two vertical components being separated by a groove on the horizontal component; A liner material is formed on each sidewall of the at least two vertical components; A single line is formed to surround the at least two vertical components that are surrounded by the padding material, and to partially fill the channel; as well as A bit line is formed on this channel structure.

19. The method for fabricating a semiconductor structure as claimed in claim 18, wherein after the channel structure is formed, a first oxide is formed in the channel.

20. The method of fabricating a semiconductor structure as claimed in claim 19, wherein after the character line is formed, a second oxide is formed on the character line located in the channel and on the first oxide.

Images