Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate; forming a control gate material layer covering a floating gate material layer, an isolation structure, and the substrate; patterning the control gate material layer and the floating gate material layer to form a control gate located in a cell array region, a first transition region, and an adjacent select gate region, with the remaining floating gate material layer serving as a floating gate. The floating gate and the control gate constitute a gate structure; forming isolation sidewalls on the sidewalls of the gate structure, with the isolation sidewalls contacting the adjacent gate structure sidewalls located in the cell array region and the first transition region; forming a silicide barrier layer on the substrate, the isolation sidewalls, and the gate structure, with the silicide barrier layer exposing the cell array region, the first transition region, and the adjacent select gate region; and forming a metal silicide layer on the top of the gate structure and the substrate surface exposed by the silicide barrier layer. In the embodiments of the present invention, the gate structure and the isolation sidewalls in the first transition region serve as barriers between the metal layer and the substrate, thereby increasing the window for the metal silicide process.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the advancement of semiconductor manufacturing technology, flash memory (Flash Memory) has been developed for storage devices with relatively fast access speeds. Flash memory, also known as flash memory, is characterized by its ability to retain stored information for long periods of time without power. It also offers advantages such as high integration, fast access speeds, and ease of erasing, reading, and writing, making it a mainstream form of non-volatile memory (NVM).

[0003] According to the different structures, flash memory is divided into NOR Flash Memory and NAND Flash Memory. NOR flash memory uses memory random read technology. Each unit is connected in parallel, and the storage unit is uniformly addressed (with independent address lines), so any word can be accessed randomly. In the NOR flash array, when a word line is selected, the M NVM units originally connected to the word are all activated. On the other hand, the other NVM units connected to the unselected word lines are electrically separated from the M bit lines. Through the connected M bit lines, the current changes in the drains of the M selected NVM units can be detected. Because the bias and signal in a NOR flash array are directly applied to the electrodes of the selected NVM cells, generally speaking, NOR flash arrays have faster read access speeds and lower operating voltages than NAND flash arrays. In addition, because NOR flash arrays have dedicated address pins for addressing, they are easier to connect to other chips and support local execution.

[0004] A NOR flash array is currently proposed, which includes multiple NOR cells. The drains of the multiple NOR cells are paired to form multiple diffused sub-bit lines, which are separated by trench field isolation regions. These diffused sub-bit lines are twisted along the extension direction of the trench field isolation regions in a manner less than or equal to one column pitch, so that these diffused sub-bit lines can connect their sub-feature size diffusion lines (whose feature size is less than the minimum feature size F) to multiple full feature size diffusion regions, and multiple full feature size contacts can be set on the full feature size diffusion regions. In this NOR flash array, the area of ​​the NVM unit can be only 4F 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0005] However, the current metal silicide process for NOR flash arrays is quite difficult. Summary of the Invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to increasing the process window of the metal silicide process and reducing the process difficulty of the metal silicide process.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a plurality of discrete cell array regions for forming memory cells; the substrate further comprising a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent selection gate region along the column direction; a plurality of isolation structures extending along the column direction and arranged along the row direction, located in the substrate; a plurality of gate structures extending along the row direction and arranged along the column direction, located on the cell array region, the first transition region and the adjacent selection gate region, the gate structure comprising: floating gates located on portions of the substrate on both sides of the isolation structure, the floating gates located in each of the gate structures being arranged at intervals along the row direction; a control gate covering the floating gates along the row direction, as well as the substrate and the control gates between the floating gates. An isolation structure; a source region along the column direction, located in the substrate between adjacent floating gates in the cell array region, the source region also extending along the column direction and located in the substrate of the first transition region and the adjacent partial selection gate region; a first drain region, located in the substrate of the isolation structure of the cell array region, the first transition region and the adjacent partial selection gate region along the row direction; an isolation sidewall, located on the sidewall of the gate structure, in the cell array region and the first transition region, the isolation sidewall located on the sidewall of the adjacent gate structure contacts; a silicide blocking layer, located on the substrate, the isolation sidewall and the gate structure, the silicide blocking layer exposing the cell array region, the first transition region and the adjacent selection gate region; a metal silicide layer, located on the top of the gate structure and the top surface of the substrate exposed by the silicide blocking layer.

[0008] Accordingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a plurality of discrete cell array regions for forming memory cells; the substrate further comprising a selection gate region located between the cell array regions along the column direction, and a first transition region located between the cell array region and an adjacent selection gate region along the column direction, a plurality of isolation structures extending along the column direction and arranged along the row direction are formed in the substrate, a floating gate material layer is formed on the substrate, an opening along the column direction is also formed in the floating gate material layer of the cell array region, the opening also passes through the first transition region and an adjacent portion of the selection gate region along the column direction, an active region is formed in the substrate below the opening, a first drain region is formed in the substrate on the second side of the row direction along the isolation structure of the cell array region, the first transition region and the adjacent portion of the selection gate region; forming a structure covering the The floating gate material layer, the isolation structure, and the control gate material layer of the substrate are patterned to form a plurality of control gates extending in the row direction and arranged in the column direction on the cell array region, the first transition region, and the adjacent select gate region. The remaining floating gate material layer located at the bottom of the control gates is used as a floating gate. The floating gates and the control gates located on the floating gates are used to form a gate structure. An isolation spacer is formed on the sidewalls of the gate structure. The isolation spacer located on the sidewalls of the adjacent gate structure in the cell array region and the first transition region contacts the isolation spacer. A silicide barrier layer is formed on the substrate, the isolation spacer, and the gate structure. The silicide barrier layer exposes the cell array region, the first transition region, and the adjacent select gate region. A metal silicide layer is formed on the top of the gate structure and the top surface of the substrate exposed by the silicide barrier layer.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the control gate material layer and the floating gate material layer are patterned, and a control gate is formed on the cell array region, the first transition region and the adjacent selection gate region. The remaining floating gate material layer serves as a floating gate. Accordingly, the gate structure is also formed on the first transition region, and then an isolation sidewall is formed on the sidewall of the gate structure. The isolation sidewalls on the sidewalls of the adjacent gate structures located in the cell array region and the first transition region are in contact with each other, and the substrate of the first transition region is correspondingly covered by the gate structure and the isolation sidewall. In the process of forming a metal silicide layer, the gate structure and the isolation sidewall in the first transition region can serve as a barrier layer between the metal layer and the substrate in the metal silicide process, preventing the metal silicide layer from being formed in the first transition region. on the substrate, which is beneficial to preventing the source region and the first drain region from being connected by the metal silicide layer on the first transition region and causing a short circuit; moreover, in the process of forming the silicide blocking layer, there is no need to retain the silicide blocking film in the first transition region, and the photolithography and etching processes for forming the silicide blocking layer do not need to be aligned in the first transition region, which is beneficial to reducing the requirements for process accuracy and increasing the process window. In addition, in the embodiment of the present invention, the silicide blocking layer is avoided from being formed on part of the gate structure of the cell array region close to the first transition region in order to reserve process space, thereby increasing the number of available gate structures and reducing the area of ​​the entire cell array region; in summary, the embodiment of the present invention is beneficial to increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 10 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figures 11 to 23 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] As can be seen from the background technology, currently 4F 2 The metal silicide process for NOR flash arrays is quite difficult. The reasons for this difficulty are analyzed in conjunction with a method for forming a semiconductor structure.

[0014] Figures 1 to 10 The present invention is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 and Figure 2 , Figure 1 For top view, Figure 2 for Figure 1A partial cross-sectional view along the aa cut line provides a substrate 1, including a plurality of discrete cell array regions 1c for forming memory cells, and the substrate 1 also includes a plurality of cell array regions 1c along the column direction (eg Figure 1 The substrate 1 is formed with a plurality of lines extending in the column direction and extending in the row direction (as shown in the y direction) and a selection gate region 1s located between the cell array region 1c and the adjacent selection gate region 1s along the column direction. Figure 1 An isolation structure 2 is arranged (as shown in the x direction in the middle), a floating gate material layer 3 is formed on the substrate 1, and an opening 4 along the column direction is further formed in the floating gate material layer 3 between adjacent isolation structures 2 in the cell array area 1c. The opening 4 also penetrates the adjacent first transition area 1b and part of the selection gate area 1s along the column direction, and an active area 5 is formed in the substrate 1 below the opening 4. A first drain area 6 is formed in the substrate 1 on the second side along the row direction of the isolation structures 2 of the cell array area 1c, the first transition area 1b and the adjacent part of the selection gate area 1s.

[0016] refer to Figure 3 and Figure 4 , Figure 3 For top view, Figure 4 for Figure 3 A local cross-sectional view along the aa cut line shows a control gate material layer (not shown) covering the floating gate material layer 3, the isolation structure 2 and the substrate 1; the control gate material layer and the floating gate material layer 3 are patterned to form a plurality of control gates 7 extending in the row direction and arranged in the column direction on the cell array area 1c and the adjacent selection gate area 1s; the remaining floating gate material layer 3 located at the bottom of the control gate 7 is used as a floating gate 8; the floating gate 8 and the control gate 7 located on the floating gate 8 are used to constitute a gate structure 9.

[0017] refer to Figure 5 , isolation spacers 10 are formed on the sidewalls of the gate structure 9 , and the isolation spacers 10 on the sidewalls of adjacent gate structures 9 in the cell array region 1 c are in contact with each other.

[0018] refer to Figure 6 A silicide blocking film 11 is conformally covered on the substrate 1 , the isolation spacer 10 and the gate structure 9 .

[0019] refer to Figure 7 , remove the silicide blocking film 11 located in the selection gate area 1s and the cell array area 1c, and the remaining silicide blocking film 11 located in the first transition area 1b is used as the silicide blocking layer 12, and the silicide blocking layer 12 also extends to cover the isolation sidewall 10 located on the side wall of the gate structure 9 in the adjacent cell array area 1c, and part of the top of the gate structure 9.

[0020] refer to Figure 8A metal layer 13 is formed on the silicide blocking layer 12 and on the substrate 1 and the gate structure 9 where the silicide blocking layer 12 is exposed.

[0021] refer to Figure 9 , the metal layer 13 is heat-treated to convert the metal layer 13 and a portion of the thickness of the substrate 1 , as well as the metal layer 13 and a portion of the thickness of the control gate 9 into a metal silicide layer 14 .

[0022] refer to Figure 10 , remove the remaining metal layer 13.

[0023] In the above method, the silicide barrier layer 12 is located on the first transition region 1b. In the metal silicide process, the silicide barrier layer 12 is used to prevent the metal layer 13 from directly contacting the substrate 1 of the first transition region 1b, thereby preventing the formation of a metal silicide layer 14 on the substrate 1 of the first transition region 1b, which is correspondingly beneficial to preventing the source region 5 and the first drain region 6 of the first transition region 1b from being short-circuited by the metal silicide layer 14.

[0024] In the process of forming the silicide blocking layer 12, the removal of the silicide blocking film 11 located in the selection gate area 1s and the cell array area 1c includes photolithography and etching processes. In order to reserve sufficient process windows and size spaces for the photolithography and etching processes to ensure the protective effect of the silicide blocking layer 12 on the first transition area 1b, the silicide blocking layer 12 also extends to cover the isolation sidewalls 10 located on the side walls of the gate structure 9 in the adjacent cell array area 1c, and part of the top of the gate structure 9.

[0025] However, this results in the metal silicide layer 14 not being formed on the gate structure 9 covered by the silicide barrier layer 12. The gate structure 9 covered by the silicide barrier layer 12 serves as a dummy gate structure, which reduces the number of gate structures 9 available in the cell array region 1c and increases the area of ​​the ineffective region, thereby reducing the unit area utilization of the cell array region 1c. In addition, the process of forming the silicide barrier layer 12 includes a photolithography process, which includes an overlay alignment process. This places high demands on the accuracy of the overlay shift, which in turn increases the difficulty of the metal silicide process and reduces the process window of the metal silicide process.

[0026] In order to solve the technical problem, in the method for forming a semiconductor structure provided by an embodiment of the present invention, the control gate material layer and the floating gate material layer are patterned, and a control gate is formed on the cell array area, the first transition area and the adjacent selection gate area. The remaining floating gate material layer serves as a floating gate. Accordingly, the gate structure is also formed on the first transition area, and then an isolation sidewall is formed on the sidewall of the gate structure. The isolation sidewalls on the sidewalls of the adjacent gate structures located in the cell array area and the first transition area are in contact with each other, and the substrate of the first transition area is correspondingly covered by the gate structure and the isolation sidewall. In the process of forming the metal silicide layer, the gate structure and the isolation sidewall of the first transition area can serve as a barrier layer between the metal layer and the substrate in the metal silicide process to prevent the metal silicide layer from being formed on the On the substrate of the first transition region, it is beneficial to prevent the source region and the first drain region from being connected by the metal silicide layer in the first transition region and causing a short circuit; moreover, in the process of forming the silicide blocking layer, there is no need to retain the silicide blocking film of the first transition region, and the lithography and etching processes for forming the silicide blocking layer do not need to be aligned in the first transition region, which is beneficial to reducing the requirements for process accuracy and increasing the process window. In addition, in the embodiment of the present invention, the silicide blocking layer is avoided to be formed on the partial gate structure of the cell array region close to the first transition region in order to reserve process space, which is beneficial to increase the number of available gate structures and reduce the area of ​​the overall cell array region; in summary, the embodiment of the present invention is beneficial to increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process.

[0027] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figures 11 to 23 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0029] refer to Figure 11 and Figure 12 , Figure 11 For top view, Figure 12 for Figure 11 A partial cross-sectional view along the AA cut line provides a substrate 100, including a plurality of discrete cell array regions 100C for forming memory cells, and the substrate 100 also includes a plurality of cell array regions 100C along the column direction (eg Figure 11 The substrate 100 is provided with a selection gate region 100S located between the cell array region 100C (shown in the Y direction), and a first transition region 100B located between the cell array region 100C and the selection gate region 100S on the adjacent side along the column direction. A plurality of strips extending along the column direction and along the row direction (shown in the Y direction) are formed in the substrate 100. Figure 11The isolation structures 110 are arranged in the cell array area 100C (as shown in the X direction), a floating gate material layer 120 is formed on the substrate 100, and an opening 130 is further formed in the floating gate material layer 120 between adjacent isolation structures 110 in the cell array area 100C along the column direction. The opening 130 also penetrates the first transition region 100B and the adjacent portion of the selection gate region 100S along the column direction. An active region 140 is formed in the substrate 100 below the opening 130, and a first drain region 150 is formed in the substrate 100 on the second side along the row direction of the isolation structures 110 in the cell array area 100C, the first transition region 100B, and the adjacent portion of the selection gate region 100S.

[0030] The substrate 100 provides a process platform for forming a NOR Flash Memory. Specifically, in this embodiment, the substrate 100 is used to form a 4F 2 In this NOR flash array, the area of ​​the NVM cell can be as small as 4F. 2 (where F is the minimum feature size feature), which is beneficial to improving the storage unit area density.

[0031] The cell array region 100C is used to form memory cells. The select gate region 100S is located between the cell array regions 100C along the column direction. Logic devices (Logic Devices) are subsequently formed on the select gate region 100S. Specifically, select gates (SG) are subsequently formed on the select gate region 100S.

[0032] The active area (AA) of the selection gate region 100S on the adjacent side of the cell array region 100C is offset toward the first side along the row direction relative to the active area of ​​the cell array region 100C, and the isolation structure 110 of the selection gate region 100S is also offset toward the first side along the row direction relative to the isolation structure 110 of the cell array region 100C. The first transition region 100B serves as a boundary region (Boundary Area) and is located between the cell array region 100C and the adjacent selection gate region 100S, and is used to connect the cell array region 100C and the adjacent selection gate region 100S.

[0033] In this embodiment, the substrate 100 further includes a second transition region (not shown) located along the column direction between the cell array region 100C and the adjacent selection gate region 100S on the other side. The first transition region 100B and the adjacent selection gate region 100S constitute a first selection gate unit (not marked); the second transition region and the adjacent selection gate region 100S constitute a second selection gate unit (not shown), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region 100C.

[0034] The active area of ​​the selection gate region 100S on the other side adjacent to the cell array region 100C is offset toward the second side along the row direction relative to the active area of ​​the cell array region 100C, and the isolation structure 110 of the selection gate region 100S is also offset toward the second side along the row direction relative to the isolation structure 110 of the cell array region 100C. The second transition region serves as a boundary region, located between the cell array region 100C and the selection gate region 100S on the other side, and is used to connect the cell array region 100C and the selection gate region 100S on the other side.

[0035] In this embodiment, the base 100 includes a substrate. Specifically, the substrate is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0036] The isolation structure 110 is used to define the active area (AA) and isolation area of ​​the substrate 100. The substrate 100 isolated by the isolation structure 110 is used as the active area, and the remaining area is used as the isolation area. The isolation structure 110 is used to isolate adjacent device units along the row.

[0037] In this embodiment, the isolation structure 110 is a shallow trench isolation (STI) structure, and the material of the isolation structure 110 is silicon oxide. In other embodiments, the material of the isolation structure may also be other dielectric materials such as silicon nitride or silicon oxide.

[0038] In this embodiment, the isolation structure 110 includes a main extension portion (not labeled) located in the cell array region 100C and a first offset extension portion (not labeled) located in the adjacent side selection gate region 100S. The first offset extension portion is offset toward the first side along the row direction relative to the main extension portion. The isolation structure also includes a first transition extension portion (not labeled) connected to the first offset extension portion and the main extension portion and located in the first transition region 100B.

[0039] In this embodiment, the isolation structure 110 further includes a second offset extension portion (not shown) located in the selection gate region 100S on the other side adjacent to the cell array region 100C, and the second offset extension portion is offset toward the second side along the row direction relative to the main extension portion. The isolation structure further includes a second transition extension portion (not shown) connected to the second offset extension portion and the main extension portion and located in the second transition region.

[0040] In this embodiment, the isolation structure 110 further includes: a first extension portion (not shown) arranged along the row direction and spaced apart from the first offset extension portion, the first extension portion also extending along the column direction to the adjacent first transition region 100B and having a gap between it and the first transition extension portion; a second extension portion (not shown) arranged along the row direction and spaced apart from the second offset extension portion, the second extension portion also extending along the column direction to the adjacent second transition region and having a gap between it and the second transition extension portion.

[0041] The floating gate material layer 120 is used to form a floating gate.

[0042] In this embodiment, the floating gate material layer 120 is made of polysilicon.

[0043] In this embodiment, a tunneling oxide layer 155 is formed between the floating gate material layer 120 and the top surface of the substrate 100, and on the exposed top surface of the substrate 100. The tunneling oxide (TOX) layer 155 is used to provide a tunneling channel for electrons from the substrate 100 to the floating gate. The tunneling oxide layer 155 is also used to isolate the floating gate from the substrate 100. In this embodiment, the material of the tunneling oxide layer 155 is silicon oxide.

[0044] In this embodiment, for the convenience of illustration and description, only the tunnel oxide layer 155 is illustrated in the cross-sectional view.

[0045] The opening 130 is used to define the shape and position of the source region 140 .

[0046] In this embodiment, the opening 130 penetrates the floating gate material layer 120 between adjacent main extensions.

[0047] In this embodiment, the opening 130 also penetrates the adjacent second transition region and part of the selection gate region 100S along the column direction, and the opening 130 also extends along the column direction to part of the selection gate region 100S adjacent to the first transition region 100B, and part of the selection gate region 100S adjacent to the second transition region, so that the source region 140 in the substrate 100 located below the opening 130 can extend to the selection gate region 100S to be connected to the subsequent selection gate.

[0048] In this embodiment, the opening 400 extending along the column direction to the portion of the selection gate region S adjacent to the first transition region 100B is located between the first offset extension portion and the first extension portion adjacent to the first side along the row direction; the opening 130 also extending along the column direction to the portion of the selection gate region 100S adjacent to the second transition region is located between the second offset extension portion and the second extension portion adjacent to the second side along the row direction.

[0049] In this embodiment, the tunnel oxide layer 155 is exposed at the bottom of the opening 130 . The tunnel oxide layer 155 can protect the substrate 100 and reduce the probability of damage to the substrate 100 during semiconductor manufacturing processes.

[0050] The source region 140 is used as a common source region and is located in the substrate 100 below the opening 130 . The source region 140 extends along the column direction.

[0051] First drain region 150 is used to form a first drain sub-bitline. First drain region 150 is located in substrate 100 along the second side of the row direction, along the main extension, first transition extension, and a portion of the first offset extension. First drain region 150 extends along the sidewalls of the main extension and first transition extension along the second side of the row direction. First drain region 150 also extends into a portion of substrate 100 along the sidewall of the adjacent first offset extension along the second side of the row direction. This allows first drain region 150 to extend into a portion of select gate region 100S adjacent to first transition region 100B, thereby connecting the memory cell corresponding to the first drain sub-bitline to the select gate.

[0052] In this embodiment, the opening 130 also penetrates the adjacent second transition region and part of the selection gate region 100S along the column direction, and a second drain region 160 is also formed in the substrate 100 on the first side along the row direction of the isolation structure 110 of the cell array region 100C, the second transition region and the adjacent part of the selection gate region 100S.

[0053] In this embodiment, the second drain region 160 is used to form a second drain sub-bit line. The second drain region 160 extends along the sidewalls of the main extension portion and the second transition extension portion along the first side in the row direction. The second drain region 160 also extends into a portion of the substrate 100 along the sidewall of the adjacent second offset extension portion along the first side in the row direction, thereby allowing the second drain region 160 to extend into a portion of the select gate region 100S adjacent to the second transition region, thereby connecting the storage cell corresponding to the second drain sub-bit line to the select gate.

[0054] In this embodiment, the doping depth of the first drain region 150 , the second drain region 160 and the source region 140 in the substrate 100 is less than the depth of the isolation structure 110 , so that each of the first drain region 150 , the second drain region 160 and the source region 140 can be isolated from each other by the isolation structure 110 .

[0055] When forming an NMOS device, the doping ions in the first drain region 150 , the second drain region 160 and the source region 140 are N-type ions; when forming a PMOS device, the doping ions in the first drain region 150 , the second drain region 160 and the source region 140 are P-type ions.

[0056] refer to Figure 13 and Figure 14, Figure 13 For top view, Figure 14 for Figure 13 A partial cross-sectional view along the AA cut line shows a control gate material layer 165 covering the floating gate material layer 120, the isolation structure 110 and the substrate 100. The control gate material layer 165 is used for forming a control gate subsequently.

[0057] In this embodiment, the control gate material layer 165 is made of polysilicon. In this embodiment, the process of forming the control gate material layer includes a deposition process (eg, a chemical vapor deposition process).

[0058] In this embodiment, the formation method further includes: before forming the control gate material layer 165, forming a gate dielectric material layer 185 on the top surface and sidewalls of the isolation structure 110, the substrate 100, and the floating gate material layer 120. The control gate material layer 165 is correspondingly formed on the gate dielectric material layer 185.

[0059] The gate dielectric material layer 185 is used to form an inter-gate dielectric layer.

[0060] The gate dielectric material layer 185 is made of a dielectric material. In this embodiment, the gate dielectric material layer 185 has a stacked structure. As an example, the gate dielectric material layer 185 has an ONO (Oxide-Nitride-Oxide) structure, and includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked sequentially from bottom to top.

[0061] In other embodiments, according to actual process requirements, the gate dielectric material layer may be made of other suitable materials, and the gate dielectric material layer may also be a single-layer structure.

[0062] refer to Figure 15 and Figure 16 , Figure 15 For top view, Figure 16 for Figure 15 In the local cross-sectional view along the AA cut line, the control gate material layer 165 and the floating gate material layer 120 are patterned, and a plurality of control gates 170 extending in the row direction and arranged in the column direction are formed on the cell array area 100C, the first transition area 100B and the adjacent selection gate area 100S. The remaining floating gate material layer 120 located at the bottom of the control gate 170 is used as a floating gate 180. The floating gate 180 and the control gate 170 located on the floating gate 180 are used to form a gate structure 200.

[0063] When the NOR flash memory is operating, programming is achieved by changing the electron injection into the floating gate or erasing from the floating gate through the control gate 170 .

[0064] When the NOR flash memory is working, the floating gate 180 can capture and store electrons, and after power failure, the electrons stored in the floating gate 180 will not be lost. The amount of charge stored in the floating gate 180 can change the on-state voltage of the field-effect transistor, and different on-state voltages can represent different states, thereby realizing information storage.

[0065] In this embodiment, the control gate 170 is also formed on the first transition region 100B. Accordingly, the gate structure 200 is also formed on the first transition region 100B. Then, an isolation sidewall is formed on the sidewall of the gate structure 200. In the cell array region 100C and the first transition region 100B, the isolation sidewalls located on the adjacent sidewalls of the gate structure 200 are in contact with each other. Accordingly, the substrate 100 of the first transition region 100B is covered by the gate structure 200 and the isolation sidewall. The gate structure 200 and the isolation sidewall of the first transition region 100B can serve as a barrier layer between the metal layer and the substrate 100 in the metal silicide process, thereby preventing the metal silicide layer from being formed on the substrate 100 of the first transition region 100B, which is beneficial to preventing the source region 140 and the first drain region 150 from being connected by the metal silicide layer in the first transition region 100B and causing a short circuit.

[0066] In this embodiment, the control gate 170 is also located on the second transition region and the adjacent select gate region 100S. Accordingly, in the subsequent step of forming the isolation spacer, the isolation spacer located on the sidewalls of the adjacent gate structure 200 in the second transition region contacts each other. During the metal silicide process, the gate structure 200 and the isolation spacer located in the second transition region can serve as a barrier layer between the metal layer and the substrate 100 in the second transition region, thereby preventing the formation of a metal silicide layer on the substrate 100 in the second transition region. This also helps prevent the source region 140 and the second drain region 160 from being connected by the metal silicide in the second transition region, thereby preventing a short circuit.

[0067] As an example, the spacing between adjacent control gates 170 located in the first transition region 100B and the second transition region is the same as the spacing between adjacent control gates 170 located on the cell array region 100C. Moreover, the size of the control gates 170 located in the first transition region 100B and the second transition region is the same as the size of the control gates 170 located on the cell array region 100C, thereby making the structures of the first transition region 100B and the second transition region consistent with the cell array region 100C, which is conducive to improving process consistency.

[0068] In this embodiment, the step of patterning the control gate material layer 165 and the floating gate material layer 120 includes: forming a plurality of mask layers (not shown) extending in the row direction and arranged at intervals in the column direction on the control gate material layer 165 in the cell array area 100C, the first transition area 100B and the adjacent selection gate area 100S; and patterning the control gate material layer 165 and the floating gate material layer 120 using the mask layers as masks.

[0069] In this embodiment, the mask layer is also formed on the first transition region 100B and the second transition region, so that after the control gate material layer 165 and the floating gate material layer 120 are patterned using the mask layer as a mask, the control gate 170 formed can be located on the first transition region 100B and the second transition region.

[0070] In this embodiment, the mask layer is made of photoresist. Forming the mask layer includes exposing the photoresist using a mask. Therefore, in this embodiment, by modifying the pattern of the mask, the mask layer formed through the photolithography process, such as exposure and development, can be formed on the first transition region 100B. Accordingly, the control gate 170 is also formed on the first transition region 100B and the second transition region. This requires minimal changes to the existing process flow, allowing the previous process flow and production process to continue normally, avoiding the costs and burdens associated with process flow changes.

[0071] In this embodiment, an anisotropic dry etching process is used to pattern the control gate material layer 165 and the floating gate material layer 120 using the mask layer as a mask. The anisotropic dry etching process has anisotropic etching characteristics, which can achieve high profile controllability and pattern transfer accuracy, and accordingly helps to ensure that the morphology and size of the control gate 170 and the floating gate 180 meet process requirements.

[0072] In this embodiment, after patterning the control gate material layer 165 and the floating gate material layer 120, the floating gate 180 has an island structure. In this embodiment, during the step of patterning the control gate material layer 165 and the floating gate material layer 120, the gate dielectric material layer 185 is also patterned. The remaining gate dielectric material layer 185 is used as an inter-gate dielectric (IPD) layer 190. The inter-gate dielectric layer 190 also has a stacked structure. Specifically, the inter-gate dielectric layer 190 also has an ONO structure.

[0073] The inter-gate dielectric layer 190 is used to isolate the control gate 170 from the floating gate 180 . The inter-gate dielectric layer 190 is also used to isolate the control gate 170 from the substrate 100 .

[0074] Therefore, the gate structure 200 further includes the inter-gate dielectric layer 190 .

[0075] refer to Figure 17 Isolation spacers 210 are formed on the sidewalls of the gate structure 200 . In the cell array region 100C and the first transition region 100B, the isolation spacers 210 on the sidewalls of adjacent gate structures 200 are in contact with each other.

[0076] The isolation sidewall 210 is used to protect the sidewall of the gate structure 200. In the cell array area 100C and the first transition area 100B, the isolation sidewalls 210 located on the sidewalls of adjacent gate structures 200 are in contact with each other, so that the isolation sidewalls 210 fill the space between the adjacent gate structures 200 in the cell array area 100C and the first transition area 100B, thereby achieving electrical isolation between adjacent gate structures 200. Moreover, the substrate 100 located in the first transition area 100B is covered by the gate structure 200 and the isolation sidewall 210, so as not to be exposed to the subsequent metal silicide process, thereby avoiding the surface of the substrate 100 in the first transition area 100B from contacting the subsequent metal layer, thereby preventing the metal silicide layer from being formed on the top surface of the substrate 100 in the first transition area 100B.

[0077] In this embodiment, in the step of forming the isolation sidewalls 210, in the second transition region, the isolation sidewalls 210 located on the sidewalls of adjacent gate structures 200 are in contact with each other, so that the isolation sidewalls 210 also fill the space between the adjacent gate structures 200 in the second transition region. The substrate 100 located in the second transition region is covered by the gate structure 200 and the isolation sidewalls 210 and will not be exposed to the subsequent metal silicide process, thereby avoiding contact between the surface of the substrate 100 in the second transition region and the metal layer, thereby preventing the metal silicide layer from being formed on the top surface of the substrate 100 in the second transition region.

[0078] The isolation spacer 210 is made of a dielectric material. The material of the isolation spacer 210 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. The isolation spacer 210 can have a single-layer structure or a stacked-layer structure. In this embodiment, the isolation spacer 210 is a single-layer structure made of silicon nitride.

[0079] In this embodiment, the isolation spacer 210 is also formed on the top of the gate structure 200, and on the top surfaces of the substrate 100 and the isolation structure 110. In this embodiment, a furnace process (i.e., a high-temperature diffusion process) is used to form the isolation spacer 210. In other embodiments, a chemical vapor deposition process (e.g., a plasma-enhanced chemical vapor deposition process) may also be used to form the isolation spacer.

[0080] In this embodiment, during the process of forming the isolation spacer 210, the thickness of the isolation spacer 210 located on the sidewall of the gate structure 200 is greater than or equal to 0.5 times the spacing between adjacent gate structures 200 in the cell array region 100C. Thus, during the process of depositing the isolation spacer 210 material, as the thickness of the deposited material located on the sidewall of the gate structure 200 gradually increases, the isolation spacer 210 material located on the sidewall of the adjacent gate structure 200 in the cell array region 100C, the first transition region 100B, and the second transition region gradually contacts, thereby filling the space between the adjacent gate structures 200 in the cell array region 100, the first transition region 100B, and the second transition region.

[0081] It should be noted that, in this embodiment, after forming the gate structure 200 and before forming the isolation sidewall 210, the method for forming the semiconductor structure further includes: conformally covering the top surface and sidewalls of the gate structure 200, the substrate 100 and the isolation structure 110 with a liner layer 220.

[0082] The liner layer 220 is used to protect the gate structure 200 and improve the adhesion between the isolation spacer 210 and the gate structure 200, thereby preventing the isolation spacer 210 from directly contacting the gate structure 200 and causing large stress defects.

[0083] Therefore, in the step of forming the isolation spacer 210, the isolation spacer 210 conformally covers the liner layer 220. In this embodiment, the material of the liner layer 220 is silicon oxide.

[0084] refer to Figures 18 to 19 A silicide blocking layer (not shown) is formed on the substrate 100 , the isolation spacer 210 and the gate structure 200 , and the silicide blocking layer exposes the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S.

[0085] The substrate 100 generally includes other types of device regions, such as a peripheral device region (not shown). The silicide blocking layer (SAB) is located in a region where a metal silicide layer does not need to be formed, and is used to block the growth of metal silicide.

[0086] In this embodiment, the substrate 100 of the first transition region 100B is covered by the gate structure 200 and the isolation spacer 210. The gate structure 200 and the isolation spacer 210 of the first transition region 100B can serve as a barrier layer between the metal layer and the substrate 100 in the metal silicide process, thereby preventing the metal silicide layer from being formed on the substrate 100 of the first transition region 100B. In this embodiment, there is no need to retain the silicide barrier film of the first transition region 100B. Accordingly, the photolithography and etching processes for forming the silicide barrier layer do not need to be aligned in the first transition region 100B, which helps to reduce the requirements for process accuracy and increase the process window. In addition, in this embodiment, there is no need to reserve process space, and the silicide barrier layer is formed on the portion of the gate structure 200 in the cell array region 100C near the first transition region 100B, which helps to increase the number of available gate structures 200 and reduce the area of ​​the entire cell array region 100C.

[0087] In this embodiment, the substrate 100 of the second transition region is covered by the gate structure 200 and the isolation sidewall 210. The gate structure 200 and the isolation sidewall 210 of the second transition region can serve as a barrier layer between the metal layer and the substrate 100 in the subsequent metal silicide process to prevent the metal layer from directly contacting the substrate 100. Therefore, the silicide barrier layer also exposes the second transition region and the adjacent selection gate region 100S. The process of forming the silicide barrier layer in this embodiment does not need to be aligned in the second transition region, which is beneficial to reducing the requirements for process accuracy, increasing the process window, and increasing the number of available gate structures 200 and reducing the area of ​​the overall unit array region 100C.

[0088] In summary, the embodiments of the present invention are beneficial for increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process.

[0089] The silicide barrier layer is made of a dielectric material, ensuring that it can isolate the metal layer from the silicon during the metal silicide process. The silicide barrier layer may be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the silicide barrier layer is made of silicon oxide.

[0090] The specific steps of forming the silicide barrier layer in this embodiment are described in detail below with reference to the accompanying drawings.

[0091] like Figure 18 As shown, a silicide blocking film 230 is conformally covered on the substrate 100, the isolation spacer 210 and the gate structure 200. The silicide blocking film 230 is used to form a silicide blocking layer.

[0092] In this embodiment, a deposition process is used to form the silicide blocking film 230. The deposition process includes a chemical vapor deposition process or an atomic layer deposition process.

[0093] In this embodiment, since the isolation sidewall 210 is not only located on the sidewall of the gate structure 200, but also located on the top of the gate structure 200, and on the top surface of the substrate 100 and the isolation structure 110, in the step of forming the silicide blocking film 230, the silicide blocking film 230 conformally covers the isolation sidewall 210.

[0094] like Figure 19 As shown, the silicide blocking film 230 located on the cell array region 100C, the first transition region 100B and the adjacent select gate region 100S is removed, and the remaining silicide blocking film 230 is used as a silicide blocking layer (not shown).

[0095] In this embodiment, the silicide blocking film 230 located on the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S is removed. Accordingly, alignment is not required in the first transition region 100B, which is beneficial to reducing the requirements for process accuracy and increasing the process window.

[0096] In this embodiment, the silicide blocking film 230 located on the second transition region and the adjacent selection gate region 100S is also removed, and accordingly, there is no need to perform alignment in the second transition region, which is beneficial to reducing the requirements for process accuracy, increasing the process window, and increasing the number of available gate structures 200 and reducing the area of ​​the overall unit array region 100C.

[0097] In this embodiment, the step of removing the silicide blocking film 230 located on the cell array region 100C, the first transition region 100B, and the adjacent select gate region 100S includes: forming a pattern layer (not shown) on the silicide blocking film 230, the pattern layer having a pattern opening exposing the silicide blocking film 230 on the cell array region 100C, the first transition region 100B, and the adjacent select gate region 100S; and using the pattern layer as a mask, removing the silicide blocking film 230 exposed by the pattern opening to form the silicide blocking layer.

[0098] The graphic opening also exposes the silicide blocking film 230 on the second transition region and the adjacent selection gate region 100S, so as to facilitate the removal of the silicide blocking film 230 of the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S, and the second transition region and the adjacent selection gate region 100S in the same step.

[0099] In this embodiment, the material of the pattern layer includes photoresist. The process of forming the pattern layer includes photolithography processes such as exposure and development. The photolithography process does not require alignment in the first transition region 100B, thereby reducing the precision requirements of the photolithography process and reducing the process difficulty.

[0100] The process of removing the silicide blocking film on the cell array region 100C, the first transition region 100B and the adjacent select gate region 100S includes: one or both of a dry etching process and a wet etching process.

[0101] It should be noted that, in this embodiment, the method for forming the semiconductor structure further includes: in the step of removing the silicide blocking film 230 in the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S, and the second transition region and the adjacent selection gate region 100S, removing the isolation sidewalls on the top surface of the gate structure 200 and the isolation structure 110 located in the cell array region 100C and the first transition region 100B, and removing the isolation sidewalls on the top surface of the gate structure 200 located adjacent to the selection gate region 100S, the substrate 100 and the isolation structure 110. The isolation sidewall 210 on the top surface of the structure 110 exposes the gate structure 200 of the cell array region 100C and the first transition region 100B and the top surface of the isolation structure 110, as well as the top of the gate structure 200 of the adjacent selection gate region 100S, the substrate 100 and the top surface of the isolation structure 110, so that in the subsequent metal silicide process, the metal layer can contact the gate structure 200 of the cell array region 100C and the first transition region 100B, as well as the gate structure 200 and the substrate 100 of the adjacent selection gate region 100S.

[0102] Similarly, in this embodiment, the isolation sidewalls on the top surfaces of the gate structure 200 and the isolation structure 110 located in the second transition region, as well as the isolation sidewalls 210 located on the top of the gate structure 200, the substrate 100 and the top surface of the isolation structure 110 located in the adjacent selection gate region 100S are also removed, thereby exposing the top surface of the gate structure 200 in the second transition region, the top of the gate structure 200 in the adjacent selection gate region 100S and the top surface of the substrate 100, so that the metal layer in the subsequent metal silicide process can contact the gate structure 200 in the second transition region, the gate structure 200 in the adjacent selection gate region 100S and the substrate 100.

[0103] It should also be noted that, in the present embodiment, a liner layer 220 is formed between the isolation sidewall 210 and the substrate 100, between the isolation sidewall 210 and the isolation structure 110, and between the isolation sidewall 210 and the gate structure 200. Therefore, the liner layer 220 on the top surface of the gate structure 200 and the isolation sidewall 210 in the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S, and the second transition region and the adjacent selection gate region 100S, as well as the liner layer 220 on the top surface of the substrate 100 of the selection gate region 100S are also removed.

[0104] In the step of removing the liner layer 220 on the top surface of the substrate 100 of the selection gate region 100S, the tunneling oxide layer 155 on the top surface of the substrate 100 of the selection gate region 100S is also removed, thereby exposing the top surface of the substrate 100 of the selection gate region 100S, thereby enabling the metal layer in the subsequent metal silicide process to directly contact the top surface of the substrate 100 of the selection gate region 100S.

[0105] refer to Figures 20 to 22 A metal silicide layer 300 is formed on the top of the gate structure 200 and the top surface of the substrate 100 where the silicide blocking layer is exposed.

[0106] As can be seen from the foregoing, the substrate 100 of the first transition region 100B and the second transition region is covered by the gate structure 200 and the isolation sidewall 210. The gate structure 200 and the isolation sidewall 210 of the first transition region 100B and the second transition region serve as a barrier layer between the metal layer and the substrate 100 in the metal silicide process, thereby preventing the metal silicide layer from being formed on the substrate 100 of the first transition region 100B and the second transition region. The photolithography and etching processes for forming the silicide barrier layer do not need to be aligned in the first transition region 100B and the second transition region, which is beneficial to reducing the requirements for process accuracy and increasing the process window. This embodiment is beneficial to increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process.

[0107] Furthermore, this embodiment requires minimal changes to existing processes, and can continue the previous process flow and procedures normally, thus avoiding the costs and burdens associated with process flow changes.

[0108] The metal silicide layer 300 is located on the top of the gate structure 200 exposed by the silicide blocking layer. After a gate plug in contact with the gate structure 200 is subsequently formed, the metal silicide layer 300 is used to improve the adhesion between the gate structure 200 and the gate plug, and is also beneficial to reducing the contact resistance between the gate structure 200 and the gate plug.

[0109] The metal silicide layer 300 is also located on the top surface of the substrate 100 exposed by the silicide barrier layer. In this embodiment, the silicide blocking layer also exposes the substrate 100 of the selection gate region 100S. The substrate 100 of the selection gate region 100S usually also includes a source region and a drain region corresponding to the selection gate region 100S. The metal silicide layer 300 is correspondingly formed on the top surfaces of the source region and the drain region of the selection gate region 100S. Therefore, after a source plug in contact with the source region of the selection gate region 100S and a drain plug in contact with the drain region of the selection gate region 100S are subsequently formed, the metal silicide layer 300 is beneficial for improving the adhesion between the source plug and the source region of the selection gate region 100S, and the adhesion between the drain plug and the drain region of the selection gate region 100S. It is also beneficial for reducing the contact resistance between the source plug and the source region of the selection gate region 100S, and between the drain plug and the drain region of the selection gate region 100S, thereby correspondingly improving the performance of the semiconductor structure.

[0110] The material of the metal silicide layer 300 includes TiSi, NiSi, CoSi, NiPtSi, etc. In this embodiment, the material of the metal silicide layer 300 is NiPtSi.

[0111] In this embodiment, the steps of forming the metal silicide layer 300 include:

[0112] like Figure 20 As shown, a metal layer 240 is formed on the silicide barrier layer, the top and sidewall of the isolation spacer 210 exposed by the silicide barrier layer, the top of the gate structure 200 and the substrate 100 .

[0113] The material of the metal layer 240 includes Ti, Ni, Co or NiPt. In this embodiment, the material of the metal layer 240 is NiPt.

[0114] In this embodiment, the metal layer 240 is formed by a physical vapor deposition (PVD) process.

[0115] like Figure 21 As shown, the metal layer 240 is heat-treated to convert the metal layer 240 and a portion of the gate structure 200, as well as the metal layer 240 and a portion of the substrate 100, into a metal silicide layer 300. In this embodiment, the heat treatment is the first heat treatment.

[0116] In this embodiment, the first heat treatment includes: performing an annealing process on the metal layer 240. In this embodiment, the annealing process includes a dynamic surface annealing (DSA) process, a rapid thermal annealing process, or a laser annealing process.

[0117] like Figure 22As shown, the remaining metal layer 240 is removed.

[0118] In this embodiment, since the metal layer 240 does not react with the isolation sidewall 210 or the isolation structure 110, the remaining unreacted metal layer 240 on the isolation sidewall 210 or the isolation structure 110 can be selectively removed after the first heat treatment.

[0119] Specifically, in this embodiment, a wet etching process is used to remove the remaining metal layer 240 .

[0120] In this embodiment, after removing the remaining metal layer 240, the step of forming the metal silicide layer 300 may further include: performing a second heat treatment on the metal silicide layer 300 to further reduce the resistance of the metal silicide layer 300. The second heat treatment process includes annealing.

[0121] Combined with reference Figure 23 After forming the metal silicide layer 300 , the method for forming the semiconductor structure further includes: forming a capping dielectric layer 250 on the metal silicide layer 300 and the silicide barrier layer.

[0122] The covering dielectric layer 250 is used to cover the metal silicide layer 300 to prevent the metal silicide layer 300 from being oxidized or causing metal contamination when exposed to the air. The covering dielectric layer 250 can also be used as an etching stop layer in the subsequent contact hole etching process to define the stop position of the contact hole etching process, which is correspondingly beneficial to prevent the contact hole etching process from causing over-etching of the substrate 100 or the gate structure 200.

[0123] The covering dielectric layer 250 is made of dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0124] Accordingly, the present invention also provides a semiconductor structure. Figure 23 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0125] The semiconductor structure includes a substrate 100, the substrate 100 includes a plurality of discrete cell array regions 100C for forming memory cells, and the substrate 100 also includes a plurality of cell array regions 100C along the column direction (eg Figure 15 The select gate region 100S is located between the cell array region 100C (shown in the Y direction), and the first transition region 100B is located between the cell array region 100C and the select gate region 100S on the adjacent side along the column direction; multiple lines extending along the column direction and along the row direction (as shown in the Y direction) Figure 15an isolation structure 110 arranged along the X direction in the middle) and located in the substrate 100; a plurality of gate structures 200 extending along the row direction and arranged along the column direction, located on the cell array region 100C, the first transition region 100B and the adjacent selection gate region 100S, the gate structure 200 including: floating gates 180 located on a portion of the substrate 100 on both sides of the isolation structure 110, the floating gates 180 located in each gate structure 200 being arranged at intervals along the row direction; a control gate 170 covering the floating gates 180 along the row direction, as well as the substrate 100 and the isolation structure 110 between the floating gates 180; a source region 140 along the column direction, located in the substrate 100 between adjacent floating gates 180 in the cell array region 100C, the source region 140 also extending along the column direction to the first transition region 100B and the adjacent portion of the selection gate region. The first drain region 150 is located in the substrate 100 of the cell array region 100C, the first transition region 100B and the isolation structure 110 of the adjacent portion of the select gate region 100S along the row direction of the second side of the substrate 100; the isolation spacer 210 is located on the sidewall of the gate structure 200, and contacts the isolation spacer 210 located on the sidewall of the adjacent gate structure 200 in the cell array region 100C and the first transition region 100B; a silicide blocking layer (not shown) is located on the substrate 100, the isolation spacer 210 and the gate structure 200, and the silicide blocking layer exposes the cell array region 100C, the first transition region 100B and the adjacent select gate region 100S; and the metal silicide layer 300 is located on the top of the gate structure 200 and the top surface of the substrate 100 exposed by the silicide blocking layer.

[0126] In this embodiment, the gate structure 200 is also located on the first transition region 100B. The substrate 100 of the first transition region 100B is covered by the gate structure 200 and the isolation sidewall 210. The gate structure 200 and the isolation sidewall 210 of the first transition region 100B can serve as a barrier layer between the metal layer and the substrate 100 in the metal silicide process, preventing the metal layer from directly contacting the substrate 100 of the first transition region 100B, thereby preventing the metal silicide layer from being formed on the substrate 100 of the first transition region 100B, which is correspondingly beneficial to preventing the source region 140 and the first drain region 150 from being short-circuited by the metal silicide layer in the first transition region 100B. In addition, in the silicide process, During the formation of the barrier layer, there is no need to retain the silicide barrier film in the first transition region 100B, and the photolithography and etching processes for forming the silicide barrier layer do not need to be aligned in the first transition region 100B, which is beneficial to reducing the requirements for process accuracy and increasing the process window. In addition, in this embodiment, there is no need to form the silicide barrier layer on the portion of the gate structure 200 near the first transition region 100B in the cell array region 100C to reserve process space, which is beneficial to increasing the number of available gate structures 200 and reducing the area of ​​the entire cell array region 100C. In summary, the embodiment of the present invention is beneficial to increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process.

[0127] The substrate 100 provides a process platform for forming a NOR gate flash memory. Specifically, in this embodiment, the substrate 100 is used to form a 4F 2 In this NOR flash array, the area of ​​the NVM cell can be as small as 4F. 2 , which is beneficial to improving the storage unit area density.

[0128] The cell array region 100C is used to form memory cells. The select gate region 100S is located between the cell array regions 100C along the column direction. Logic devices are subsequently formed on the select gate region 100S. Specifically, select gates are subsequently formed on the select gate region 100S.

[0129] The active area (AA) of the selection gate region 100S on the adjacent side of the cell array region 100C is offset toward the first side along the row direction relative to the active area of ​​the cell array region 100C, and the isolation structure 110 of the selection gate region 100S is also offset toward the first side along the row direction relative to the isolation structure 110 of the cell array region 100C. The first transition region 100B serves as a boundary area (Boundary Area) and is located between the cell array region 100C and the adjacent selection gate region 100S, and is used to connect the cell array region 100C and the adjacent selection gate region 100S.

[0130] In this embodiment, the substrate 100 further includes a second transition region (not shown) located along the column direction between the cell array region 100C and the adjacent selection gate region 100S on the other side. The first transition region 100B and the adjacent selection gate region 100S constitute a first selection gate unit (not marked); the second transition region and the adjacent selection gate region 100S constitute a second selection gate unit (not shown), and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region 100C.

[0131] The active area of ​​the selection gate region 100S on the other side adjacent to the cell array region 100C is offset toward the second side along the row direction relative to the active area of ​​the cell array region 100C, and the isolation structure 110 of the selection gate region 100S is also offset toward the second side along the row direction relative to the isolation structure 110 of the cell array region 100C. The second transition region serves as a boundary region, located between the cell array region 100C and the selection gate region 100S on the other side, and is used to connect the cell array region 100C and the selection gate region 100S on the other side.

[0132] In this embodiment, the base 100 includes a substrate. As an example, the substrate is a silicon substrate.

[0133] The isolation structure 110 is used to define the active area and the isolation area of ​​the substrate 100. The substrate 100 isolated by the isolation structure 110 is used as the active area, and the remaining area is used as the isolation area. The isolation structure 110 is used to isolate adjacent device units along the row.

[0134] In this embodiment, the isolation structure 110 is an STI, and the material of the isolation structure 110 is silicon oxide.

[0135] In this embodiment, the isolation structure 110 includes a main extension portion (not labeled) located in the cell array region 100C and a first offset extension portion (not labeled) located in the adjacent side selection gate region 100S. The first offset extension portion is offset toward the first side along the row direction relative to the main extension portion. The isolation structure also includes a first transition extension portion (not labeled) connected to the first offset extension portion and the main extension portion and located on the first transition region 100B.

[0136] In this embodiment, the isolation structure 110 further includes a second offset extension portion (not shown) located on the other side of the selection gate region 100S adjacent to the cell array region 100C, and the second offset extension portion is offset toward the second side along the row direction relative to the main extension portion. The isolation structure further includes a second transition extension portion (not shown) connected to the second offset extension portion and the main extension portion and located on the second transition region.

[0137] In this embodiment, the isolation structure 110 further includes: a first extension portion (not shown) arranged along the row direction and spaced apart from the first offset extension portion, the first extension portion also extending along the column direction to the adjacent first transition region 100B and having a gap between it and the first transition extension portion; a second extension portion (not shown) arranged along the row direction and spaced apart from the second offset extension portion, the second extension portion also extending along the column direction to the adjacent second transition region and having a gap between it and the second transition extension portion.

[0138] In this embodiment, the gate structure 200 is also located on the second transition region and the adjacent select gate region 100S. In the second transition region, the isolation spacers 210 located on the sidewalls of the adjacent gate structures 200 are in contact. During the metal silicide process, the gate structure 200 and the isolation spacers 210 located in the second transition region can serve as a barrier layer between the metal layer and the substrate 100 in the second transition region, thereby preventing the metal layer from contacting the substrate 100 in the second transition region. This, in turn, can prevent the metal silicide layer 300 from forming on the substrate 100 in the second transition region, thereby preventing the source region 140 and the second drain region 160 from being connected by the metal silicide layer 300 in the second transition region, thereby preventing a short circuit.

[0139] As an example, the spacing between adjacent gate structures 200 located in the first transition region 100B and the second transition region is the same as the spacing between adjacent gate structures 200 located in the cell array region 100C. Moreover, the size of the gate structures 200 located in the first transition region 100B and the second transition region is the same as the size of the gate structure 200 located in the cell array region 100C, thereby making the structures of the first transition region 100B and the second transition region consistent with the cell array region 100C, which is conducive to improving process consistency.

[0140] When the NOR flash memory is operating, floating gate 180 captures and stores electrons. Even after power is lost, the electrons stored in floating gate 180 are not lost. Furthermore, the amount of charge stored in floating gate 180 changes the on-state voltage of the field-effect transistor. Different on-state voltages represent different states, thereby enabling information storage. In this embodiment, floating gate 180 is an island structure.

[0141] In this embodiment, the floating gate 180 is made of polysilicon.

[0142] When the NOR flash memory is operating, programming is achieved by changing the electron injection into the floating gate 180 or erasing from the floating gate 180 through the control gate 170. In this embodiment, the material of the control gate 170 is polysilicon.

[0143] In this embodiment, the gate structure 200 further includes an inter-gate dielectric layer 190 located between the control gate 170 and the floating gate 180 , between the control gate 170 and the isolation structure 110 , and between the control gate 170 and the substrate 100 .

[0144] The inter-gate dielectric layer 190 is used to isolate the control gate 170 from the floating gate 180 . The inter-gate dielectric layer 190 is also used to isolate the control gate 170 from the substrate 100 .

[0145] In this embodiment, the inter-gate dielectric layer 190 is a stacked structure. As an example, the inter-gate dielectric layer 190 is an ONO structure, and the inter-gate dielectric layer 190 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.

[0146] In this embodiment, the semiconductor structure further includes a tunneling oxide layer 155 located between the gate structure 200 and the substrate 100 , and between the isolation spacer 210 and the substrate 100 .

[0147] The tunneling oxide layer 155 is used to provide a tunneling channel for electrons from the substrate 100 to the floating gate 180. The tunneling oxide layer 155 is also used to isolate the floating gate 180 from the substrate 100. In this embodiment, the material of the tunneling oxide layer 155 is silicon oxide.

[0148] In this embodiment, for the convenience of illustration and description, only the tunnel oxide layer 155 is illustrated in the cross-sectional view.

[0149] The source region 140 is used as a common source region. In this embodiment, the source region 140 is further extended along the column direction and is located in the substrate 100 adjacent to the second transition region and a portion of the select gate region 100S.

[0150] In this embodiment, the source region 140 also extends along the column direction and is located in the substrate of the first transition region 100B and the adjacent portion of the selection gate region 100S, and the second transition region and the adjacent portion of the selection gate region 100S, so that the source region 140 can extend to the selection gate region 100S to be connected to the selection gate.

[0151] In this embodiment, the source region 140 extending along the column direction to the portion of the selection gate region S adjacent to the first transition region 100B is located between the first offset extension portion and the first extension portion adjacent to the first side along the row direction; the source region 140 also extending along the column direction to the portion of the selection gate region 100S adjacent to the second transition region is located between the second offset extension portion and the second extension portion adjacent to the second side along the row direction.

[0152] First drain region 150 is used to form a first drain sub-bit line. First drain region 150 is located in substrate 100 along the second side of the row direction of the main extension, first transition extension, and a portion of the first offset extension. First drain region 150 extends along the sidewalls of the main extension and first transition extension along the second side of the row direction. First drain region 150 also extends into a portion of substrate 100 along the sidewall of the adjacent first offset extension along the second side of the row direction. Thus, first drain region 150 extends into a portion of select gate region 100S adjacent to first transition region 100B, thereby connecting the memory cell corresponding to the first drain sub-bit line to the select gate.

[0153] In this embodiment, the semiconductor structure further includes a second drain region 160 located in the substrate 100 along the first side of the row direction of the isolation structure 110 in the cell array region 100C, the second transition region, and an adjacent portion of the select gate region 100S.

[0154] The second drain region 160 is used to form a second drain sub-bit line. The second drain region 160 extends along the sidewalls of the main extension and the second transition extension along the first side in the row direction. The second drain region 160 also extends into a portion of the substrate 100 along the sidewall of the adjacent second offset extension along the first side in the row direction. Thus, the second drain region 160 extends into a portion of the select gate region 100S adjacent to the second transition region, thereby connecting the memory cell corresponding to the second drain sub-bit line to the select gate.

[0155] In this embodiment, the doping depths of the first drain region 150 , the second drain region 160 , and the source region 140 in the substrate 100 are less than the depth of the isolation structure 110 , so that any two of the first drain region 150 , the second drain region 160 , and the source region 140 can be isolated by the isolation structure 110 .

[0156] When forming an NMOS device, the doping ions in the first drain region 150 , the second drain region 160 and the source region 140 are N-type ions; when forming a PMOS device, the doping ions in the first drain region 150 , the second drain region 160 and the source region 140 are P-type ions.

[0157] The isolation spacers 210 are used to protect the side walls of the gate structure 200. In the cell array region 100C and the first transition region 100B, the isolation spacers 210 located on the side walls of the adjacent gate structures 200 are in contact with each other, so that the isolation spacers 210 fill the space between the adjacent gate structures 200 in the cell array region 100C and the first transition region 100B, thereby achieving electrical isolation between the adjacent gate structures 200.

[0158] Among them, the substrate 100 located in the first transition region 100B is covered by the gate structure 200 and the isolation sidewall 210, so that it will not be exposed to the metal silicide process, and accordingly avoids the surface of the substrate 100 in the first transition region 100B from contacting the metal layer of the metal silicide process, thereby preventing the metal silicide layer 300 from being formed on the top surface of the substrate 100 in the first transition region 100B.

[0159] In this embodiment, in the second transition region, the isolation sidewalls 210 located on the side walls of adjacent gate structures 200 are in contact with each other, so that the isolation sidewalls 210 also fill the space between the adjacent gate structures 200 in the second transition region. The substrate 100 located in the second transition region is covered by the gate structure 200 and the isolation sidewalls 210, and will not be exposed to the metal silicide process, thereby avoiding the surface of the substrate 100 in the second transition region from contacting the metal layer of the metal silicide process, thereby preventing the metal silicide layer 300 from being formed on the top surface of the substrate 100 in the second transition region.

[0160] The isolation spacer 210 is made of a dielectric material. The material of the isolation spacer 210 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. The isolation spacer 210 can have a single-layer structure or a stacked-layer structure. In this embodiment, the isolation spacer 210 is a single-layer structure made of silicon nitride.

[0161] It should be noted that, in this embodiment, the semiconductor structure further includes a liner layer 220 located between the isolation spacer 210 and the substrate 100 , and between the isolation spacer 210 and the gate structure 200 .

[0162] The liner layer 220 is used to protect the gate structure 200. The liner layer 220 is also used to improve the adhesion between the isolation spacer 210 and the gate structure 200, thereby preventing the isolation spacer 210 from directly contacting the gate structure 200 and causing large stress defects. In this embodiment, the liner layer 220 is made of silicon oxide.

[0163] The substrate 100 generally includes other types of device regions, such as a peripheral device region (not shown). The silicide blocking layer (SAB) is located in a region where a metal silicide layer does not need to be formed, and is used to block the growth of metal silicide.

[0164] In this embodiment, the silicide blocking layer further exposes the second transition region and the adjacent select gate region 100S.

[0165] In this embodiment, the silicide blocking layer does not need to be retained on the first transition region 100B and the second transition region, and the lithography and etching processes for forming the silicide blocking layer do not need to be aligned in the first transition region 100B and the second transition region, which is beneficial to reducing the requirements for process accuracy and increasing the process window, and is beneficial to increasing the process window of the metal silicide process and reducing the difficulty of the metal silicide process.

[0166] The silicide barrier layer is made of a dielectric material to ensure that it can isolate the metal layer from the silicon during the metal silicide process. The silicide barrier layer can be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the silicide barrier layer is made of silicon oxide.

[0167] The metal silicide layer 300 is located on the top of the gate structure 200 exposed by the silicide blocking layer, and a gate plug is subsequently formed in contact with the gate structure 200. The metal silicide layer 300 is used to improve the adhesion between the gate structure 200 and the gate plug, and is also beneficial to reduce the contact resistance between the gate structure 200 and the gate plug, thereby correspondingly improving the performance of the semiconductor structure.

[0168] The metal silicide layer 300 is also located on the top surface of the substrate 100 exposed by the silicide blocking layer. In this embodiment, the silicide blocking layer also exposes the substrate 100 of the select gate region 100S. The substrate 100 of the select gate region 100S typically also includes a source region and a drain region corresponding to the select gate region 100S. The metal silicide layer 300 is correspondingly located on the top surfaces of the source region and the drain region of the select gate region 100S. Therefore, after a source plug contacting the source region of the select gate region 100S and a drain plug contacting the drain region of the select gate region 100S are subsequently formed, the metal silicide layer 300 helps improve the adhesion between the source plug and the source region of the select gate region 100S, and between the drain plug and the drain region of the select gate region 100S. It also helps reduce the contact resistance between the source plug and the source region of the select gate region 100S, and between the drain plug and the drain region of the select gate region 100S, thereby improving the performance of the semiconductor structure.

[0169] The material of the metal silicide layer 300 includes TiSi, NiSi, CoSi, NiPtSi, etc. In this embodiment, the material of the metal silicide layer 300 is NiPtSi.

[0170] In this embodiment, the semiconductor structure further includes: a covering dielectric layer 250 located on the metal silicide layer 300 and the silicide barrier layer.

[0171] The cover dielectric layer 250 is used to cover the metal silicide layer 300 to prevent the metal silicide layer 300 from being oxidized or causing metal contamination when exposed to air. The cover dielectric layer 250 can also be used as an etch stop layer in the subsequent contact hole etching process to define the stop position of the contact hole etching process, which helps prevent the contact hole etching process from causing over-etching of the substrate 100 or the gate structure 200. The cover dielectric layer 250 is made of a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0172] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a plurality of discrete cell array regions for forming memory cells; the substrate further comprising a select gate region located between the cell array regions along a column direction, and a first transition region located between the cell array region and an adjacent select gate region along a column direction; A plurality of isolation structures extending in the column direction and arranged in the row direction, located in the substrate; A plurality of gate structures extending in the row direction and arranged in the column direction are located on the cell array region, the first transition region, and the adjacent select gate region, the gate structures comprising: floating gates located on portions of the substrate on both sides of the isolation structure, the floating gates in each gate structure being arranged at intervals in the row direction; and control gates covering the floating gates, as well as the substrate and isolation structure between the floating gates in the row direction; A source region along the column direction is located in the substrate between adjacent floating gates in the cell array region, and the source region is further extended along the column direction and located in the substrate of the first transition region and an adjacent portion of the select gate region; A first drain region is located in the substrate on the second side of the isolation structure of the cell array region, the first transition region, and the adjacent portion of the select gate region along the row direction; an isolation spacer located on a sidewall of the gate structure, wherein the isolation spacer located on an adjacent sidewall of the gate structure contacts the cell array region and the first transition region; and a substrate of the first transition region is correspondingly covered by the gate structure and the isolation spacer; a silicide blocking layer, located on the substrate, the isolation sidewalls and the gate structure; the silicide blocking layer is located on a portion of the gate structure near the first transition region in the cell array region, and the silicide blocking layer exposes the cell array region, the first transition region and the adjacent select gate region; The metal silicide layer is located on the top of the gate structure and the top surface of the substrate exposed by the silicide barrier layer.

2. The semiconductor structure according to claim 1, wherein The isolation structure includes a main extension portion located in the cell array area and a first offset extension portion located in the adjacent side selection gate area, wherein the first offset extension portion is offset toward the first side along the row direction relative to the main extension portion. The isolation structure also includes a first transition extension portion connected to the first offset extension portion and the main extension portion and located on the first transition region; the first drain region is located in the substrate along the second side of the row direction of the main extension portion, the first transition extension portion and a portion of the first offset extension portion.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a covering dielectric layer located on the metal silicide layer and the silicide barrier layer.

4. The semiconductor structure according to any one of claims 1 to 3, wherein: The substrate further includes a second transition region located between the cell array region and the adjacent select gate region on the other side along the column direction; the source region further extends along the column direction and is located in the substrate between the second transition region and the adjacent portion of the select gate region; The semiconductor structure further includes: a second drain region located in the substrate along the first side of the row direction of the isolation structure of the cell array region, the second transition region, and the adjacent portion of the select gate region; The gate structure is also located on the second transition region and the adjacent select gate region; In the second transition region, the isolation spacers located on adjacent sidewalls of the gate structure are in contact with each other; The silicide blocking layer further exposes the second transition region and the adjacent select gate region; The first transition region and the adjacent selection gate region constitute a first selection gate unit; the second transition region and the adjacent selection gate region constitute a second selection gate unit, and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region.

5. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, comprising a plurality of discrete cell array regions for forming memory cells; the substrate further comprising a select gate region located between the cell array regions along a column direction, and a first transition region located between the cell array region and an adjacent select gate region along a column direction; a plurality of isolation structures extending along the column direction and arranged along the row direction are formed in the substrate; a floating gate material layer is formed on the substrate; an opening is further formed in the floating gate material layer of the cell array region along the column direction, the opening also penetrating the first transition region and an adjacent portion of the select gate region along the column direction; an active region is formed in the substrate below the opening; a first drain region is formed in the substrate along a second side of the row direction between the isolation structures of the cell array region, the first transition region, and the adjacent portion of the select gate region; forming a control gate material layer covering the floating gate material layer, the isolation structure and the substrate; Patterning the control gate material layer and the floating gate material layer to form a plurality of control gates extending in the row direction and arranged in the column direction on the cell array region, the first transition region, and the adjacent select gate region, with the remaining floating gate material layer located at the bottom of the control gates serving as floating gates. The floating gates and the control gates located on the floating gates constitute a gate structure; forming isolation spacers on the sidewalls of the gate structure, wherein the isolation spacers located on the adjacent sidewalls of the gate structure are in contact with each other in the cell array region and the first transition region; The substrate of the first transition region is correspondingly covered by the gate structure and the isolation spacer; forming a silicide blocking layer on the substrate, the isolation spacer and the gate structure, wherein the silicide blocking layer is formed on a portion of the gate structure in the cell array region close to the first transition region, and the silicide blocking layer exposes the cell array region, the first transition region and the adjacent select gate region; A metal silicide layer is formed on the top of the gate structure and the top surface of the substrate where the silicide blocking layer is exposed.

6. The method for forming a semiconductor structure according to claim 5, wherein: The steps of forming the silicide blocking layer include: conformally covering the substrate, isolation sidewalls and gate structure with a silicide blocking film; removing the silicide blocking film located on the cell array region, the first transition region and the adjacent selection gate region, and the remaining silicide blocking film is used as a silicide blocking layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: In the step of forming the isolation spacer, the isolation spacer is also formed on the top of the gate structure and the top surface of the substrate and the isolation structure; The method for forming the semiconductor structure also includes: in the step of removing the silicide blocking film located on the cell array region, the first transition region and the adjacent selection gate region, removing the isolation sidewalls on the gate structure and the top surface of the isolation structure located in the cell array region and the first transition region, as well as the isolation sidewalls on the top of the gate structure, the substrate and the top surface of the isolation structure located adjacent to the selection gate region.

8. The method for forming a semiconductor structure according to claim 6, wherein: The step of removing the silicide blocking film located on the cell array region, the first transition region and the adjacent select gate region includes: forming a pattern layer on the silicide blocking film, wherein the pattern layer has a pattern opening exposing the silicide blocking film on the cell array region, the first transition region and the adjacent select gate region; using the pattern layer as a mask, removing the silicide blocking film exposed by the pattern opening to form the silicide blocking layer.

9. The method for forming a semiconductor structure according to claim 6, wherein: The process of forming the silicide barrier film includes an atomic layer deposition process or a chemical vapor deposition process.

10. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the silicide blocking film located on the cell array region, the first transition region and the adjacent selection gate region includes: one or both of a dry etching process and a wet etching process.

11. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming the metal silicide layer includes: forming a metal layer on the silicide barrier layer and on the top and sidewalls of the isolation spacers exposed by the silicide barrier layer, the top of the gate structure and the top surface of the substrate; performing a heat treatment on the metal layer to convert the metal layer and a partial thickness of the gate structure, and the metal layer and a partial thickness of the substrate into a metal silicide layer; The remaining metal layer is removed.

12. The method for forming a semiconductor structure according to claim 11, wherein: The heat treatment of the metal layer includes: annealing the metal layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The process of removing the remaining metal layer includes a wet etching process.

14. The method for forming a semiconductor structure according to claim 5, wherein: In the step of providing the substrate, the isolation structure includes a main extension located in the cell array region and a first offset extension located in the adjacent select gate region, wherein the first offset extension is offset toward the first side along the row direction relative to the main extension, and the isolation structure further includes a first transition extension connected to the first offset extension and the main extension and located on the first transition region; The first drain region is located in the substrate along the second side of the main extension, the first transition extension, and a portion of the first offset extension.

15. The method for forming a semiconductor structure according to claim 5, wherein: After forming the metal silicide layer, the method for forming a semiconductor structure further includes: forming a capping dielectric layer on the metal silicide layer and the silicide barrier layer.

16. The method for forming a semiconductor structure according to any one of claims 5 to 15, wherein: In the step of providing a substrate, the substrate further includes a second transition region located between the cell array region and the adjacent select gate region on the other side along the column direction, the source region further extends along the column direction and is located in the substrate between the second transition region and the adjacent portion of the select gate region, and a second drain region is formed in the substrate on the first side along the row direction between the isolation structure of the cell array region, the second transition region, and the adjacent portion of the select gate region; The first transition region and the adjacent selection gate region constitute a first selection gate unit; the second transition region and the adjacent selection gate region constitute a second selection gate unit, and the second selection gate unit and the first selection gate unit are symmetrical about the center of the cell array region; In the step of forming the control gate, the control gate is also located on the second transition region and the adjacent select gate region; In the step of forming the isolation spacers, in the second transition region, the isolation spacers located on adjacent sidewalls of the gate structure are in contact with each other; In the step of forming the silicide blocking layer, the silicide blocking layer also exposes the second transition region and the adjacent select gate region.

Images