Display panel and display device using the same

Abstract

Disclosed are a display panel and a display device using the same, in which two signal lines include a bridge portion in any one of the signal lines at an intersection region thereof. The display panel includes a substrate, a first signal line along a first direction, a first insulating film covering the first signal line, a second signal line along a second direction different from the first direction, a second insulating film covering the first insulating film, and a first pixel electrode on the second insulating film, wherein the second signal line includes an extension line, a connection line, an overlapping line, and a bridge portion connected to the extension line, the connection line, and the overlapping line through a contact hole provided on the second insulating film.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0141301, filed on October 28, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to display panels and display devices using the display panels. Background Technology

[0004] The display device includes a liquid crystal display device and a light-emitting display device, and the display device includes a display panel configured to output images.

[0005] As the display panel displays a high resolution and the number of masks used in the display panel decreases, the resistive-capacitive load (RC load) in the display panel increases, resulting in a decrease in image quality due to the reduced charging rate.

[0006] In particular, as the overlap area between two intersecting lines increases, the parasitic capacitance between the two lines increases, thereby increasing the RC load in the display panel. Summary of the Invention

[0007] This disclosure is made in view of the above-mentioned problems, and the purpose of this disclosure is to provide a display panel in which two signal lines include a bridging portion in either of their intersection areas; and a display device using the display panel.

[0008] According to one aspect of this disclosure, the above and other objectives can be achieved by providing a display panel comprising: a substrate; a first signal line disposed along a first direction of the substrate and disposed on the substrate; a first insulating film disposed on the substrate and configured to cover the first signal line; a second signal line disposed along a second direction different from the first direction; a second insulating film configured to cover the first insulating film; and a first pixel electrode disposed on the second insulating film and electrically connected to a transistor disposed on the first insulating film, wherein the second signal line comprises: an extension line disposed on a first side of the first signal line relative to the first signal line intersecting the second signal line and disposed on the first insulating film; a connecting line disposed on a second side of the first signal line and disposed on the first insulating film; an overlapping line disposed on the first insulating film and overlapping with the first signal line; and a bridging portion disposed on the second insulating film and connected to the extension line, the connecting line, and the overlapping line through a contact hole disposed on the second insulating film.

[0009] According to another aspect of this disclosure, a display panel is provided, comprising: a substrate; a first signal line disposed along a first direction of the substrate and disposed on the substrate; a first insulating film disposed on the substrate and configured to cover the first signal line; a second signal line disposed along a second direction different from the first direction; a second insulating film configured to cover the first insulating film; and a first pixel electrode disposed on the second insulating film and electrically connected to a transistor disposed on the first insulating film, wherein the second signal line comprises: an extension line disposed on a first side of the first signal line relative to the first signal line intersecting the second signal line and disposed on the first insulating film; a connecting line disposed on a second side of the first signal line and disposed on the first insulating film; and a bridging portion disposed on the second insulating film and connected to the extension line and the connecting line through a contact hole disposed on the second insulating film.

[0010] According to another aspect of this disclosure, a display panel is provided, comprising: a substrate; a first signal line disposed along a first direction of the substrate and disposed on the substrate; a first insulating film disposed on the substrate and configured to cover the first signal line; a second signal line disposed along a second direction different from the first direction; and a second insulating film configured to cover the first insulating film; wherein the second signal line comprises: a plurality of lines disposed on the first insulating film and separated from each other; and a bridging portion disposed on the second insulating film, wherein the bridging portion is connected to the plurality of lines through contact holes disposed on the second insulating film.

[0011] According to another aspect of this disclosure, a display device is provided, comprising: a display panel according to this disclosure; a data driver configured to provide a data voltage to a data line disposed in the display panel; a gate driver configured to provide a gate voltage to a gate line disposed in the display panel; and a controller configured to control the data driver and the gate driver.

[0012] In addition to the effects of this disclosure as mentioned above, those skilled in the art will clearly understand other purposes of this disclosure based on the following description. Attached Figure Description

[0013] The above and other objects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0014] Figure 1 A display device according to an embodiment of the present disclosure is shown;

[0015] Figure 2A and Figure 2B The pixel structure applied to a display device according to this disclosure is shown;

[0016] Figure 3 Four pixels of the display panel according to this disclosure are shown;

[0017] Figure 4 The setting is shown Figure 3 The first panel electrode in the pixel shown;

[0018] Figure 5 The setting is shown Figure 3 The second panel electrode in the pixel shown;

[0019] Figure 6 The setting is shown Figure 3 The third panel electrode in the pixel shown;

[0020] Figure 7A and Figure 7B It is along Figure 3 A cross-sectional view of A-A';

[0021] Figure 8 It is along Figure 3 Another cross-sectional view of A-A'; and

[0022] Figure 9 It is along Figure 3 Another cross-sectional view of A-A'. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms, and it should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0024] The shapes, dimensions, ratios, angles, and numbers disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. Throughout the specification, similar reference numerals indicate similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the focus of this disclosure. Where terms such as “comprising,” “having,” and “including” are used in this specification, an additional part may be added unless “only…” is used. Unless otherwise stated, singular terms may include plural forms.

[0025] When interpreting components, even if not explicitly described, the components are interpreted as including a range of tolerances.

[0026] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "next to," one or more parts may be arranged between two other parts unless "exactly" or "directly" is used.

[0027] When describing temporal relationships, such as when time sequence is described as "after", "following", "next", and "before", discontinuous cases may be included unless "exactly" or "directly" is used.

[0028] It should be understood that while the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0029] It should be understood that the term "at least one" includes all combinations associated with any one of them. For example, "at least one of the first element, the second element, and the third element" can include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each of the first element, the second element, and the third element.

[0030] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may cooperate with each other and be technically driven in various ways. The embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0031] In the following, a display panel according to this disclosure and a display device using the display panel will be described in detail with reference to the accompanying drawings. In the drawings, even if the same or similar elements are depicted in different drawings, the same or similar elements are indicated by the same reference numerals.

[0032] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 A display device according to an embodiment of the present disclosure is shown. Figure 2A and Figure 2B The pixel structure applied to a display device according to this disclosure is shown.

[0034] The display device according to this disclosure can constitute various electronic devices. For example, electronic devices can be smartphones, tablets, televisions, monitors, etc.

[0035] like Figure 1As shown, the display device according to this disclosure includes: a display panel 100, which includes a display area 120 configured to output an image and a non-display area 130 disposed around the periphery of the display area; a gate driver 200 configured to provide gate signals to gate lines GL1 to GLg disposed in the display area of ​​the display panel 100; a data driver 300 configured to provide data voltages to data lines DL1 to DLd disposed in the display panel; and a controller 400 configured to control the operation of each of the gate driver 200 and the data driver 300.

[0036] First, the display panel 100 includes a display area 120 and a non-display area 130. In the display area 120, there are gate lines GL1 to GLg, data lines DL1 to DLd, and pixels 110.

[0037] The display panel 100 may be a light-emitting display panel composed of light-emitting devices (EDs), or it may be a liquid crystal display panel that displays images using liquid crystals.

[0038] Reference Figure 2A When the display panel 100 is a light-emitting display panel, the pixel 110 included in the display panel 100 may include a light-emitting device ED, a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. That is, the pixel 110 includes a pixel driving circuit PDC and a light-emitting part, and the pixel driving circuit PDC may include a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2. In addition, the light-emitting part may include a light-emitting device ED.

[0039] The light-emitting device (ED) may include any one of an organic light-emitting layer, an inorganic light-emitting layer, and a quantum dot light-emitting layer. Alternatively, the ED may include a stacked or hybrid structure of an organic light-emitting layer (or an inorganic light-emitting layer) and a quantum dot light-emitting layer.

[0040] The switching transistor Tsw1, constituting the pixel driving circuit PDC, can be turned on or off by the gate signal GS provided to the gate line GL. When the switching transistor Tsw1 is on, the data voltage Vdata provided through the data line DL is supplied to the driving transistor Tdr. The first voltage EVDD can be supplied to the driving transistor Tdr and the light-emitting device ED through the first voltage power line PLA. In addition, the second voltage EVSS is supplied to the light-emitting device ED through the second voltage power line PLB. The sensing transistor Tsw2 can be turned on or off by the sensing control signal SS provided through the sensing control line SCL. In addition, the sensing line SL can be connected to the sensing transistor Tsw2. The reference voltage Vref can be supplied to the pixel 110 through the sensing line SL. The sensing signal related to the characteristic change of the driving transistor Tdr can be transmitted to the sensing line SL through the sensing transistor Tsw2.

[0041] Although the light-emitting display panel according to this disclosure can be formed as Figure 2A The structure shown is not limited to this. Therefore, in addition to Figure 2A In addition to the structure shown, the light-emitting display panel according to this disclosure can be modified in various ways.

[0042] Reference Figure 2B When the display panel 100 is a liquid crystal display panel, the pixels 110 included in the display panel 100 may include a switching transistor Tsw, a common electrode, and liquid crystal. For example, pixel 110 may include a pixel driving circuit PDC and a light-emitting part. The pixel driving circuit PDC may include a switching transistor Tsw and a common electrode Vcom. Furthermore, the light-emitting part may include liquid crystal. Figure 2B In the figure, the reference numeral "Clc" indicates the storage capacitance formed in the liquid crystal by the pixel voltage provided to the pixel electrode connected to the switching transistor Tsw and the common voltage Vcom provided to the common electrode.

[0043] When the display panel 100 is a liquid crystal display panel, the display device may further include a backlight configured to emit light to the liquid crystal display panel.

[0044] The display panel 100 can form a pixel area in which pixels 110 are formed. In the display panel 100, there are signal lines configured to provide various signals to the pixel driving circuit PDC disposed in the pixels 110.

[0045] For example, in such Figure 2A In the light-emitting display panel shown, which includes pixels 110, the signal lines may include gate line GL, data line DL, sensing control line SCL, first voltage power supply line PLA, second voltage power supply line PLB, and sensing line SL.

[0046] In addition, in such Figure 2B In the liquid crystal display panel shown, which includes pixels 110, the signal lines may include gate lines GL and data lines DL.

[0047] Then, the data driver 300 can be disposed on the on-film chip attached to the display panel 100. Furthermore, the data driver 300 can be connected to a motherboard on which the controller 400 is disposed. In this case, wiring for electrically connecting the data driver 300 and the display panel 100 can be disposed in the on-film chip. For this purpose, the wiring is electrically connected to pads disposed in the display panel 100 and the motherboard. The motherboard is electrically connected to an external substrate on which an external system is mounted.

[0048] The data drive 300 can be directly installed on the display panel 100 and can be electrically connected to the motherboard.

[0049] However, the data driver 300 can be integrated with the controller 400 into a single integrated circuit. Furthermore, the integrated circuit can be disposed on an on-film chip or directly mounted on the display panel 100.

[0050] An external system performs the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a smartphone, the external system can receive various voice, image, and text information via a wireless communication network and send the received image information to the controller 400. The image information can be input image data.

[0051] When the display panel 100 is a light-emitting display panel, the data driver 300 can receive a sensing signal related to the characteristic change of the driving transistor Tdr disposed in the light-emitting display panel from the light-emitting display panel, and can send the sensing signal to the controller 400.

[0052] Next, the gate driver 200 can be composed of an integrated circuit and then integrated with the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) method. If the gate-in-panel (GIP) method is used, the transistors constituting the gate driver 200 can be disposed in the non-display area 130 using the same process as the transistors disposed in each pixel 110 of the display area 120.

[0053] When a gate pulse generated in the gate driver 200 is provided to the gate of the switching transistor Tsw1 or Tsw disposed in the pixel 110, the switching transistor is turned on. Therefore, light can be output from the pixel. When a gate cutoff signal is provided to the switching transistor Tsw1 or Tsw, the switching transistor is turned off. Therefore, no light is output from the pixel. The gate signal GS provided to the gate line GL includes the gate pulse and the gate cutoff signal.

[0054] Finally, the controller 400 can realign the input image data sent from the external system using a timing synchronization signal sent from the external system. Additionally, the control unit 400 may include: a data aligner configured to provide the realigned image data to the data driver 300; a control signal generator configured to generate a gate control signal GCS and a data control signal DCS using the timing synchronization signal; an input section configured to receive the timing synchronization signal and input image data sent from the external system, and to send the received timing synchronization signal and input image data to the data aligner and the control signal generator; and an output section configured to output the image data Data generated in the data aligner and the control signals DCS and GCS generated in the control signal generator to the data driver 300 or the gate driver 200.

[0055] The controller 400 may be embedded in the display panel 100. Alternatively, the controller 400 may also perform functions such as analyzing touch sensing signals received through a touch panel attached to the display panel 100 and sensing the presence and location of a touch.

[0056] In the following text, such as Figure 2A As shown, a light-emitting display panel including a light-emitting device (ED) is described as an example of a display panel according to this disclosure.

[0057] Figure 3 Four pixels of the display panel according to this disclosure are shown. Figure 4 The setting is shown Figure 3 The first panel electrode in the pixel shown. Figure 5 The setting is shown Figure 3 The second panel electrode in the pixel shown. Figure 6 The setting is shown Figure 3 The third panel electrode in the pixel shown. Figure 7A and Figure 7B It is along Figure 3 A-A' cross-sectional view.

[0058] like Figures 3 to 7B As shown, the display panel according to this disclosure includes a substrate 101, a first signal line L1 disposed along a first direction of the substrate 101 and disposed on the first substrate 101, a first insulating film 102 disposed on the substrate 101 and configured to cover the first signal line L1, a second signal line L2 disposed along a second direction different from the first direction, a second insulating film 103 configured to cover the first insulating film 102, and a first pixel electrode disposed on the second insulating film 103 and electrically connected to a transistor disposed on the first insulating film 102.

[0059] The second signal line L2 may include: an extension line L2a, which is disposed on a first side of the first signal line L1 relative to the first signal line L1 intersecting with the second signal line L2, and disposed on the first insulating film 102; a connecting line L2b, which is disposed on a second side of the first signal line L1 and disposed on the first insulating film 102; an overlapping line L2c, which overlaps with the first signal line, wherein the first insulating film 102 is located between the overlapping line L2c and the first signal line; and a bridging portion L2d disposed on the second insulating film. Furthermore, the bridging portion L2d can be connected to the extension line L2a, the connecting line L2b, and the overlapping line L2c through contact holes CH1 to CH4 disposed on the second insulating film 103.

[0060] like Figure 1 As shown, the display panel according to this disclosure may include a plurality of pixels 110. Figure 3 The image shows the four pixels that make up a single pixel. Figure 3 The diagram shows a red pixel representing red (R), a blue pixel representing blue (B), a white pixel representing white (W), and a green pixel representing green (G).

[0061] Each pixel may include a pixel driving circuit (PDC) and a light-emitting unit (EU). Figure 3 In the pixel drive circuit PDC shown for each pixel, as follows: Figure 2A As shown, there is a switching transistor Tsw1, a driving transistor Tdr, and a sensing transistor Tsw2. The light-emitting part EU can be formed by a light-emitting device ED, and the light-emitting device ED can be formed by a light-emitting diode. Furthermore, the light-emitting diode can be an organic light-emitting diode or an inorganic light-emitting diode. However, this disclosure is not limited thereto, and it can be a light-emitting diode having organic or inorganic materials.

[0062] Within each pixel, there are signal lines configured to provide various signals to the pixel driving circuitry (PDC). For example, Figure 3 The display panel shown may include a data line DL, a gate line GL, a first voltage power supply line PLA, a sensing line SL, and a sensing control line SCL.

[0063] In this disclosure, the first signal line L1 can be along... Figure 1 The first direction (e.g., vertical direction) of the display panel 100 shown is provided on any one of the signal lines in the display panel 100. For example, each of the data line DL, the first voltage power line PLA, and the sensing line SL can be the first signal line L1.

[0064] In addition, the second signal line L2 can be along... Figure 1The second direction (a direction different from the first direction) of the display panel 100 shown is provided on any one of the signal lines in the display panel 100. For example, each of the gate line GL and the sensing control line SCL can be the second signal line L2. The second direction can be horizontal.

[0065] This disclosure can be embodied in either the first signal line or the second signal line including a bridging portion in the region where the first signal line L1 and the second signal line L2 intersect each other.

[0066] In the following description, a display panel having a second signal line including a bridging portion is described as an example of the present disclosure.

[0067] Reference Figure 3 The area where the first signal line L1 and the second signal line L2 intersect can be represented by K1 to K6.

[0068] For example, in the first intersection region indicated by K1, two data lines DL intersect with the gate line GL. In this document, each of the two data lines DL can be a first signal line, and the gate line GL can be a second signal line.

[0069] In the second intersection region indicated by K2, the sensing line SL intersects with the gate line GL. At this time, the sensing line SL can be a first signal line, and the gate line GL can be a second signal line.

[0070] In the third intersection region indicated by K3, the two data lines DL intersect the gate line GL in the same manner as in the first intersection region K1. Therefore, the description of the first intersection region K1 can be applied equally to the third intersection region K3.

[0071] In the fourth intersection region indicated by K4, the two data lines DL intersect with the sensing control line SCL. In this text, each of the two data lines DL can be a first signal line, and the sensing control line SCL can be a second signal line.

[0072] In the fifth intersection region indicated by K5, the sensing line SL intersects with the sensing control line SCL. In this text, the sensing line SL can be a first signal line, and the sensing control line SCL can be a second signal line.

[0073] In the sixth intersection region indicated by K6, the two data lines DL intersect with the sensing control line SCL in the same manner as in the fourth intersection region K4.

[0074] In the region where the two signal lines L1 and L2 intersect, one of the two signal lines L1 and L2 includes a bridging portion L2d. Moreover, these features can be implemented in the first intersection region K1 to the sixth intersection region K6.

[0075] Among the resistive-capacitive loads (hereinafter referred to as RC loads) generated when two signal lines L1 and L2 intersect each other, the RC loads that affect defects in the display panel are those generated in the area where the data line DL and the gate line GL intersect each other.

[0076] In the following description, for ease of illustration, a display panel in which the first signal line L1 is a data line DL and the second signal line L2 is a gate line GL is described as an example of the present disclosure.

[0077] As described above, the regions where the data line DL and the gate line GL intersect are the first intersection region K1 and the third intersection region K3. Therefore, embodiments of this specification will be described with reference to the first intersection region K1.

[0078] Figure 7A and Figure 7B It is along Figure 3 The cross-sectional view of A-A' in the first intersecting region K1 is shown.

[0079] The substrate 101 can be a glass substrate or a plastic substrate, and can be formed from various films.

[0080] like Figure 4 As shown, a first panel electrode can be formed on the substrate 101. Some of the first panel electrodes can be data lines DL used as first signal lines L1. That is, the first signal line L1, which is one of the first panel electrodes, is... Figure 7A and Figure 7B As shown in the figure, the first signal line L1 can be the data line DL.

[0081] The data voltage Vdata generated from the data driver 300 can be supplied to the data line DL. The data voltage Vdata can also be supplied to transistors configured in the pixel driving circuit. For example, as... Figure 2A and Figure 2B As shown, the data voltage Vdata can be supplied to either the switching transistor Tsw1 or the switching transistor Tsw.

[0082] The first signal line L1 can be disposed in a first direction of the substrate 101. For example, it can be along... Figure 1 The first signal line L1 is set in the vertical direction of the display panel shown.

[0083] The first signal line L1 can be covered by the first insulating film 102.

[0084] The first insulating film 102 may include a buffer 102a that contacts the first signal line L1 and a gate insulating film 102b that covers the buffer 102a.

[0085] The buffer 102a can be disposed on the substrate 101.

[0086] A gate insulating film 102b can be formed on the upper surface of the buffer 102a. The gate insulating film 102b can be disposed between the active layer of the driving transistor Tdr disposed in the pixel driving circuit PDC and the gate electrode of the driving transistor Tdr. The gate insulating film 102b can be configured to cover the active layer on the buffer 102a. Furthermore, the gate electrode of the driving transistor Tdr can be disposed on the gate insulating film 102b.

[0087] The thickness of the buffer 102a located in the overlapping region with the first signal line L1 can be greater than the thickness of the buffer 102a located in the overlapping region with the driving transistor Tdr or other transistors besides the driving transistor Tdr. Therefore, the thickness of the first insulating film 102 located in the region overlapping with the first signal line L1 can be greater than the thickness of the first insulating film 102 located in the region overlapping with the driving transistor Tdr. That is, the thickness of the first insulating film 102 disposed between the first signal line L1 and the overlapping line L2c can be greater than the thickness of the first insulating film 102 disposed in the overlapping region with the driving transistor Tdr or other transistors besides the driving transistor Tdr.

[0088] The thickness of the gate insulating film 102b disposed at the upper end of the first signal line L1 can be greater than the thickness of the gate insulating film 102b in the region where the driving transistor Tdr is disposed. For example, the thickness of the gate insulating film 102b located in the region overlapping with the first signal line L1 can be greater than the thickness of the gate insulating film 102b located in the region overlapping with the driving transistor Tdr.

[0089] This thickness difference can be formed by etching the buffer 102a or the gate insulating film 102b using a halftone mask (H / T mask).

[0090] The buffer 102a may be formed of at least one inorganic membrane or at least one organic membrane. Alternatively, the buffer 102a may be formed by stacking at least one inorganic membrane and at least one organic membrane.

[0091] The gate insulating film 102b may be formed of at least one inorganic film or at least one organic film. Alternatively, the gate insulating film 102b may be formed by stacking at least one inorganic film and at least one organic film.

[0092] like Figure 5 As shown, a second panel electrode can be formed at the upper end of the first insulating film 102. Some of the second panel electrodes can be second signal lines L2, and the second signal lines L2 can be gate lines GL. The second panel electrode may include extension lines L2a, connecting lines L2b, and overlapping lines L2c constituting the second signal lines L2.

[0093] The second signal line L2 can be a gate line GL. An extension line L2a can be disposed on a first side of the first signal line L1 relative to the first signal line L1 intersecting with the second signal line L2. The second signal line L2 may include: an extension line L2a on the first insulating film 102, a connecting line L2b disposed on a second side of the first signal line L1 and disposed on the first insulating film 102, an overlapping line L2c disposed on the first insulating film 102 and overlapping with the first signal line L1, and a bridging portion L2d on the second insulating film 103. The bridging portion L2d can be connected to the extension line L2a, the connecting line L2b, and the overlapping line L2c through a contact hole disposed on the second insulating film 103.

[0094] Figure 5 Some of the second panel electrodes shown can be as follows: Figure 7A and Figure 7B The extension line L2a, connecting line L2b, and overlapping line L2c are shown. (Refer to...) Figure 7A and Figure 7B The left side of the first signal line L1 is referred to as the first side, and the right side of the first signal line L1 can be referred to as the second side. An extension line L2a is provided on the first side of the first signal line L1, and a connecting line L2b can be provided on the second side of the first signal line L1. An overlapping line L2c can be provided to overlap with the first signal line L1.

[0095] like Figure 7A and Figure 7B As shown, the second panel electrode disposed between the two first signal lines L1 can be a connecting line L2b disposed on the right side relative to the first signal line L1 intersecting with the second signal line L2. Alternatively, the second panel electrode can be an extension line L2a disposed on the left side relative to the first signal line L1 intersecting with the second signal line L2.

[0096] The second signal line L2 may include an extension line L2a, a connecting line L2b, and an overlapping line L2c. The extension line L2a, connecting line L2b, and overlapping line L2c may be arranged in a second direction different from the first direction. A second insulating film 103 may be disposed on the first insulating film 102, and the second insulating film 103 may cover the first insulating film 102. Figure 7A and Figure 7B As shown, the extension line L2a, connecting line L2b and overlapping line L2c provided on the first insulating film 102 can also be covered by the second insulating film 103.

[0097] The second insulating film 103 may include a protective film 103a disposed on the extension line L2a, the connecting line L2b, and the overlapping line L2c, and a planarization film 103b disposed on the protective film 103a. The protective film 103a may protect the extension line L2a, the connecting line L2b, and the overlapping line L2c, or it may insulate the extension line L2a, the connecting line L2b, and the overlapping line L2c from other metallic materials. In addition, the planarization film 103b may be used to reduce the step difference generated by the components disposed below the planarization film 103b.

[0098] For example, various transistors and signal lines constituting the pixel driving circuit PDC can be disposed between the first insulating film 102 and the second insulating film 103. In this case, the various transistors and signal lines can have different thicknesses, and the thickness of the area where transistors and signal lines are disposed can be different from the thickness of the area where transistors and signal lines are not disposed.

[0099] Due to the step difference formed by the transistor and signal line, the upper surface of the protective film 103a covering the transistor and signal line may be uneven.

[0100] A planarization film 103b is formed on the upper surface of the protective film 103a and is configured to planarize the uneven upper surface. The planarization film 103b is configured to have a thickness greater than that of the protective film 103a, thereby forming a planarized surface on the upper surface of the planarization film 103b.

[0101] The protective film 103a may be formed from at least one inorganic film.

[0102] The planarization membrane 103b can be formed from at least one organic membrane, or it can be formed in a stacked structure of at least one inorganic membrane and at least one organic membrane.

[0103] like Figure 6 As shown, a third panel electrode can be formed at the upper end of the second insulating film 103. Some of the third panel electrodes can be gate lines GL used as the second signal line L2. Specifically, the third panel electrode may include a bridging portion L2d configured to form the second signal line L2.

[0104] Figure 6 Some of the third panel electrodes shown can be as follows: Figure 7A and Figure 7B The bridging part L2d is shown.

[0105] The bridging portion L2d can be disposed on the second insulating film 103. The bridging portion L2d can be connected to the extension line L2a, the connecting line L2b, and the overlapping line L2c through the contact holes CH1, CH2, CH3, and CH4 formed on the second insulating film.

[0106] For example, the bridging section L2d may include a first bridge L2d1 connected to the extension line L2a and the overlapping line L2c, and a second bridge L2d2 connected to the connecting line L2b and the overlapping line L2c.

[0107] The first bridge L2d1 can be connected to the extension line L2a through the first contact hole CH1 formed on the second insulating film 103, and can be connected to the overlapping line L2c through the second contact hole CH2 formed on the second insulating film 103.

[0108] The second bridge L2d2 can be connected to the connecting line L2b through the fourth contact hole CH4 formed on the second insulating film 103, and can be connected to the overlapping line L2c through the third contact hole CH3 formed on the second insulating film 103.

[0109] The overlapping line L2c can be connected to the first bridge L2d1 through the second contact hole CH2, and can be connected to the second bridge L2d2 through the third contact hole CH3.

[0110] Extension line L2a is connected to first bridge L2d1 via first contact hole CH1. First bridge L2d1 is connected to overlapping line L2c via second contact hole CH2. Overlapping line L2c is connected to second bridge L2d2 via third contact hole CH3. Second bridge L2d2 can be connected to connecting line L2b via fourth contact hole CH4. Therefore, extension line L2a and connecting line L2b, which are separate from each other and have a first signal line L1 between them, can be electrically connected via first bridge L2d1 connected to extension line L2a and overlapping line L2c, and second bridge L2d2 connected to overlapping line L2c and connecting line L2b.

[0111] Therefore, the parasitic capacitance generated between the first signal line L1 and the second signal line L2 can be reduced, and a second signal line L2 intersecting with the first signal line L1 can be formed.

[0112] In the region of the first insulating film 102 where the first signal line L1 and the overlapping line L2c are provided, the overlapping line L2c, the extension line L2a and the connecting line L2b are not provided on the inclined surface M of the first insulating film that is inclined by the first signal line L1 (hereinafter referred to as the inclined surface M of the first insulating film).

[0113] Therefore, no parasitic capacitance caused by the overlap between the first signal line L1 and the second signal line L2 is generated in the inclined surface M of the first insulating film. Thus, the RC load of the data voltage Vdata transmitted along the data line DL or the gate signal GS transmitted along the gate line GL can be reduced.

[0114] For example, in the first intersection region K1, the first signal line L1 overlaps only with the overlapping line L2c configured to form the second signal line L2. Therefore, the RC load in each of the gate line GL and data lines DL can be reduced compared to the RC load in each of the gate lines and data lines in a prior art display panel where the second signal line L2 is formed on the inclined surface M of the first insulating film. Thus, image quality defects caused by RC load can be reduced in this disclosure.

[0115] Furthermore, as described above, the thickness of the buffer 102a disposed on the first signal line L1 can be greater than the thickness of the buffer disposed on the driving transistor Tdr.

[0116] Therefore, the parasitic capacitance between the first signal line L1 and the overlapping line L2c can also be reduced. Consequently, due to the increased RC load of the gate signal GS transmitted according to the data line or along the gate line GL (high resolution and mask reduction), a decrease in charging rate may occur in prior art display panels. Image quality deteriorates due to the increased RC load.

[0117] For example, the RC load may increase due to parasitic capacitance generated between intersecting data lines and gate lines. Specifically, as the width of the signal lines decreases, the RC load may increase due to parasitic capacitance generated between overlapping data lines and gate lines on the inclined surface M of the first insulating film. To prevent this, the intersection area between the data lines and gate lines must be reduced.

[0118] Therefore, in this disclosure, the second signal line L2 is not disposed on the inclined surface M of the first insulating film, and the first signal line L1 overlaps only with the overlapping line L2c constituting the second signal line L2.

[0119] Furthermore, in this disclosure, the thickness of the first insulating film 102 disposed at the upper end of the first signal line L1 is greater than the thickness of the first insulating film 102 disposed in the region where the driving transistor is disposed.

[0120] In this case, it is necessary to increase the capacitance to improve the charging rate of the storage capacitor Cst in the region where the driving transistor is located. Therefore, preferably, the thickness of the buffer 102a and the gate insulating film 102b located at the upper end of the driving transistor can be less than the thickness of the buffer 102a and the gate insulating film 102b located between the first signal line L1 and the overlapping line L2c.

[0121] Since the parasitic capacitance between the first signal line L1 and the overlapping line L2c increases as the thickness of the first insulating film 102 decreases, the thickness of the first insulating film 102 in the region overlapping with the first signal line L1 is greater than the thickness of the first insulating film 102 in the region overlapping with the driving transistor Tdr.

[0122] When the thickness of the first insulating film 102 increases, the length of the inclined surface M of the first insulating film can be increased. In this disclosure, the second signal line L2 is not formed on the inclined surface M of the first insulating film, which can reduce the parasitic capacitance on the lateral side of the first signal line L1.

[0123] like Figure 3 and Figure 6 As shown, some of the third panel electrodes disposed on the second insulating film 103 may be formed by the first pixel electrode for the light-emitting part EU.

[0124] The first pixel electrode can be either of the two electrodes constituting the light-emitting device (ED). For example, when the ED is an organic light-emitting diode (OLED), the OLED may include a first pixel electrode, a light-emitting layer disposed above the first pixel electrode, and a second pixel electrode disposed above the light-emitting layer. The first pixel electrode can be an anode, and the second pixel electrode can be a cathode. In this case, the first pixel electrode is connected to the driving transistor Tdr.

[0125] In other words, the first pixel electrode disposed on the second insulating film 103 can be electrically connected to a transistor disposed below the second insulating film 103. For example, the first pixel electrode can be electrically connected to a driving transistor Tdr disposed on the lower surface of the second insulating film through a contact hole in the second insulating film.

[0126] The bridging portion L2d can be covered by the dam portion 104, which is configured to form an opening through which the output light passes. The partition 105 can be additionally formed on the upper end of the bridging portion L2d of the dam portion 104.

[0127] A cathode 107 may be formed at the upper end of the embankment 104. A light-emitting layer 106 may be formed between the embankment 104 and the cathode 107. When a partition 105 is provided separately, the light-emitting layer 106 may be provided between the embankment 104 and the partition 105 and the cathode 107.

[0128] When the light-emitting device ED is an organic light-emitting diode (OLED), the OLED may include an anode, a light-emitting layer disposed above the anode, and a cathode disposed above the light-emitting layer. In this case, the anode may be patterned to be disposed in each of a plurality of pixels. The cathode 107 may be formed over the entire display area 120. Alternatively, the cathode 107 may be patterned to be disposed only in the area used for the anode. The light-emitting layer 106 may also be disposed over the entire surface of the display area 120. Alternatively, the light-emitting layer 106 may be patterned and formed only in the area corresponding to the anode. Figure 7A and Figure 7BIn this disclosure, a display panel including a light-emitting layer 106 disposed in a display area 120 of a substrate 101 is shown as an example of the present disclosure.

[0129] A dam 104 can be provided around the light-emitting portion EU. The dam 104 can define a light-emitting area. For example, light generated in the area of ​​the light-emitting portion EU not covered by the dam 104 (hereinafter referred to as an opening) can be output to the outside of the display panel. Therefore, the area in the display area 120 of the substrate 101 not covered by the dam 104 can be defined as a light-emitting area. The dam 104 can cover the bridging portion L2d.

[0130] The gap between the bridging portion L2d and the cathode 107 without the partition 105 is smaller than the gap between the bridging portion L2d and the cathode 107 with the partition 105.

[0131] If the gap between the bridging portion L2d and the cathode 107 decreases, parasitic capacitance may be generated between the bridging portion L2d and the cathode 107. Therefore, the RC load may increase in each of the bridging portion L2d and the cathode 107. Since the bridging portion L2d is formed of metal, parasitic capacitance may be generated between the metal-formed cathode 107 and the metal-formed bridging portion L2d. Therefore, the RC load may increase.

[0132] To prevent this situation, such as Figure 7B As shown, the partition 105 can be disposed between the embankment 104 and the cathode 107, and the partition 105 can overlap with the bridging portion L2d.

[0133] However, if the parasitic capacitance between the cathode 107 and the bridging portion L2d is small, then it can be as follows: Figure 7A As shown, no partition 105 is installed.

[0134] Figure 8 It is along Figure 3 Another cross-sectional view of A-A'. In the following description, references are omitted or briefly described. Figures 1 to 7B Descriptions that are identical or similar.

[0135] For reference Figures 1 to 7B The display panel according to this disclosure includes a substrate 101, a first signal line L1 disposed along a first direction of the substrate 101, a first insulating film 102 disposed on the substrate 101 and configured to cover the first signal line L1, a second signal line L2 disposed along a second direction different from the first direction, a second insulating film 103 configured to cover the first insulating film 102, and a first pixel electrode disposed on the second insulating film 103 and electrically connected to a transistor disposed on the first insulating film 102.

[0136] The second signal line L2 may include: an extension line L2a, which is disposed on a first side of the first signal line L1 relative to the first signal line L1 intersecting with the second signal line L2, and is disposed on the first insulating film 102; a connecting line L2b, which is disposed on a second side of the first signal line L1 and is disposed on the first insulating film 102; an overlapping line L2c, which is disposed on the first insulating film 102 and overlaps with the first signal line; and a bridging portion L2d disposed on the second insulating film. Furthermore, the bridging portion L2d can be connected to the extension line L2a, the connecting line L2b, and the overlapping line L2c through contact holes CH1 to CH4 disposed on the second insulating film 103.

[0137] A fifth contact hole CH5 can be formed on the second insulating film 103, through which the overlapping line L2c is exposed. The bridging portion L2d may include: a first bridge L2d1 connected to the extension line L2a through a first contact hole CH1 formed on the second insulating film 103 and connected to the overlapping line L2c through the fifth contact hole CH5; and a second bridge L2d2 connected to the connecting line L2b through a fourth contact hole CH4 formed on the second insulating film 103 and connected to the overlapping line L2c through the fifth contact hole CH5.

[0138] For example, in Figure 7A and 7B In the display panel shown, extension line L2a is connected to first bridge L2d1 through first contact hole CH1, first bridge L2d1 is connected to one side of overlapping line L2c through second contact hole CH2, the other side of overlapping line L2c is connected to second bridge L2d2 through third contact hole CH3, and second bridge L2d2 is connected to connecting line L2b through fourth contact hole CH4. Thus, the extension line L2a and connecting line L2b, which are separate from each other and have first signal line L1, can be electrically connected to each other.

[0139] However, in Figure 8 In the display panel shown, extension line L2a is connected to first bridge L2d1 through first contact hole CH1, first bridge L2d1 is connected to one side of overlapping line L2c through fifth contact hole CH5, the other side of overlapping line L2c is connected to second bridge L2d2 through fifth contact hole CH5, and second bridge L2d2 is connected to connecting line L2b through fourth contact hole CH4. Thus, the extension line L2a and connecting line L2b, which are separate from each other and have first signal line L1, can be electrically connected to each other.

[0140] exist Figure 7A and Figure 7B In the display panel shown, the first bridge L2d1 and the second bridge L2d2 are connected to the overlapping line L2c through different contact holes CH2 and CH3. However, in Figure 8In the display panel shown, the first bridge L2d1 and the second bridge L2d2 are connected to the overlapping line L2c through a contact hole, namely the fifth contact hole CH5.

[0141] Therefore, with Figure 7A and Figure 7B Compared to the display panel shown, in Figure 8 One contact hole can be reduced in the display panel shown. Furthermore, the first bridge L2d1 and the second bridge L2d2 are... Figure 7A and Figure 7B The planarization film 103b is positioned at the top of the display panel shown. However, in Figure 8 In the display panel shown, the overlapping line L2c is exposed through the fifth contact hole CH5, and the planarization film 103b is removed from the fifth contact hole CH5. Therefore, Figure 8 The spacing between the overlapping line L2c shown and the cathode 107 can be greater than [missing information]. Figure 7A and Figure 7B The spacing between the first bridge L2d1 / second bridge L2d2 and the cathode 107 is shown. Therefore, with Figure 7A and Figure 7B Compared to the display panel shown, the parasitic capacitance between the cathode 107 and the gate line used as the second signal line L2 can be reduced.

[0142] In the region of the first insulating film 102 where the first signal line L1 and the overlapping line L2c are provided, the overlapping line L2c, the extension line L2a and the connecting line L2b are not provided on the inclined surface M of the first insulating film that is inclined by the first signal line L1.

[0143] Therefore, parasitic capacitance caused by the overlap of the first signal line L1 and the second signal line L2 can be prevented or reduced in the inclined surface M of the first insulating film. Consequently, the RC load of the data voltage Vdata transmitted along the data line DL or the gate signal GS transmitted along the gate line GL can be reduced.

[0144] Furthermore, the thickness of the buffer 102a disposed at the upper end of the first signal line L1 can be greater than the thickness of the buffer disposed in the region where the driving transistor Tdr is disposed, thereby reducing the parasitic capacitance between the first signal line L1 and the overlapping line L2c. Therefore, the RC load of the data voltage Vdata transmitted along the data line DL or the gate signal GS transmitted along the gate line GL can be reduced.

[0145] Furthermore, the bridging portion L2d is covered by the dam portion 104, which is configured to form an opening through which light is output, and a partition 105 may be formed at the upper end of the bridging portion L2d of the dam portion 104. In this case, a cathode 107 may be disposed at the upper end of the dam portion 104, and a light-emitting layer 106 may be disposed between the dam portion 104 and the cathode 107.

[0146] In other words, in order to increase the gap between the bridging portion L2d and the cathode 107, a partition 105 can be provided between the dam portion 104 and the cathode 107, and the partition 105 can overlap with the bridging portion L2d, thereby reducing the RC load in the cathode 107 and the bridging portion L2d.

[0147] However, if the parasitic capacitance between the cathode and the bridging portion L2d is small, the partition 105 may not be required.

[0148] Figure 9 It is along Figure 3 Another cross-sectional view of A-A'. In the following description, references are omitted or briefly described. Figures 1 to 8 Descriptions that are identical or similar.

[0149] For reference Figures 1 to 8 The display panel according to this disclosure includes a substrate 101, a first signal line L1 disposed along a first direction of the substrate 101 and disposed on the substrate 101, a first insulating film 102 disposed on the substrate 101 and configured to cover the first signal line L1, a second signal line L2 disposed along a second direction different from the first direction, a second insulating film 103 configured to cover the first insulating film 102, and a first pixel electrode disposed on the second insulating film 103 and electrically connected to a transistor disposed on the first insulating film 102.

[0150] Reference Figures 1 to 8 The second signal line L2 may include: an extension line L2a, which is disposed on a first side of the first signal line L1 relative to the first signal line L1 intersecting with the second signal line L2, and disposed on the first insulating film 102; a connecting line L2b, which is disposed on a second side of the first signal line L1 and disposed on the first insulating film 102; an overlapping line L2c, which is disposed on the first insulating film 102 and overlaps with the first signal line; and a bridging portion L2d disposed on the second insulating film. Furthermore, the bridging portion L2d can be connected to the extension line L2a, the connecting line L2b, and the overlapping line L2c through contact holes CH1 to CH4 disposed on the second insulating film 103.

[0151] exist Figure 9 In the display panel shown, the second signal line L2 may include: an extension line L2a, which is disposed on a first side of the first signal line L1 relative to the first signal line L1 intersecting with the second signal line L2, and is disposed on the first insulating film 102; a connecting line L2b, which is disposed on a second side of the first signal line L1 and is disposed on the first insulating film 102; and a bridging portion L2d disposed on the second insulating film. Furthermore, the bridging portion L2d can be connected to the extension line L2a and the connecting line L2b through a contact hole disposed on the second insulating film 103.

[0152] The bridging portion L2d can be connected to the extension line L2a through the first contact hole CH1 formed on the second insulating film 103, and can be connected to the connecting line L2b through the fourth contact hole CH4 formed on the second insulating film 103.

[0153] exist Figure 9 In the display panel shown, extension line L2a is connected to bridging part L2d through first contact hole CH1, and bridging part L2d is connected to connecting line L2b through fourth contact hole CH4, thereby allowing the separate extension line L2a and connecting line L2b, which have first signal line L1, to be electrically connected to each other.

[0154] exist Figure 9 In the display panel shown, there is no overlapping line L2c, and the bridging part L2d is connected to the extension line L2a and the connecting line L2b through the first contact hole CH1 and the fourth contact hole CH4.

[0155] Therefore, with Figure 7A and Figure 7B Compared to the display panel shown, in Figure 9 Two contact holes can be reduced in the display panel shown. Furthermore, with... Figure 8 Compared to the display panel shown, in Figure 9 One contact hole can be reduced in the display panel shown. Furthermore, in... Figure 7A and Figure 7B and Figure 8 In the case of the display panel shown, in the overlapping area between the second signal line L2 and the first signal line L1, the overlapping line L2c is disposed at the upper end of the first insulating film 102. However, in Figure 9 In the case of the display panel shown, the bridging portion L2d is located at the upper end of the planarization film 103b. Therefore, Figure 9 The spacing between the first signal line L1 and the bridging part L2d shown can be greater than Figure 7A , Figure 7B and Figure 8 The spacing between the overlapping line L2c and the first signal line L1 is shown. Therefore, with Figure 7A , Figure 7B and Figure 8 Compared to the display panel shown, Figure 9 The display panel shown can reduce the parasitic capacitance between the first signal line L1 and the second signal line L2.

[0156] According to the aforementioned pre-disclosed content, in the region of the first insulating film 102 where the first signal line L1 is provided, the extension line L2a and the connecting line L2b are not provided on the inclined surface M of the first insulating film that is inclined by the first signal line L1.

[0157] Therefore, parasitic capacitance caused by the overlap of the first signal line L1 and the second signal line L2 can be prevented or reduced in the inclined surface M of the first insulating film. Consequently, the RC load of the data voltage Vdata transmitted along the data line DL or the gate signal GS transmitted along the gate line GL can be reduced.

[0158] Furthermore, the thickness of the buffer 102a disposed at the upper end of the first signal line L1 can be greater than the thickness of the buffer disposed in the region where the driving transistor Tdr is disposed, thereby reducing the parasitic capacitance between the first signal line L1 and the bridge portion L2d. Therefore, the RC load of the data voltage Vdata transmitted along the data line DL or the gate signal GS transmitted along the gate line GL can be reduced.

[0159] Furthermore, the bridging portion L2d is covered by the dam portion 104, which is configured to form an opening through which light is output, and a partition 105 may be formed at the upper end of the bridging portion L2d of the dam portion 104. In this case, a cathode 107 may be disposed at the upper end of the dam portion 104, and a light-emitting layer 106 may be disposed between the dam portion 104 and the partition 105 and the cathode 107.

[0160] In other words, in order to increase the gap between the bridging portion L2d and the cathode 107, a partition 105 can be provided between the dam portion 104 and the cathode 107, and the partition 105 can overlap with the bridging portion L2d, thereby reducing the RC load in the cathode 107 and the bridging portion L2d.

[0161] However, if the parasitic capacitance between the cathode and the bridging portion L2d is small, the partition 105 may not be required.

[0162] According to this disclosure, the overlap area between two intersecting signal lines can be reduced, thereby reducing the parasitic capacitance between the two intersecting signal lines.

[0163] In particular, according to this disclosure, the lateral surface of the first signal line disposed at the lower end of the two intersecting signal lines is not covered by the second signal line disposed at the upper end of the two intersecting signal lines, thereby reducing the parasitic capacitance between the two signal lines.

[0164] Therefore, the defects in image quality caused by RC load can be reduced in this disclosure.

[0165] The features, structures, and effects described above in this disclosure are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, content associated with combinations and modifications should be interpreted as being within the scope of this disclosure.

[0166] It will be apparent to those skilled in the art that various modifications and variations may be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A display panel, comprising: substrate; A first signal line is disposed along a first direction of the substrate and on the substrate; A first insulating film is disposed on the substrate and covers the first signal line; A second signal line disposed along a second direction different from the first direction; A second insulating film covering the first insulating film; as well as A first pixel electrode is disposed on the second insulating film and electrically connected to a transistor disposed on the first insulating film. The second signal line includes: An extension line is disposed on a first side of the first signal line relative to the first signal line intersecting with the second signal line, and is disposed on the first insulating film; A connecting wire, wherein the connecting wire is disposed on the second side of the first signal line and on the first insulating film; Overlapping lines, wherein the overlapping lines are disposed on the first insulating film and overlap with the first signal lines; and A bridging portion is disposed on the second insulating film and connected to the extension line, the connecting line and the overlapping line through a contact hole disposed on the second insulating film.

2. The display panel according to claim 1, wherein, The first signal line is a data line, and the second signal line is a gate line.

3. The display panel according to claim 1, wherein, The bridging portion includes: The first bridge connecting the extension line and the overlapping line; and A second bridge connected to the connecting line and the overlapping line.

4. The display panel according to claim 3, in, The first bridge is connected to the extension line through a first contact hole provided on the second insulating film, and is connected to the overlapping line through a second contact hole provided on the second insulating film. The second bridge is connected to the connecting line through a fourth contact hole provided on the second insulating film, and is connected to the overlapping line through a third contact hole provided on the second insulating film.

5. The display panel according to claim 1, in, A fifth contact hole is provided on the second insulating film to expose the overlapping lines; and The bridging portion includes: A first bridge, the first bridge being connected to the extension line via a first contact hole disposed on the second insulating film and connected to the overlapping line via the fifth contact hole; and The second bridge is connected to the connecting line through a fourth contact hole provided on the second insulating film and to the overlapping line through the fifth contact hole.

6. The display panel according to claim 5, wherein, The first bridge and the second bridge are connected to or separated from each other on the upper surface of the overlapping line.

7. The display panel according to claim 1, wherein, In the region of the first insulating film where the first signal line and the overlapping line are provided, the overlapping line, the extension line, and the connecting line are not provided on the inclined surface of the first insulating film that is inclined by the first signal line.

8. The display panel according to claim 1, in, The light-emitting layer is disposed above the first pixel electrode, and The second pixel electrode is disposed at the upper end of the light-emitting layer.

9. The display panel according to claim 1, in, The bridging portion is covered by a dam portion, the dam portion including an opening for outputting light. A partition is disposed at the upper end of the bridging portion of the embankment. The cathode is disposed at the upper end of the dike, and The light-emitting layer is disposed between the embankment / the partition and the cathode.

10. The display panel according to claim 1, wherein, The thickness of the first insulating film between the first signal line and the overlapping line is greater than the thickness of the first insulating film in the region where the transistor is disposed.

11. A display panel, comprising: substrate; A first signal line is disposed along a first direction of the substrate and on the substrate; A first insulating film is disposed on the substrate and covers the first signal line; A second signal line disposed along a second direction different from the first direction; A second insulating film covering the first insulating film; as well as A first pixel electrode is disposed on the second insulating film and electrically connected to a transistor disposed on the first insulating film. The second signal line includes: An extension line is disposed on a first side of the first signal line relative to the first signal line intersecting with the second signal line, and is disposed on the first insulating film; A connecting wire, wherein the connecting wire is disposed on the second side of the first signal line and disposed on the first insulating film; and A bridging portion is disposed on the second insulating film and connected to the extension line and the connecting line through a contact hole disposed on the second insulating film.

12. The display panel according to claim 11, in, The bridging portion is connected to the extension line through a first contact hole provided on the second insulating film, and is connected to the connecting line through a fourth contact hole provided on the second insulating film.

13. The display panel according to claim 11, in, The bridging portion is covered by a dam portion, the dam portion including an opening for outputting light. A partition is disposed at the upper end of the bridging portion of the embankment. The cathode is disposed at the upper end of the dike, and The light-emitting layer is disposed between the embankment / the partition and the cathode.

14. The display panel according to claim 11, wherein, The first signal line is a data line, and the second signal line is a gate line.

15. The display panel according to claim 11, wherein, In the region of the first insulating film where the first signal line is located, the extension line and the connecting line are not located on the inclined surface of the first insulating film that is inclined by the first signal line.

16. The display panel according to claim 11, wherein, The thickness of the first insulating film disposed at the upper end of the first signal line is greater than the thickness of the first insulating film in the region where the transistor is disposed.

17. A display panel, comprising: substrate; A first signal line is disposed along a first direction of the substrate and on the substrate; A first insulating film is disposed on the substrate and covers the first signal line; A second signal line disposed along a second direction different from the first direction; as well as A second insulating film covering the first insulating film; The second signal line includes: A plurality of separate lines disposed on the first insulating film; and A bridging portion is disposed on the second insulating film, wherein the bridging portion is connected to the plurality of wires through contact holes disposed on the second insulating film. The first signal line is a data line, and the second signal line is a gate line.

18. The display panel according to claim 17, wherein, The plurality of lines includes: an extension line disposed on a first side of the first signal line relative to the first signal line intersecting with the second signal line; a connecting line disposed on a second side of the first signal line; and an overlapping line overlapping the first signal line; or The plurality of lines include: an extension line disposed on a first side of the first signal line relative to the first signal line intersecting with the second signal line; and a connecting line disposed on a second side of the first signal line.

19. A display device, comprising: Display panel according to any one of claims 1-18; A data driver configured to provide data voltage to data lines disposed in the display panel; A gate driver configured to provide a gate voltage to a gate line disposed in the display panel; as well as A controller configured to control the data driver and the gate driver.

Images