Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods for forming semiconductor structures are provided. A semiconductor structure includes a substrate and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure also includes a gate layer including a first portion through the second layer and a second portion extending between the first layer and the second layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component or line that can be created using manufacturing processes) has decreased.

[0003] However, as component sizes continue to shrink, manufacturing processes continue to become more difficult to implement, and the critical dimensional uniformity of components (or lines) continues to become more difficult to control. For example, complex operations may require more photomasks, leading to higher costs and consequently lower yields. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a substrate; a dielectric stack above the substrate, the dielectric stack including: a first layer above the substrate; and a second layer above the first layer; a gate layer inserted into the dielectric stack and including a first portion and a second portion, wherein the first portion extends from top to bottom through the second layer, and wherein the second portion extends laterally between the first layer and the second layer to be located above the first layer and below the second layer; and a semiconductor channel layer conforming to the outline of the gate layer and enclosing the second portion to separate the second portion from the dielectric stack.

[0005] Other embodiments of this application provide a semiconductor structure including: a substrate; a dielectric stack above the substrate, the dielectric stack including: a first layer above the substrate; and a second layer above the first layer; a gate layer extending from top to bottom through the dielectric stack and having a cross-shaped profile; and a first high-k material in direct contact with the bottom surface of the second layer and separating the gate layer from the dielectric stack.

[0006] Further embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first layer over a substrate, wherein the first layer comprises a first material; forming a sacrificial layer over the first layer, wherein the sacrificial layer comprises a second material different from the first material; forming a second layer over the sacrificial layer; forming a first recess to expose sidewalls of the sacrificial layer; laterally removing a portion of the sacrificial layer from the sidewalls; and forming a gate material in the first recess, wherein the gate material is located below the second layer and above the first layer. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a schematic diagram showing a three-dimensional view of a semiconductor structure according to some embodiments of the present invention.

[0009] Figure 1B Some embodiments according to the present invention are shown. Figure 1A A magnified partial schematic diagram of part X of the semiconductor device.

[0010] Figure 1B' Some other embodiments according to the present invention are shown. Figure 1A A magnified partial schematic diagram of part X of the semiconductor device.

[0011] Figure 1B "This illustrates some other embodiments according to the present invention." Figure 1A A magnified partial schematic diagram of part X of the semiconductor device.

[0012] Figure 1C Some embodiments according to the present invention are shown. Figure 1A A cross-sectional view of the reference section C1-C1 of the semiconductor device.

[0013] Figure 1D Some embodiments according to the present invention are shown. Figure 1A A cross-sectional view of the reference section C2-C2 of the semiconductor device.

[0014] Figure 1E Some embodiments according to the present invention are shown. Figure 1A A cross-sectional view of the reference section C3-C3 of the semiconductor device.

[0015] Figure 2 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention is shown.

[0016] Figures 3 to 9 This is a cross-sectional view of a semiconductor structure during an intermediate stage of the manufacturing operation according to some embodiments of the present invention.

[0017] Figure 10A This is a schematic diagram illustrating a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention.

[0018] Figure 10B Some embodiments according to the present invention are shown. Figure 10A A cross-sectional view of the reference section C4-C4 of the semiconductor device.

[0019] Figure 10C Some embodiments according to the present invention are shown. Figure 10A The cross-sectional view of the reference section C5-C5 of the semiconductor device.

[0020] Figure 10D Some embodiments according to the present invention are shown. Figure 10A A cross-sectional view of the reference section C6-C6 of the semiconductor device.

[0021] Figure 11A This is a schematic diagram illustrating a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention.

[0022] Figure 11B Some embodiments according to the present invention are shown. Figure 11A A cross-sectional view of the reference section C7-C7 of the semiconductor device.

[0023] Figure 11C Some embodiments according to the present invention are shown. Figure 11A A cross-sectional view of the reference section C8-C8 of the semiconductor device.

[0024] Figure 11D Some embodiments according to the present invention are shown. Figure 11A A cross-sectional view of the reference section C9-C9 of the semiconductor device.

[0025] Figure 12 This is a schematic diagram illustrating a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. Detailed Implementation

[0026] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0028] While the numerical ranges and parameters illustrating the broad scope of the invention are approximate, the values ​​described in specific examples are reported as precisely as possible. However, any numerical value inherently contains some errors, which are necessarily caused by the standard deviation found in the corresponding test measurements. Moreover, as used herein, the terms “substantially,” “about,” or “approximately” generally refer to a value or range that can be considered by one of ordinary skill in the art. Alternatively, the terms “substantially,” “about,” or “approximately” mean within an acceptable standard error of the average value as considered by one of ordinary skill in the art. One of ordinary skill in the art will understand that acceptable standard errors can vary depending on the technology. Except in operational / working examples, or unless expressly stated otherwise, all reference ranges, quantities, values, and percentages disclosed herein (such as those for material quantities, durations, temperatures, operating conditions, ratios of quantities, etc.) should be understood to be modified in all cases by the terms “substantially,” “about,” or “approximately.” Therefore, unless indicated to the contrary, the reference parameters set forth in the invention and the appended claims are approximate values ​​that can be varied as needed. At a minimum, each reference parameter should be interpreted based on the number of significant figures reported and by applying ordinary rounding techniques. A range may be expressed in this document as a distance from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise stated.

[0029] Memory devices are widely used in a variety of applications, including data storage, data transmission, networking, computing, and more. Advanced applications, such as 5G mobile networks or artificial intelligence, require memory devices with higher speeds, higher device density, lower latency, and higher bandwidth. However, the trend towards shrinking semiconductor device geometry faces challenges related to complex manufacturing operations (such as complex photolithography operations that rely on numerous photomasks) and the resulting costs.

[0030] This invention provides a semiconductor structure and a method for manufacturing the semiconductor structure to solve the aforementioned problems. For example, compared with other methods, manufacturing can be simplified and the amount of photolithography stages can be reduced. Furthermore, by increasing the device channel area, speed and / or device performance can be improved.

[0031] refer to Figure 1A and Figure 1B , Figure 1A This is a schematic diagram illustrating a perspective view of a semiconductor structure according to some embodiments of the present invention, and Figure 1B Some embodiments according to the present invention are shown. Figure 1A This is a partially enlarged schematic diagram of portion X of a semiconductor device. The semiconductor device 100 may include a substrate 101, a dielectric stack 110 above the substrate 101, a gate layer 121 in the dielectric stack 110, and conductive components 131A and 132A in the dielectric stack 110. In some embodiments, the substrate 101 comprises silicon. Optionally or additionally, the substrate 101 comprises: another material, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or gallium arsenide indium phosphide (GaInAsP); or combinations thereof. In some other embodiments, the substrate 101 comprises one or more group III-V materials, one or more group II-IV materials, or combinations thereof. In some alternative embodiments, the substrate 101 may be undoped. In some other embodiments, substrate 101 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In some other embodiments, substrate 101 may include active regions.

[0032] The dielectric stack 110 may include an insulating material. In some embodiments, the dielectric stack 110 may include a dielectric material having portions formed at different stages. In some embodiments, the dielectric stack 110 may include a multilayer composition, such as a first layer 111, a second layer 113 above the first layer 111, and a spacer layer 112 having portions located between the first layer 111 and the second layer 113. In some embodiments, the first layer 111 and the second layer 113 may include oxides. In some embodiments, the material of the first layer 111 may be similar to the material of the second layer 113. In some embodiments, the material of the spacer layer 112 may include an oxide-based material. In some cases, the material of the spacer layer 112 may be similar to or substantially the same as the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of the spacer layer 112 may be different from the first layer 111 and / or the second layer 113. For example, the material of the spacer layer 112 may include other oxide-based materials, silicon nitride (SiN), silicon germanium (SiGe), or other insulating / film materials.

[0033] refer to Figure 1B' , Figure 1B' Some embodiments according to the present invention are shown. Figure 1A A magnified partial schematic diagram of part X of the semiconductor device. Figure 1B' Some of the alternative embodiments shown are similar to Figure 1B The discussion in [the previous section] is similar, but the difference lies in that the material of spacer layer 112 is the same as the materials of the first layer 111 and the second layer 113. For example, the same material (such as an oxide-based material) is used as the material of the first layer 111 and the second layer 113 (as will be discussed in [the previous section]). Figure 3 (discussed in the middle) and used to fill the gap between two adjacent gate layers 121 (as will be discussed in the middle) Figures 8 to 9 (Discussed in the following section). When the material of spacer layer 112 is the same as that of the first layer 111 and the second layer 113, their layers can be formed at different stages, which is subsequently... Figures 2 to 12 The following discussion will be held. In some embodiments, the materials of the first layer 111, the second layer 113, and the spacer layer 112 may be combined or integrated.

[0034] refer to Figure 1B " Figure 1B "This illustrates some embodiments according to the present invention" Figure 1A A magnified partial schematic diagram of part X of the semiconductor device. Figure 1B Some of the alternative embodiments shown are similar to Figure 1B or Figure 1B' The discussion in [the previous section] differs in that the material of spacer layer 112 is different from the materials of the first layer 111 and the second layer 113, wherein a portion of spacer layer 112 is not covered by the second layer 113. In some embodiments, the material of spacer layer 112 may include an oxide-based material. In some cases, the material of spacer layer 112 may be similar to the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of spacer layer 112 may be different from the first layer 111 and / or the second layer 113. For example, the material of spacer layer 112 may include other oxide-based materials, silicon nitride (SiN), silicon germanium (SiGe), or another insulating / film material.

[0035] refer to Figure 1A In some embodiments, the width WB of the spacer layer 112 along the main direction PD may be smaller than the width WA of the first layer 111 or the width WC of the second layer 113.

[0036] Semiconductor device 100 may include a plurality of gate layers 121 spaced apart on a predominant direction PD. The gate layers 121 may include a conductive material, such as tungsten (W). The gate layers 121 may have a cross-shaped / intersecting shape in a cross-sectional view (e.g., Figure 1A , Figure 1B , Figure 1B' or Figure 1B (as shown in the diagram), and each of the gate layers 121 extends along a secondary direction SD that is substantially perpendicular to the primary direction PD.

[0037] refer to Figure 1B , Figure 1B' and Figure 1B The gate layer 121 may include a first portion 121A extending through the second layer 113, a second portion 121B extending between the first layer 111 and the second layer 113, and a third portion 121C located in the first layer 111 and close to the substrate 101. Viewed from above (along the third direction TD), the second portion 121B may overlap with the first layer 111 and the second layer 113. In some embodiments, the first portion 121A of the gate layer 121 may be exposed from the dielectric stack 110.

[0038] The semiconductor device 100 may further include a first high-k material 122, a channel layer 123, and a second high-k material 122' located between the gate layer 121 and the dielectric stack 110. The second high-k material 122' conforms to the outer contour of the outer sidewall and bottom surface of the gate layer 121. The channel layer 123 conforms to the outer contour of the second high-k material 122'. The first high-k material 122 conforms to the outer contour of the channel layer 123. In other words, the channel layer 123 is located between the first high-k material 122 and the second high-k material 122'. The first high-k material 122, the channel layer 123, and the second high-k material 122' extend along the secondary direction SD.

[0039] The first high-k material 122 may include a material suitable for use as a dipole layer, such as, for example, hafnium zirconium oxide (HfZrO; for example, Hf...). x Zr x O y Other hafnium-zirconium-based materials or ferroelectric materials. The first high-k material 122 can be used as a dipole layer for changing the state of the channel memory. The second high-k material 122' can include materials different from the first high-k material 122, such as, for example, hafnium oxide (e.g., HfO) or other materials suitable for enhancing channel carrier performance. For example, HfO can provide oxide vacancies for enhancing channel carrier performance.

[0040] The first high-k material 122 can be in direct contact with the bottom surface BS of the second layer 113, the top surface TS of the first layer 111, and the sidewall SW1 of the spacer layer 112. In some embodiments, the width W1 measured from the sidewall of the first high-k material 122 adjacent to the sidewall SW1 of the spacer layer 112 to the sidewall SW2 of the spacer layer 112 near the first portion 121A of the gate layer 121 (or the sidewall SW3 of the spacer layer 112 near the third portion 121C of the gate layer 121) can be in the range of about 30 nm to 90 nm. With a width smaller than the above range, device performance may be lower than expected due to the reduced device channel area. With a width larger than the above range, control-related operations (e.g., in...) may be affected. Figure 4 The difficulty of the lateral pull-back operation discussed in the text may undesirably increase. In some embodiments, the depth T1 measured from the surface of the first high-k material 122 adjacent to the bottom surface BS of the second layer 113 to another surface of the first high-k material 122 adjacent to the top surface TS of the first layer 111 can be in the range of about 50 nm to 80 nm. With a depth less than the above range, the device performance may be lower than expected due to the reduced device channel area, or the difficulty of forming the gate layer 121 may increase. With a depth greater than the above range, the entire height of the semiconductor device 100 along the third direction TD may be too large, making it difficult to meet the requirements for device size reduction.

[0041] With this configuration, the second portion 121B of the gate layer 121 can have substantially vertical sidewalls and in a cross-sectional view (e.g.) Figure 1B , Figure 1B' or Figure 1B The device channel area (as shown in the diagram) is configured to resemble a quadrilateral, rectangle, or square. Therefore, compared to a comparative embodiment with a curved profile, the device channel area can be increased, thereby improving device performance (such as processing speed). In some embodiments, the first angle θ1 between the sidewall of spacer layer 112 and the bottom surface BS of second layer 113 can be in the range of about 80 degrees to about 90 degrees. Similarly, the second angle θ2 between the sidewall SW2 of the first portion 121A of second layer 113 near gate layer 121 and the bottom surface BS of second layer 113 can be in the range of about 80 degrees to about 90 degrees. When the angle is greater than or less than the above range, defects may occur; the formation of the first high-k material 122, channel layer 123, and second high-k material 122' may be difficult, or the device channel region may be too small.

[0042] refer to Figure 1A , Figure 1C , Figure 1D and Figure 1E According to some embodiments of the present invention, Figure 1C It shows Figure 1A A cross-sectional view of the reference section C1-C1 of the semiconductor device. Figure 1D It shows Figure 1A A cross-sectional view of the reference section C2-C2 of the semiconductor device, and Figure 1E It shows Figure 1A A cross-sectional view of the semiconductor device at reference section C3-C3. The semiconductor device 100 may further include conductive components 131A and 132A embedded in the dielectric stack 110 and between a pair of gate layers 121. Conductive components 131A and 132A pass through the second layer 113 and the spacer layer 112. In some embodiments, conductive component 131A may constitute a source layer and conductive component 132A may constitute a drain layer. In some embodiments, conductive components 131A and 132A may comprise a conductive material, such as tungsten (W). It should be noted that although... Figure 1A and Figure 1C Only two conductive components 131A and one conductive component 132A are shown in the diagram, but the invention is not limited thereto. The semiconductor device 100 may include multiple rows of conductive components 131A and 132A located between other pairs of gate layers 121, or may have one or more conductive components 131A and 132A between two gate layers 121.

[0043] like Figure 1D or Figure 1E As shown, the bottom surface BS' of conductive component 131A (or conductive component 132A) is located at a horizontal plane lower than the horizontal plane of the top surface TS of the first layer 111. In some embodiments, portions of conductive components 131A and 132A may be laterally surrounded by the first layer 111. For example, the depth D1 measured from the bottom surface BS' of conductive component 131A (or conductive component 132A) to the surface of the first high-k material 122 adjacent to the top surface TS of the first layer 111 can range from about 20 nm to about 30 nm. This configuration can increase the contact area between the first high-k material 122 and the conductive component 131A (or conductive component 132A). When the depth D1 is less than 20 nm or the top surface TS of the first layer 111 is above the bottom surface BS' of the conductive component 131A (or conductive component 132A), the overall contact area between the first high-k material 122 and the conductive component 131A (or conductive component 132A) may be reduced, the etching operation may be difficult to control, or the reliability may be affected. When the depth D1 is greater than 30nm, reliability (such as the characteristics of the first layer 111) may be affected.

[0044] The semiconductor device 100 also includes an insulating layer 130 above the dielectric stack 110 and interconnect structures disposed in the dielectric stack 110. The interconnect structures may include first conductive vias 131B electrically connected to each of the conductive components 131A and second conductive vias 132B electrically connected to each of the conductive components 132A. In some embodiments, the semiconductor device 100 further includes a conductive path 133 disposed in the insulating layer 130 and connected to the gate layer 121. In some embodiments, the conductive path 133 constitutes a word line. In some embodiments, the first conductive vias 131B, the second conductive vias 132B, and the conductive path 133 may include a conductive material, such as copper.

[0045] refer to Figure 2 , Figure 2 A flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention is shown. Method 1000 for manufacturing a semiconductor device includes: forming a first layer over a substrate (operation 1004, see example...). Figure 3 A sacrificial layer is formed above the first layer (operation 1007, see example). Figure 3 A second layer is formed above the sacrificial layer (operation 1013, see example). Figure 3 ); Form a first groove to expose the sidewalls of the sacrificial layer (operation 1018, see example) Figure 4 ); forming a high-k material conforming to the profile of the first groove (operation 1022, see example) Figure 5 ); and forming a gate material in the first recess (operation 1027, see example) Figure 6 ).

[0046] refer to Figure 3 , Figure 3 This is a cross-sectional view of a semiconductor structure during an intermediate stage of the manufacturing operation according to some embodiments of the present invention. A substrate 101 is provided. Details regarding the substrate 101 can be found in [reference needed]. Figure 1A A first layer 111 is formed over a substrate 101, wherein the first layer 111 may include an insulating material. In some embodiments, the first layer 111 may include an oxide-based material or other suitable material. A sacrificial layer 112S is formed over the first layer 111, wherein the material of the sacrificial layer 112S is different from the material of the first layer 111. For example, the sacrificial layer 112S may include a thin film material such as silicon nitride (SiN), silicon germanium (SiGe), etc. A second layer 113 is formed over the sacrificial layer 112S, wherein the material of the second layer 113 is different from the material of the sacrificial layer 112S. In some embodiments, the material of the second layer 113 may be the same as or similar to the material of the first layer 111, such as an oxide-based material or other suitable insulating material.

[0047] refer to Figure 4 , Figure 4 This is a cross-sectional view of a semiconductor structure during an intermediate stage of a manufacturing operation according to some embodiments of the present invention. The implementation may include dicing operations of etching and photolithography to remove portions of the first layer 111, the sacrificial layer 112S, and the second layer 113, thereby forming a plurality of first recesses R1. In an alternative embodiment, only one first recess R1 is formed. The sidewalls of the sacrificial layer 112S are exposed at the sidewalls of each of the first recesses R1. In some embodiments, portions of the substrate 101 are exposed after the etching and photolithography operations. In some embodiments, the etching operation may be an anisotropic etching operation. In some embodiments, the photolithography operation may include utilizing a photomask.

[0048] A lateral pull-back operation is performed to enlarge each of the first recesses R1 by removing portions of the sacrificial layer 112S. In some embodiments, portions of the sacrificial layer 112S are removed from the sidewalls of the first recesses R1 by a selective etching operation, which may include applying a suitable chemical substance over the substrate 101. For example, in the case of a material having silicon nitride as the sacrificial layer 112S, phosphoric acid (H3PO4) or another suitable chemical substance with an elevated temperature (e.g., approximately 170°C) may be applied over the substrate 101 to laterally remove portions of the sacrificial layer 112S. In another example, in the case of a material having silicon germanium as the sacrificial layer 112S, fluorine gas (F2) or another suitable chemical substance may be applied over the substrate 101 to laterally remove portions of the sacrificial layer 112S. The amount of sacrificial layer 112S removed in the lateral pull-back operation can be controlled by time calculations.

[0049] By utilizing a lateral pull-back operation, portions of the bottom surface of the second layer 113 and the top surface of the first layer 111 can be exposed and revealed through the sacrificial layer 112S. Furthermore, after the lateral pull-back operation, the remaining sacrificial layer 112S can have substantially vertical sidewalls SW', and from a cross-sectional view, the first groove R1 can have a cross-shaped / intersecting shape. Similar to... Figures 1A to 1E The discussion in the paper indicates that the lateral etch depth W1' of the lateral pull-back operation can be in the range of approximately 30 nm to 90 nm. With lateral etch depths smaller than this range, device performance may be lower than expected due to the reduced device channel area. With lateral etch depths larger than this range, the difficulty of controlling the related operations may undesirably increase, or in some cases, defects may occur due to over-etching.

[0050] refer to Figure 3 and Figure 4The thickness T1' of the sacrificial layer 112S can be in the range of approximately 50 nm to 80 nm. With a thickness smaller than this range, device performance may be lower than expected due to the reduced device channel area, or the difficulty of lateral pull-back operations may increase due to the higher aspect ratio. With a thickness greater than this range, the entire height of the semiconductor device along the third direction TD may be too large, and therefore may be difficult to meet the requirements for device size reduction.

[0051] In addition, the angle at the corner of the second layer 113 (corresponding to) Figure 1B , Figure 1B' or Figure 1B The second angle θ2 shown can range from about 80 degrees to about 90 degrees. Furthermore, the angle at the corner between the sidewall SW' of the remaining sacrificial layer 112S and the exposed bottom surface of the second layer 113 (corresponding to...) Figure 1B , Figure 1B' or Figure 1B The first angle θ1 shown can be in the range of about 80 degrees to about 90 degrees. If either angle is greater than or less than the above range, defects may occur, and the subsequent formation of the first high-k material 122, the channel layer 123, and the second high-k material 122' may be difficult (as will be...). Figures 5 to 6 (Discussed in the middle), or the device channel region may be too small.

[0052] refer to Figure 5 , Figure 5 This is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present invention. A first high-k material 122 is formed to conform to the profile of a first recess R1. In some embodiments, the first high-k material 122 also covers the top surface of the second layer 113. In some embodiments, the first high-k material 122 may be in direct contact with an exposed portion of the substrate 101. The first high-k material 122 may include a material suitable for use as a dipole layer, such as, for example, hafnium zirconium oxide (HfZrO; for example, Hf...). x Zr x O y Other hafnium-zirconium-based materials or ferroelectric materials. A channel layer 123 is formed over the first high-k material 122, wherein the channel layer 123 conforms to the contour of the first high-k material 122 (and the contour of the first groove R1).

[0053] A second high-k material 122' is formed above the channel layer 123, wherein the second high-k material 122' conforms to the contour of the channel layer 123 (and the contour of the first groove R1). The second high-k material 122' may include a material different from the first high-k material 122, such as, for example, hafnium oxide (e.g., HfO) or other materials suitable for enhancing channel carrier performance. For example, HfO can provide oxide vacancies for enhancing channel carrier performance.

[0054] The profile of the first groove R1 formed by the lateral pull-back operation can facilitate the formation of the first high-k material 122, the channel layer 123, and the second high-k material 122', and can provide sufficient device channel area to improve device performance.

[0055] refer to Figure 6 , Figure 6 This is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present invention. Above the second high-k material 122' and the first recess R1 (e.g.) Figure 5 A gate material 121M is formed in the (shown). The gate material 121M may include a conductive material, such as tungsten (W).

[0056] refer to Figure 7 , Figure 7 This is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present invention. A planarization operation, such as chemical mechanical planarization (CMP), can be performed from the top surface of the gate material 121M to remove excess portions of the gate material 121M, the first high-k material 122, the channel layer 123, and the second high-k material 122'. The top surface of the second layer 113 is exposed by the planarization operation, and the remaining gate material 121M thereby forms the gate layer 121. The top surfaces of the gate layer 121, the second layer 113, the first high-k material 122, the channel layer 123, and the second high-k material 122' can be coplanar. As previously stated in... Figures 1A to 1E As discussed in the cross-sectional view, the gate layer 121 may have a cross-shaped / intersecting shape, which includes a first portion 121A that passes through the second layer 113, a second portion 121B that extends between the first layer 111 and the second layer 113, and a third portion 121C that is located in the first layer 111 and close to the substrate 101.

[0057] refer to Figure 8 , Figure 8This is a cross-sectional view of a semiconductor structure during an intermediate stage of the manufacturing operation according to some embodiments of the present invention. In some embodiments, the remaining sacrificial layer 112S and the portion of the second layer 113 above the remaining sacrificial layer 112S can be removed by an etching operation, thereby forming a plurality of second recesses R2. In alternative embodiments, only one second recess R2 is formed. In some embodiments, the entire remaining sacrificial layer 112S is removed. In some embodiments, the etching operation can be controlled by time calculation. In some embodiments, a portion of the first layer 111 can be etched from its top surface. In some alternative embodiments, a portion of the sacrificial layer 112S can be retained.

[0058] refer to Figure 9 , Figure 9 This is a cross-sectional view of a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present invention. The material of the spacer layer 112 and / or the second layer 113 may be formed in the second recess R2 (e.g., Figure 8 As shown in some embodiments, such as Figure 1B As discussed, spacer layer 112 and a second layer 113 above the spacer layer are formed in the second groove R2. In some embodiments, the material of spacer layer 112 may include an oxide-based material. In some cases, the material of spacer layer 112 may be similar to or substantially the same as the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of spacer layer 112 may be different from the first layer 111 and / or the second layer 113. For example, the material of spacer layer 112 may include other oxide-based materials, silicon nitride (SiN), silicon germanium (SiGe), or another insulating / film material. In some embodiments, planarization operations (such as CMP) may be performed to remove excess material.

[0059] In some alternative embodiments, reference Figure 1B' The spacer layer 112 is made of the same material as the first layer 111 and the second layer 113, and this material fills the second groove R2. In some embodiments, a planarization operation (such as CMP) may be performed to remove excess material.

[0060] In some alternative embodiments, reference Figure 1BThe material of spacer layer 112 is different from the materials of the first layer 111 and the second layer 113, and spacer layer 112 is formed in the second groove R2. In some cases, the material of spacer layer 112 may be similar to the material of the first layer 111 or the second layer 113. In some alternative embodiments, the material of spacer layer 112 may be different from the first layer 111 and / or the second layer 113. For example, the material of spacer layer 112 may include another oxide-based material, silicon nitride (SiN), silicon germanium (SiGe), or some other insulating / film material. In some embodiments, planarization operations (such as CMP) may be performed to remove excess material, and spacer layer 112 may have a surface exposed and revealed by the second layer 113.

[0061] By filling the second groove R2, the first layer 111, the second layer 113, and the spacer layer 112 thereby constitute the dielectric stack 110.

[0062] refer to Figure 10A , Figure 10B , Figure 10C and Figure 10D According to some embodiments of the present invention, Figure 10A This is a schematic diagram illustrating the semiconductor structure during an intermediate stage of the manufacturing process. Figure 10B It shows Figure 10A A cross-sectional view of the reference section C4-C4 of the semiconductor device. Figure 10C It shows Figure 10A A cross-sectional view of the reference section C5-C5 of the semiconductor device, and Figure 10D It shows Figure 10A A cross-sectional view of the semiconductor device at reference section C6-C6. Multiple third recesses R131 and fourth recesses R132 may be formed in the dielectric stack 110. In an alternative embodiment, only one third recess R131 is formed, and multiple fourth recesses R132 are formed. In an alternative embodiment, multiple third recesses R131 and multiple fourth recesses R132 are alternately formed in the secondary direction SD.

[0063] At least a portion of the sidewall SW4 of the first high-k material 122 (which may be close to the second portion 121B of the gate layer 121) is exposed from the third recess R131 and the fourth recess R132. In some embodiments, the formation of the third recess R131 and the fourth recess R132 may include photolithography and / or etching operations. The etching operation can be controlled by time calculation. In some embodiments, the bottom surfaces of the third recess R131 and the fourth recess R132 are located at a horizontal plane at a distance D1' lower than the horizontal plane of the interface INT between the top surface of the first layer 111 and the first high-k material 122. For example, the bottom surfaces of the third recess R131 and the fourth recess R132 may be located at a horizontal plane in the range of about 20 nm to about 30 nm below the top surface of the first layer 111 (or the interface INT).

[0064] refer to Figure 11A , Figure 11B , Figure 11C and Figure 11D According to some embodiments of the present invention, Figure 11A This is a schematic diagram illustrating the semiconductor structure during an intermediate stage of the manufacturing process. Figure 11B It shows Figure 11A A cross-sectional view of the reference section C7-C7 of the semiconductor device. Figure 11C It shows Figure 11A A cross-sectional view of the reference section C8-C8 of the semiconductor device, and Figure 11D Show Figure 11A A cross-sectional view of the semiconductor device at reference section C9-C9. In some embodiments, conductive components 131A and 132A may be formed in the third recess R131 and the fourth recess R132, respectively, wherein conductive components 131A and 132A comprise a conductive material, such as tungsten (W). Conductive components 131A and 132A may be in direct contact with the first high-k material 122 (corresponding to two adjacent gate layers 121) on two opposite sides at the sidewalls SW4 where they intersect each other in the main direction PD. In some embodiments, conductive component 131A may constitute the source layer, and conductive component 132A may constitute the drain layer.

[0065] refer to Figure 12 , Figure 12This is a schematic diagram illustrating a semiconductor structure during an intermediate stage of manufacturing operations according to some embodiments of the present invention. An insulating layer 130 is formed over a dielectric stack 110, and interconnect structures are formed in the dielectric stack 110. In some embodiments, the formation of the interconnect structures may include photolithography and etching operations. The interconnect structures may include a first conductive via 131B electrically connected to each of conductive components 131A and a second conductive via 132B electrically connected to conductive components 132A. In some embodiments, the semiconductor device 100 further includes a conductive path 133 disposed in the insulating layer 130 and connected to the gate layer 121. In some embodiments, the conductive path 133 constitutes a word line. The first conductive via 131B, the second conductive via 132B, and the conductive path 133 may include a conductive material, such as copper.

[0066] This invention provides a semiconductor structure that can be used in memory device applications. Specifically, this invention provides a gate layer 121 having a basic cross-shaped / intersecting shape when viewed in cross-sectional view (e.g., Figures 1A to 1E and Figure 12 (As shown in the diagram). Due to the shape of the gate layer 121, the total contact area between the high-k layer and the channel layer (and the contact area between the second high-k material 122' and the gate layer 121) is increased, and the overall device channel area can be increased compared to comparative embodiments with upright or curved gates. This results in improved device performance, such as increased processing speed or reliability.

[0067] Furthermore, the aforementioned contour of the gate layer 121 (in) Figures 1A to 12 (As discussed in the text) can be formed through simplified operations. In a comparative embodiment where the gate layer is formed before forming the high-k material, additional photolithography operations can be used to expose portions of the gate layer to connect the gate layer to word lines. In some embodiments, the present invention can reduce the total number of photolithography operations (e.g., reduce two photomasks), thereby improving yield and manufacturing efficiency.

[0068] Furthermore, the lateral pull-back technique on the sacrificial layer 112S creates sidewalls with a vertical profile. These sidewalls of the remaining sacrificial layer 112S are used to form the high-k materials 122 and 122' before the gate layer 121 is formed. In some cases, an additional etch stop layer can be omitted, thereby contributing to a reduction in device size. Moreover, this configuration allows for the formation of recesses to expose the sidewalls of the first high-k material 122 from the sacrificial layer 112S using an etch operation.

[0069] The similar techniques discussed in this invention can be applied to various types of memory structures or other semiconductor structures, including but not limited to non-volatile memory devices, volatile memory devices, nanosheet devices, all-around gate devices, nanowire devices, FinFET structures or other types of transistors.

[0070] Some embodiments of the present invention provide a semiconductor structure comprising: a substrate; a dielectric stack above the substrate, including a first layer above the substrate and a second layer above the first layer; and a gate layer including a first portion through the second layer and a second portion extending between the first and second layers.

[0071] Some embodiments of the present invention provide a semiconductor structure comprising: a substrate; a dielectric stack above the substrate, including a first layer above the substrate and a second layer above the first layer; and a first high-k material in direct contact with the bottom surface of the second layer.

[0072] Some embodiments of the present invention provide a method for manufacturing a semiconductor structure, comprising: forming a first layer over a substrate, wherein the first layer comprises a first material; forming a sacrificial layer over the first layer, wherein the sacrificial layer comprises a second material different from the first material; forming a second layer over the sacrificial layer; forming a first trench to expose the sidewalls of the sacrificial layer; and forming a gate material in the first trench.

[0073] Some embodiments of this application provide a semiconductor structure including: a substrate; a dielectric stack above the substrate, the dielectric stack including: a first layer above the substrate; and a second layer above the first layer; a gate layer inserted into the dielectric stack and including a first portion and a second portion, wherein the first portion extends from top to bottom through the second layer, and wherein the second portion extends laterally between the first layer and the second layer to be located above the first layer and below the second layer; and a semiconductor channel layer conforming to the outline of the gate layer and enclosing the second portion to separate the second portion from the dielectric stack.

[0074] In some embodiments, the semiconductor channel layer is located on three different sides of the second protrusion. In some embodiments, the semiconductor structure further includes: a conductive member extending from top to bottom through the second layer, wherein the second portion is laterally located between and adjacent to the conductive member and the first portion. In some embodiments, the bottom surface of the conductive member is located at a horizontal plane lower than the horizontal plane of the top surface of the first layer. In some embodiments, the first layer extends laterally in a closed path to surround the conductive member. In some embodiments, the semiconductor structure further includes: a first high-k material in direct contact with the bottom surface of the second layer and separating the second portion from the dielectric stack. In some embodiments, the first high-k material includes a sidewall connecting the bottom surface of the second layer and the top surface of the first layer, wherein the angle between the sidewall of the first high-k material and the bottom surface of the second layer is in the range of 80 degrees to 90 degrees.

[0075] Other embodiments of this application provide a semiconductor structure including: a substrate; a dielectric stack above the substrate, the dielectric stack including: a first layer above the substrate; and a second layer above the first layer; a gate layer extending from top to bottom through the dielectric stack and having a cross-shaped profile; and a first high-k material in direct contact with the bottom surface of the second layer and separating the gate layer from the dielectric stack.

[0076] In some embodiments, the semiconductor structure further includes: a channel layer conforming to the inner sidewall of the first high-k material and separating the gate layer from the first high-k material. In some embodiments, the first high-k material is in direct contact with the top surface of the first layer. In some embodiments, the first high-k material comprises hafnium zirconium oxide or hafnium zirconium. In some embodiments, the gate layer includes a pair of protrusions, wherein the protrusions are located on opposite sides of the gate layer and protrude in opposite directions to positions below the second layer and above the first layer. In some embodiments, the semiconductor structure further includes: a second high-k material in direct contact with the top and bottom surfaces of the protrusions, wherein the composition of the second high-k material is different from that of the first high-k material.

[0077] Further embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a first layer over a substrate, wherein the first layer comprises a first material; forming a sacrificial layer over the first layer, wherein the sacrificial layer comprises a second material different from the first material; forming a second layer over the sacrificial layer; forming a first recess to expose sidewalls of the sacrificial layer; laterally removing a portion of the sacrificial layer from the sidewalls; and forming a gate material in the first recess, wherein the gate material is located below the second layer and above the first layer.

[0078] In some embodiments, lateral removal of a portion of the sacrificial layer includes applying phosphoric acid over the substrate. In some embodiments, after lateral removal of a portion of the sacrificial layer, a portion of the bottom surface of the second layer is exposed. In some embodiments, the method further includes forming a first high-k material conforming to the profile of the first groove and directly contacting the bottom surface of the second layer. In some embodiments, the method further includes forming a semiconductor channel layer on top of the first high-k material and conforming to the first high-k material, wherein the semiconductor channel layer extends along the bottom surface of the second layer. In some embodiments, the method further includes forming a second groove extending through the second layer and exposing the sidewalls of the first high-k material after forming the gate material in the first groove. In some embodiments, the method further includes replacing the sacrificial layer with a spacer layer.

[0079] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

[0080] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of substances, means, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of this invention that, according to the present invention, processes, machines, manufactures, compositions of substances, means, methods, or steps that are currently existing or will be developed thereafter can be utilized to implement substantially the same function or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of substances, means, methods, or steps within their scope.

Claims

1. A semiconductor structure, comprising: Substrate; A dielectric stack is located above the substrate, the dielectric stack comprising: a first layer located above the substrate; and a second layer located above the first layer; A gate layer, inserted into the dielectric stack and comprising a first portion and a second portion, wherein the first portion extends from top to bottom through the second layer, and wherein the second portion extends laterally between the first layer and the second layer, situated above the first layer and below the second layer; and A semiconductor channel layer conforms to the outline of the gate layer and wraps around the second portion to separate the second portion from the dielectric stack.

2. The semiconductor structure of claim 1, wherein, The semiconductor channel layer is located on three different sides of the second portion.

3. The semiconductor structure of claim 1, further comprising: A conductive component extends from top to bottom through the second layer, wherein the second portion is laterally located between and adjacent to the conductive component and the first portion.

4. The semiconductor structure of claim 3, wherein, The bottom surface of the conductive component is located at a horizontal plane that is lower than the horizontal plane of the top surface of the first layer.

5. The semiconductor structure of claim 3, wherein, The first layer extends laterally in a closed path to surround the conductive component.

6. The semiconductor structure according to claim 1, further comprising: A first high-k material is in direct contact with the bottom surface of the second layer and separates the second portion from the dielectric stack.

7. The semiconductor structure according to claim 6, wherein, The first high-k material includes a sidewall connecting the bottom surface of the second layer and the top surface of the first layer, wherein the angle between the sidewall of the first high-k material and the bottom surface of the second layer is in the range of 80 degrees to 90 degrees.

8. A semiconductor structure, comprising: Substrate; A dielectric stack is located above the substrate, the dielectric stack comprising: a first layer located above the substrate; and a second layer located above the first layer; A gate layer, extending from top to bottom through the dielectric stack and having a cross-shaped profile; and A first high-k material is in direct contact with the bottom surface of the second layer and separates the gate layer from the dielectric stack. The channel layer conforms to the outline of the gate layer and separates the gate layer from the first high-k material.

9. The semiconductor structure according to claim 8, wherein, The channel layer conforms to the inner wall of the first high-k material.

10. The semiconductor structure according to claim 8, wherein, The first high-k material is in direct contact with the top surface of the first layer.

11. The semiconductor structure according to claim 8, wherein, The first high-k material includes hafnium zirconium oxide or hafnium zirconium oxide.

12. The semiconductor structure according to claim 8, wherein, The gate layer includes a pair of protrusions, wherein the protrusions are located on opposite sides of the gate layer and protrude in opposite directions to a position below the second layer and above the first layer.

13. The semiconductor structure according to claim 12, further comprising: A second high-k material is in direct contact with the top and bottom surfaces of the protrusion, wherein the composition of the second high-k material is different from that of the first high-k material.

14. A method for forming a semiconductor structure, comprising: A first layer is formed over a substrate, wherein the first layer comprises a first material; A sacrificial layer is formed above the first layer, wherein the sacrificial layer comprises a second material different from the first material; A second layer is formed above the sacrificial layer; A first groove is formed to expose the sidewalls of the sacrificial layer; A portion of the sacrificial layer is removed laterally from the sidewall; A first high-k material is formed to conform to the contour of the first groove; Forming a semiconductor channel layer on top of the first high-k material and conforming to the first high-k material; and A gate material is formed in the first groove, wherein the gate material is located below the second layer and above the first layer.

15. The method according to claim 14, wherein, The lateral removal of the sacrificial layer includes applying phosphoric acid over the substrate.

16. The method of claim 14, wherein, After a portion of the sacrificial layer is removed laterally, a portion of the bottom surface of the second layer is exposed.

17. The method of claim 14, wherein, The first high-k material is in direct contact with the bottom surface of the second layer.

18. The method according to claim 17, wherein, The semiconductor channel layer extends along the bottom surface of the second layer.

19. The method of claim 17, further comprising: After the gate material is formed in the first groove, a second groove is formed that extends through the second layer and exposes the sidewalls of the first high-k material.

20. The method of claim 14, further comprising: Replace the sacrificial layer with a spacer layer.

Images