Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: providing a substrate with a plurality of mutually separated fin structures thereon; forming a gate dielectric film on surfaces of the fin structures; forming a protective film on the substrate and on surfaces of the gate dielectric film; forming a gate electrode material layer on a surface of the protective film; etching part of the gate electrode material layer until surfaces of the protective film are exposed, thereby forming a plurality of mutually separated gate electrodes on the protective film, the gate electrodes crossing the fin structures. Thus, the performance and reliability of the semiconductor structure are improved, and the difficulty of the process for forming the semiconductor structure is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the control ability of the traditional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on the channel current is weakened, causing serious leakage current. The fin field-effect transistor (FinFET) is a new multi-gate device, which generally includes a fin portion protruding from the surface of a semiconductor substrate, a gate structure covering the top surface and sidewall of the fin portion, and source / drain doping regions in the fin portion on both sides of the gate structure.

[0003] With the further development of semiconductor technology, in order to increase the working current of the traditional fin field-effect transistor, a gate-all-around (GAA) structure fin field-effect transistor is also proposed, which increases the volume used as the channel region, further increasing the working current of the gate-all-around structure fin field-effect transistor.

[0004] However, the performance and reliability of the existing semiconductor structure still need to be improved, and at the same time, the process of forming the existing semiconductor structure is difficult. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance and reliability of the semiconductor structure and reduce the process difficulty of forming the semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate has a plurality of mutually separate fin structures on the substrate; a gate dielectric film located on the surface of the fin structure; a protective film located on the surface of the substrate and the gate dielectric film; a plurality of mutually separate gate electrodes located on the surface of the protective film, and the gate electrodes span the fin structure.

[0007] Optionally, the thickness of the protective film ranges from 50 angstroms to 150 angstroms.

[0008] Optionally, the material of the protective film is different from the material of the gate dielectric film.

[0009] Optionally, it further comprises: an intermediate film located between the surface of the substrate and the protective film, and between the gate dielectric film and the protective film.

[0010] Optionally, the thickness of the intermediate film is less than the thickness of the protective film.

[0011] Optionally, the thickness of the intermediate film ranges from 20 angstroms to 80 angstroms.

[0012] Optionally, the material of the intermediate film is different from the material of the gate dielectric film, and the material of the intermediate film is different from the material of the protective film.

[0013] Optionally, further comprising: an isolation dielectric layer between the surface of the substrate and the protective film, the isolation dielectric layer is also located on part of the sidewall surface of the fin structure.

[0014] Optionally, the material of the protective film comprises a dielectric material or a metal compound.

[0015] Optionally, the fin structure comprises: a plurality of layers of sacrificial layers arranged in a direction perpendicular to the surface of the substrate, and a nanosheet located between adjacent sacrificial layers.

[0016] Correspondingly, the present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually discrete fin structures thereon; forming a gate dielectric film on the surface of the fin structure; forming a protective film on the surface of the substrate and the gate dielectric film; forming a gate electrode material layer on the surface of the protective film; etching part of the gate electrode material layer until the surface of the protective film is exposed, forming a plurality of mutually discrete gate electrodes on the protective film, the gate electrodes spanning the fin structure.

[0017] Optionally, the method for etching part of the gate electrode material layer further comprises: etching part of the gate electrode material layer using a first etching process until the top surface of the protective film is exposed; after the top surface of the protective film is exposed, etching part of the gate electrode material layer using a second etching process until the surface of the protective film on the substrate is exposed, forming a plurality of gate electrodes, and the etching rate of the protective film in the first etching process is greater than the etching rate of the protective film in the second etching process.

[0018] Optionally, the first etching process comprises a dry etching process, and the process parameters of the first etching process include: a pressure range of 4 mTorr to 100 mTorr; a source power range of 200 W to 2000 W; a bias power range of 400 W to 2000 W; and an etching gas comprising a halogen-containing gas.

[0019] Optionally, in the second etching process, the etching selectivity of the gate electrode material layer and the protective film is above 5:1.

[0020] Optionally, the second etching process comprises a dry etching process, and process parameters of the second etching process comprise: a pressure range of 20-400 mTorr, a source power range of 500-2000 W, a bias power range of 0-800 W, and an etching gas comprising one or more of a chlorine-containing gas and a bromine-containing gas, and a protective gas comprising oxygen or nitrogen.

[0021] Optionally, the protective film has a thickness in a range of 50-150 angstroms.

[0022] Optionally, the material of the protective film is different from that of the gate dielectric film.

[0023] Optionally, the method further comprises forming an intermediate film on the surface of the gate dielectric film and the substrate before forming the protective film.

[0024] Optionally, the intermediate film has a thickness less than that of the protective film.

[0025] Optionally, the intermediate film has a thickness in a range of 20-80 angstroms.

[0026] Optionally, the material of the intermediate film is different from that of the gate dielectric film and that of the protective film.

[0027] Optionally, the material of the intermediate film comprises silicon, silicon nitride or silicon germanium.

[0028] Optionally, the process of forming the intermediate film comprises a chemical vapor deposition process, an atomic layer deposition process or a thermal oxidation process.

[0029] Optionally, the method further comprises etching the protective film until the surface of the intermediate film is exposed after forming the gate electrode, and etching the intermediate film until the surface of the substrate is exposed after etching the protective film.

[0030] Optionally, the method further comprises forming an isolation dielectric layer on the surface of the substrate before forming the gate dielectric film, the isolation dielectric layer also being located on part of the side wall surface of the fin structure.

[0031] Optionally, the material of the protective film comprises a dielectric material or a metal compound.

[0032] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0033] The forming method of the semiconductor structure provided by the technical scheme forms a gate dielectric film on the surface of the fin structure, and after forming a protective film on the substrate and the surface of the gate dielectric film, etches the gate electrode material layer to form a plurality of mutually separated gate electrodes on the protective film. Therefore, the fin structure and the gate dielectric film can be protected by the protective film in the subsequent etching process of etching the gate electrode material layer, the damage to the fin structure and the gate dielectric film is reduced, the influence on the electrical performance of the semiconductor device is reduced, the limitation on the etching process of etching the gate electrode material layer is reduced, the process window of the etching process is increased, the performance and reliability of the semiconductor structure are improved, and the process difficulty of forming the semiconductor structure is reduced.

[0034] Further, in the method of etching the gate electrode material layer, the first etching process is used to etch the gate electrode material layer until the top surface of the protective film is exposed, and after the top surface of the protective film is exposed, the second etching process is used to etch part of the gate electrode material layer until the surface of the protective film on the substrate is exposed to form a plurality of gate electrodes. Therefore, after the first etching process is used to etch the gate electrode material layer, the thickness consistency of the remaining gate electrode material layer on the substrate is higher, so that when the second etching process is used to etch the gate electrode material layer, the process window of the second etching process can be increased and the difficulty of the second etching process can be reduced. At the same time, since the etching rate of the protective film in the first etching process is greater than the etching rate of the protective film in the second etching process, the etching efficiency can be improved and the damage to the protective film can be reduced in the etching process of forming the gate electrode layer, so that the performance of the semiconductor structure is improved while the process efficiency is improved. Specifically, on the one hand, since the top surface of the protective film is stopped in the process of etching the gate electrode material layer by using the first etching process, the influence of the protective film on the first etching process is small, that is, the protective film has less limitation on the process parameters of the first etching process, so that the gate electrode material layer can be etched faster to improve the etching efficiency. On the other hand, since the etching rate of the protective film in the second etching process is smaller, the damage to the protective film can be reduced in the etching process after the top surface of the protective film is exposed while etching the gate electrode material layer, so that the performance of the semiconductor structure is improved.

[0035] Further, since the intermediate film is formed on the surface of the gate dielectric film and the substrate before the protective film is formed, on the one hand, the fin structure and the gate dielectric film can be protected by the intermediate film in the subsequent process of etching the protective film; on the other hand, the intermediate film is protected by the protective film in the process of etching the gate electrode material layer, so that the loss of the intermediate film is small, that is, the uniformity of the thickness of the intermediate film is good before the intermediate film is etched, and further, in the subsequent process of etching the intermediate film until the surface of the gate dielectric film is exposed, the damage of the gate dielectric film and the fin structure caused by the etching process of etching the intermediate film can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figures 1 to 7 is a structure diagram of each step of a forming method of a semiconductor structure;

[0037] Figures 8 to 20 is a structure diagram of each step of a forming method of a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] As described in the background, the performance and reliability of the existing semiconductor structure are poor, and the process of forming the existing semiconductor structure is difficult. The present application will be described in conjunction with specific embodiments, Figures 1 to 7 is a structure diagram of each step of a forming method of a semiconductor structure.

[0039] It should be noted that the "surface" in the present specification is used to describe the relative position relationship in space, and is not limited to whether it is in direct contact.

[0040] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 has a plurality of mutually separated fin structures 101; an isolation dielectric layer 110 is formed on the surface of the substrate 100, and the isolation dielectric layer 110 is also located on part of the side wall surface of the fin structure 101; after the isolation dielectric layer 110 is formed, a gate dielectric layer 120 is formed on the surface of the fin structure 101; an initial gate electrode material layer 130 is formed on the surface of the gate dielectric layer 120 and the surface of the isolation dielectric layer 110; and a plurality of mutually separated gate mask structures 140 are formed on the surface of the initial gate electrode material layer 130.

[0041] Please refer to Figure 2 , the initial gate electrode material layer 130 is etched by taking the gate mask structure 140 as a mask to form a gate electrode material layer 131, and the surface of the gate electrode material layer 131 is higher than the top surface of the fin structure 101.

[0042] Please refer to Figures 3 to 5 , Figure 3 isFigure 5 a cross-sectional structure schematic view along the direction A1-A2, Figure 4 Figure 5 a cross-sectional structure schematic view along the direction B1-B2, Figure 5 Figure 4 a top view structure schematic view along the direction C, after forming the gate electrode material layer 131, continue to perform a second etching on the gate electrode material layer 131 with the gate mask structure 140 as a mask, until the surface of the isolation dielectric layer 110 is exposed, forming a plurality of mutually separated gate electrode layers 132, which span the fin structure 101.

[0043] Compared with forming a gate electrode layer on a plane, forming a gate electrode layer on the surface of a three-dimensional fin structure 101 increases the aspect ratio of the structure of the gate electrode layer. In order to protect the fin structure 101 and the gate dielectric layer 120 while forming the gate electrode layer 132 with a larger aspect ratio, the first etching and the second etching are performed respectively.

[0044] Specifically, in the process of the first etching, by reducing the limit of the etching selectivity ratio of the materials of the initial gate electrode material layer 130 and the fin structure 101, and the initial gate electrode material layer 130 and the gate dielectric layer 120 respectively, the etching speed of the initial gate electrode material layer 130 is increased; in the process of the second etching, on the one hand, the etching selectivity ratio of the materials of the initial gate electrode material layer 130 and the fin structure 101, and the etching selectivity ratio of the materials of the initial gate electrode material layer 130 and the gate dielectric layer 120 are increased, on the other hand, by forming a large amount of etching by-products (such as SiO2) on the sidewall surface of the fin structure 101 (as shown in region I in Figure 3 and region II in Figure 5 , so that the fin structure 101 and the gate dielectric layer 120 are protected during the second etching, and the damage of the fin structure 101 and the gate dielectric layer 120 caused by the second etching is reduced.

[0045] Please refer to Figure 6 and Figure 7 , Figure 6 consistent with the view direction of Figure 3 , Figure 7 consistent with the view direction of Figure 4 , after forming the gate electrode layer 132, perform a third etching on the sidewall of the bottom of the gate electrode layer 132 (as shown in region III in Figure 4 , and the sidewall surface of the fin structure 101, to remove the residual material of the gate electrode layer 132 on the sidewall surface of the fin structure 101, and at the same time, increase the perpendicularity of the sidewall surface of the gate electrode layer 132.

[0046] The process of the third etching is a plasma etching process.​​

[0047] However, in the above method, in order to better remove the residue of the material of the gate electrode layer 132 on the sidewall surface of the fin structure 101, and ensure the verticality of the sidewall surface of the gate electrode layer 132, in the third etching process, the incidence angle of the plasma (the angle between the incidence direction of the plasma and the normal direction of the surface of the substrate 100) is large, and the energy of the plasma is high, so that the fin structure 101 and the gate dielectric layer 120 are easily damaged in the third etching process, which affects the electrical performance of the semiconductor device, and makes the performance and reliability of the semiconductor structure poor.

[0048] Moreover, on the one hand, when there are many etching by-products in the second etching process, it is difficult to remove the residue on the sidewall surface of the fin structure 101 in the third etching process, and it is not conducive to improving the verticality of the sidewall surface of the gate electrode layer 132; on the other hand, when there are few etching by-products in the second etching process, the fin structure 101 and the gate dielectric layer 120 are easily damaged in the second etching process. Therefore, the process window of the second etching process is small, and the difficulty of the etching process is great.

[0049] To solve the technical problem, the embodiment of the present application provides a semiconductor structure and a forming method thereof. Before etching the gate electrode material layer, a protective film is formed on the substrate and the surface of the gate dielectric film, and the gate electrode material layer is formed on the surface of the protective film. Therefore, the performance and reliability of the semiconductor structure are improved, and the process difficulty of forming the semiconductor structure is reduced.

[0050] In order to make the above-mentioned purposes, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0051] Figures 8 to 20 is a structure schematic diagram of each step of the forming method of the semiconductor structure of an embodiment of the present application.

[0052] Please refer to Figure 8 , a substrate 200 is provided, and the substrate 200 has a plurality of mutually separated fin structures 201 on the surface thereof; and a gate dielectric film 221 is formed on the surface of the fin structure 201.

[0053] The material of the substrate 200 includes a semiconductor material.

[0054] In the embodiment, the material of the substrate 200 is silicon.

[0055] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, InGaAsP, or the like.

[0056] In other embodiments, the fin structure includes a plurality of fin sacrificial layers arranged along a direction perpendicular to the surface of the substrate, and nanosheets located between adjacent fin sacrificial layers.

[0057] In this embodiment, before forming the gate dielectric film 221, an isolation dielectric layer 210 is formed on the surface of the substrate 200, and the isolation dielectric layer 210 is also located on part of the sidewall surface of the fin structure 201.

[0058] In this embodiment, the material of the gate dielectric film 221 is silicon oxide.

[0059] In this embodiment, the process of forming the gate dielectric film 221 includes an oxidation process.

[0060] Please refer to Figure 9 A protective film 230 is formed on the surface of the substrate 200 and the surface of the gate dielectric film 221.

[0061] Specifically, since the isolation dielectric layer 210 is formed on the surface of the substrate 200 in this embodiment, forming the protective film 230 on the surface of the substrate 200 and the surface of the gate dielectric film 221 means that the protective film 230 is formed on the surface of the isolation dielectric layer 210 and the surface of the gate dielectric film 221.

[0062] The protective film 230 is used to protect the fin structure 201 and the gate dielectric film 221 during subsequent etching of the gate electrode material layer.

[0063] In this embodiment, the thickness of the protective film 230 ranges from 50 angstroms to 150 angstroms.

[0064] The protection film 230 is too thick, on one hand, increasing the difficulty of removing the protection film 230, causing the process difficulty of forming the semiconductor structure to increase and the efficiency to decrease, on the other hand, in the process of removing the protection film 230 on the surface of the fin structure 201, the fin structure 201 is easily damaged, which is not conducive to improving the performance and reliability of the semiconductor structure. The protection film 230 is too thin, then in the etching process of etching the gate electrode material layer, the protection ability of the fin structure 201 and the gate dielectric film 221 is insufficient, causing the fin structure 201 and the gate dielectric film 221 to be damaged, which is also not conducive to improving the performance and reliability of the semiconductor structure. Therefore, selecting a suitable thickness of the protection film 230, that is, the thickness of the protection film 230 ranges from 50 angstroms to 150 angstroms, on one hand, can reduce the process difficulty and improve the efficiency, on the other hand, it is conducive to better improving the performance and reliability of the semiconductor structure.

[0065] In the embodiment, the process of forming the protection film 230 includes a deposition process, and the deposition process includes at least one of a chemical vapor deposition process, a physical deposition process, and an atomic layer deposition process.

[0066] In the embodiment, the material of the protection film 230 includes a dielectric material or a metal compound.

[0067] Specifically, the dielectric material is, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbonitride, etc. The metal compound is, for example, titanium nitride, aluminum oxide, or tungsten oxide, etc.

[0068] In the embodiment, before forming the protection film 230, an intermediate film 231 is formed on the surface of the gate dielectric film 221 and the substrate 200.

[0069] Specifically, in the embodiment, the intermediate film 231 is located between the protection film 230 and the gate dielectric film 221, and between the protection film 230 and the surface of the substrate 200.

[0070] Since the intermediate film 231 is formed on the surface of the gate dielectric film 221 and the substrate 200 before the protective film 230 is formed, on the one hand, the fin structure 201 and the gate dielectric film 221 can be protected by the intermediate film 231 in the subsequent etching process of the protective film 230; on the other hand, the intermediate film 231 is protected by the protective film 230 in the subsequent etching process of the gate electrode material layer, so that the loss of the intermediate film 231 is small, that is, the uniformity of the thickness of the intermediate film 231 is good before the intermediate film 231 is etched, and thus the damage of the etching process of the intermediate film 231 to the gate dielectric film 221 and the fin structure 201 can be reduced in the subsequent etching process of the intermediate film 231 until the surface of the gate dielectric film 221 is exposed.

[0071] In this embodiment, the thickness of the intermediate film 231 is less than the thickness of the protective film 230. Therefore, the intermediate film 231 on the surface of the gate dielectric film 221 can be removed more easily after the etching of the protective film 230, so as to reduce the damage of the etching process of the gate dielectric film 221 to the fin structure 201 and the gate dielectric film 221, and improve the performance and reliability of the semiconductor structure.

[0072] In this embodiment, the thickness of the intermediate film 231 ranges from 20 angstroms to 80 angstroms.

[0073] If the thickness of the intermediate film 231 is too large, the process difficulty of removing the intermediate film 231 is increased, and the fin structure 201 is easily damaged in the process of removing the intermediate film 231 on the surface of the fin structure 201, which is not conducive to improving the performance and reliability of the semiconductor structure. If the thickness of the intermediate film 231 is too small, the protection of the fin structure 201 and the gate dielectric film 221 is insufficient in the etching process of the protective film 230, which also causes damage to the fin structure 201 and the gate dielectric film 221, and is not conducive to improving the performance and reliability of the semiconductor structure. Therefore, when the thickness of the intermediate film 231 ranges from 20 angstroms to 80 angstroms, on the one hand, the process difficulty of removing the intermediate film 231 is reduced, and on the other hand, the performance and reliability of the semiconductor structure are improved.

[0074] The process of forming the intermediate film 231 includes a chemical vapor deposition process, an atomic layer deposition process or a thermal oxidation process.

[0075] In this embodiment, the process of forming the intermediate film 231 is an atomic layer deposition process.

[0076] The intermediate film 231 can be formed by an atomic layer deposition process, so that the intermediate film 231 is dense and thin, and can meet the thickness requirement of the intermediate film 231, and the dense intermediate film 231 has a stronger barrier capability, so that the fin structure 201 and the gate dielectric film 221 can be better protected during the subsequent etching of the protection film 230.

[0077] In this embodiment, the material of the intermediate film 231 is different from the material of the gate dielectric film 221, and the material of the intermediate film 231 is different from the material of the protection film 230.

[0078] In this embodiment, the material of the intermediate film 231 includes silicon, such as amorphous silicon or polycrystalline silicon.

[0079] In other embodiments, the material of the intermediate film includes silicon nitride or silicon germanium.

[0080] In another embodiment, the intermediate film is not formed, and the material of the protection film is different from the material of the gate dielectric film.

[0081] Please refer to Figures 10 to 12 , Figure 11 is Figure 10 a schematic diagram of a cross-sectional structure along the X1-X2 direction in the protection film 230, Figure 12 is Figure 10 a schematic diagram of a cross-sectional structure along the Y1-Y2 direction in the protection film 230, Figure 10 is Figure 11 a schematic diagram of a top view structure along the Z direction in the protection film 230, and a gate electrode material layer 240 is formed on the surface of the protection film 230.

[0082] The gate electrode material layer 240 provides material for the subsequent formation of a gate electrode.

[0083] In this embodiment, the process for forming the gate electrode material layer 240 includes a deposition process, such as a chemical vapor deposition process, a physical deposition process, or an atomic layer deposition process.

[0084] In this embodiment, the material of the gate electrode material layer 240 includes silicon, such as amorphous silicon or polycrystalline silicon. Correspondingly, the material for the subsequent formation of the electrode layer includes silicon, such as amorphous silicon or polycrystalline silicon.

[0085] Then, part of the gate electrode material layer 240 is etched until the surface of the protection film 230 is exposed, and a plurality of mutually separated gate electrodes are formed on the protection film 230, and the gate electrodes cross the fin structure 201.

[0086] After the gate dielectric film 221 is formed on the surface of the fin structure 201, and the protective film 230 is formed on the substrate 200 and the surface of the gate dielectric film 221, the gate electrode material layer 240 is etched to form a plurality of mutually separated gate electrodes on the protective film 230. Thus, the fin structure 201 and the gate dielectric film 221 can be protected by the protective film 230 during the etching of the gate electrode material layer 240, the damage to the fin structure 201 and the gate dielectric film 221 is reduced, the influence on the electrical performance of the semiconductor device is reduced, the etching process for etching the gate electrode material layer 240 is not limited, and the process window of the etching process is increased. Thus, the performance and reliability of the semiconductor structure are improved, and the process difficulty for forming the semiconductor structure is reduced.

[0087] The specific steps for forming the gate electrode are described below with reference to Figures 10 to 20 .

[0088] The specific steps for forming the gate electrode are described below with reference to Figures 10 to 12 A plurality of mutually separated gate electrode mask structures 241 are formed on the surface of the gate electrode material layer 240, and the gate electrode mask structures 241 span the fin structure 201.

[0089] The method for forming the gate electrode mask structures 241 includes: forming a gate electrode mask material layer (not shown) on the surface of the gate electrode material layer 240; using an exposure and development process to form a photoresist patterned layer (not shown) on the surface of the gate electrode mask material layer; and etching the gate electrode mask material layer until the gate electrode material layer 240 is exposed, using the photoresist patterned layer as a mask.

[0090] The process for forming the gate electrode mask material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0091] The process for etching the gate electrode mask material layer includes a dry etching process or a wet etching process.

[0092] In this embodiment, the material of the gate electrode mask structures 241 includes a dielectric material or a combination of a plurality of dielectric materials, and the dielectric material includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon oxycarbonitride.

[0093] In this embodiment, the photoresist patterned layer is removed after the gate electrode mask structures 241 are formed. The process for removing the photoresist patterned layer includes an ashing process.

[0094] The specific steps for forming the gate electrode are described below with reference to Figures 13 to 14 , Figure 13 andFigure 11 The view orientation is consistent. Figure 14 and Figure 12 With the view direction consistent, using the gate electrode mask structure 241 as a mask, a portion of the gate electrode material layer 240 is etched using the first etching process until the top surface of the protective film 230 is exposed.

[0095] The first etching process includes either a dry etching process or a wet etching process.

[0096] In this embodiment, the first etching process is a dry etching process.

[0097] Specifically, in this embodiment, the dry etching process is a plasma etching process, and the process parameters of the first etching process include: a pressure range of 4 mTorr to 100 mTorr; a source power range of 200 watts to 2000 watts; a bias power range of 400 watts to 2000 watts; and the etching gas includes a gas containing halogen elements.

[0098] Please refer to Figures 15 to 17 , Figure 16 yes Figure 15 A schematic diagram of the cross-sectional structure along the X3-X4 direction. Figure 17 yes Figure 15 A schematic diagram of the cross-sectional structure along the Y1-Y2 direction. Figure 15 yes Figure 16 A top view of the structure along the Z-direction shows that after the top surface of the protective film 230 is exposed, a second etching process is used to continue etching a portion of the gate electrode material layer 240 using the gate electrode mask structure 241 as a mask until the surface of the protective film 230 on the substrate 200 is exposed, forming a plurality of gate electrodes 242. Furthermore, the etching rate of the protective film 230 in the first etching process is greater than the etching rate of the protective film 230 in the second etching process.

[0099] In the method of etching the gate electrode material layer 240, since the first etching process is used to etch the gate electrode material layer 240 until the top surface of the protective film 230 is exposed, and after the top surface of the protective film 230 is exposed, the second etching process is used to etch part of the gate electrode material layer 240 until the surface of the protective film 230 on the substrate 200 is exposed to form the gate electrode 242, therefore, after the first etching process is used to etch the gate electrode material layer 240, the thickness consistency of the gate electrode material layer 240 remaining on the substrate 200 is higher, so that when the second etching process is used to etch the gate electrode material layer 240, the process window of the second etching process can be increased, and the difficulty of the second etching process is reduced. At the same time, since the etching rate of the protective film 230 in the first etching process is greater than the etching rate of the protective film 230 in the second etching process, in the etching process of forming the gate electrode layer 242, the etching efficiency can also be improved, and the damage to the protective film 230 is reduced, so that the process efficiency is improved, and the performance of the semiconductor structure is better improved.

[0100] Specifically, on the one hand, since the top surface of the protective film 230 is stopped in the process of etching the gate electrode material layer 240 by using the first etching process, the first etching process is less affected by the protective film 230, that is, the protective film 230 has less limitation on the process parameters of the first etching process, so that the gate electrode material layer 240 can be etched faster to improve the etching efficiency. On the other hand, since the etching rate of the protective film 230 in the second etching process is smaller, in the etching process after the top surface of the protective film 230 is exposed, the damage to the protective film 230 can be reduced while etching the gate electrode material layer 240, so that the performance of the semiconductor structure is better improved.

[0101] In the embodiment, the gate electrode 242 is a pseudo gate in the back gate process.

[0102] In the embodiment, the etching selectivity ratio of the gate electrode material layer 240 to the protective film 230 in the second etching process is greater than 5:1. Therefore, in the etching process after the top surface of the protective film 230 is exposed, the damage to the protective film 230 can be reduced while etching the gate electrode material layer 240.

[0103] The second etching process includes a dry etching process or a wet etching process.

[0104] In the embodiment, the second etching process is a dry etching process.

[0105] Specifically, in the embodiment, the dry etching process is a plasma etching process, and the process parameters of the second etching process include: a pressure range of 20-400 mTorr, a source power range of 500-2000 W, a bias power range of 0-800 W, and an etching gas including one or more of a chlorine-containing gas and a bromine-containing gas, and a protective gas including oxygen or nitrogen.

[0106] In the embodiment, after the gate electrode 242 is formed, the gate electrode mask structure 241 is removed.

[0107] Please refer to Figures 18 to 20 , Figure 19 is Figure 18 a cross-sectional structure schematic view along the X3-X4 direction in the embodiment, Figure 20 is Figure 18 a cross-sectional structure schematic view along the Y1-Y2 direction in the embodiment, Figure 18 is Figure 19 a top view structure schematic view along the direction Z in the embodiment, after the gate electrode 242 is formed, the protective film 230 is etched until the surface of the intermediate film 231 is exposed; after the protective film 230 is etched, the intermediate film 231 is etched until the surface of the substrate 200 is exposed.

[0108] In the embodiment, the process of etching the protective film 230 includes a dry etching process or a wet etching process.

[0109] Specifically, in the process of etching the protective film 230, the etching selectivity of the protective film 230 and the intermediate film 231 is above 3:1. Thus, by using a larger etching selectivity, the loss of the intermediate film 231 can be reduced during the etching of the protective film 230, so as to improve the protection ability of the intermediate film 231 to the fin structure 201 and the gate dielectric film 221.

[0110] Specifically, in the process of etching the protective film 230, the etching selectivity of the protective film 230 and the gate electrode 242 is above 5:1. Thus, by using a larger etching selectivity, the damage to the surface of the gate electrode 242 can be reduced during the etching of the protective film 230, so as to form a gate structure with better quality and higher pattern precision in the subsequent gate-last process.

[0111] In the embodiment, the process of etching the intermediate film 231 includes a dry etching process or a wet etching process.

[0112] Specifically, in the process of etching the intermediate film 231, the etching selectivity ratio of the intermediate film 231 to the gate dielectric film 221 is greater than 5:1. Thus, by the larger etching selectivity ratio, the damage to the surface of the gate dielectric film 221 can be reduced in the process of etching the intermediate film 231, so as to reduce the influence on the performance of the semiconductor structure.

[0113] Specifically, in the process of etching the intermediate film 231, the etching selectivity ratio of the intermediate film 231 to the gate electrode 242 is greater than 7:1. Thus, by the larger etching selectivity ratio, the damage to the surface of the gate electrode 242 can be reduced in the process of etching the intermediate film 231, so as to form a gate electrode structure with better quality and higher pattern precision in the subsequent gate-last process.

[0114] In the embodiment, after the intermediate film 231 is etched until the surface of the substrate 200 is exposed, a first dielectric layer (not shown) is formed on the surface of the isolation dielectric layer 210, and the surface of the first dielectric layer exposes the top surface of the gate electrode 242; the gate electrode 242 and the residual protective film 230 and intermediate film 231 between the gate electrode layer 242 and the isolation dielectric layer 210 are removed to form a plurality of gate openings (not shown) in the first dielectric layer; and the gate electrode structure is formed in the gate openings.

[0115] Correspondingly, the embodiment of the present application also provides a semiconductor structure formed by the above method, which will be described below with reference to Figures 15 to 17 , comprising: a substrate 200, wherein the substrate 200 has a plurality of mutually separated fin structures 201; a gate dielectric film 221 located on the surface of the fin structure 201; a protective film 230 located on the surface of the substrate 200 and the gate dielectric film 221; and a plurality of mutually separated gate electrodes 242 located on the surface of the protective film 230 and crossing the fin structure 201.

[0116] The material of the substrate 200 includes a semiconductor material.

[0117] In the embodiment, the material of the substrate 200 is silicon.

[0118] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, InGaAsP, etc.

[0119] In other embodiments, the fin structure includes a plurality of fin sacrificial layers arranged in a direction perpendicular to the surface of the substrate, and a nanosheet located between adjacent fin sacrificial layers.

[0120] In this embodiment, the material of the gate dielectric film 221 is silicon oxide.

[0121] In this embodiment, the material of the protective film 230 includes a dielectric material or a metal compound.

[0122] Specifically, the dielectric material is, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbinitride, etc. The metal compound is, for example, titanium nitride, aluminum oxide, or tungsten oxide, etc.

[0123] In this embodiment, the thickness of the protective film 230 ranges from 50 angstroms to 150 angstroms.

[0124] In this embodiment, the semiconductor structure further includes an intermediate film 231 between the surface of the substrate 200 and the protective film 230, and between the gate dielectric film 221 and the protective film 230.

[0125] In this embodiment, the thickness of the intermediate film 231 is less than the thickness of the protective film 230.

[0126] In this embodiment, the thickness of the intermediate film 231 ranges from 20 angstroms to 80 angstroms.

[0127] In this embodiment, the material of the intermediate film 231 is different from the material of the gate dielectric film 221, and the material of the intermediate film 231 is different from the material of the protective film 230.

[0128] In this embodiment, the material of the intermediate film 231 includes silicon, for example, amorphous silicon or polycrystalline silicon, etc.

[0129] In other embodiments, the material of the intermediate film includes silicon nitride or silicon germanium.

[0130] In another embodiment, the semiconductor structure does not have an intermediate film, and the material of the protective film is different from the material of the gate dielectric film.

[0131] In this embodiment, the semiconductor structure further includes an isolation dielectric layer 210 between the surface of the substrate 200 and the protective film 230, and the isolation dielectric layer 210 is also on part of the sidewall surface of the fin structure 201.

[0132] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of mutually discrete fin structures; A gate dielectric film is formed on the surface of the fin structure; A protective film is formed on the substrate and on the surface of the gate dielectric film; A gate electrode material layer is formed on the surface of the protective film; The gate electrode material layer is etched until the surface of the protective film is exposed, so as to form a plurality of mutually discrete gate electrodes on the protective film, the gate electrodes spanning the fin structure; The method of etching a portion of the gate electrode material layer further includes: etching a portion of the gate electrode material layer using a first etching process until the top surface of the protective film is exposed; After exposing the top surface of the protective film, a second etching process is used to etch a portion of the gate electrode material layer until the surface of the protective film on the substrate is exposed to form a plurality of gate electrodes. Furthermore, the etching rate of the protective film in the first etching process is greater than the etching rate of the protective film in the second etching process.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process includes a dry etching process, and the process parameters of the first etching process include: a pressure range of 4 mTorr to 100 mTorr; a source power range of 200 watts to 2000 watts; a bias power range of 400 watts to 2000 watts; and an etching gas including a halogen-containing gas.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the second etching process, the etching selectivity ratio of the gate electrode material layer and the protective film is greater than 5:

1.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The second etching process includes a dry etching process, and the process parameters of the second etching process include: a pressure range of 20 mTorr to 400 mTorr, a source power range of 500 watts to 2000 watts, a bias power range of 0 watts to 800 watts, an etching gas including one or more of chlorine-containing gases and bromine-containing gases, and a protective gas including oxygen or nitrogen.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the protective film ranges from 50 angstroms to 150 angstroms.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective film is different from the material of the gate dielectric film.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming the protective film, an intermediate film is formed on the surface of the gate dielectric film and on the substrate.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The thickness of the intermediate film ranges from 20 angstroms to 80 angstroms.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The thickness of the intermediate film is less than the thickness of the protective film.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the intermediate film is different from the material of the gate dielectric film, and the material of the intermediate film is different from the material of the protective film.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the intermediate film includes silicon, silicon nitride, or silicon germanium.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for forming the intermediate film includes chemical vapor deposition, atomic layer deposition, or thermal oxidation.

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: After the gate electrode is formed, the protective film is etched until the surface of the intermediate film is exposed; After etching the protective film, the intermediate film is etched until the substrate surface is exposed.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: Before forming the gate dielectric film, an isolation dielectric layer is formed on the surface of the substrate, and the isolation dielectric layer is also located on a portion of the sidewall surface of the fin structure.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective film is made of dielectric materials or metal compounds.

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