A SOT-MRAM device and its forming method

Abstract

The present invention discloses a method for forming a SOT-MRAM device, comprising the following steps: providing a substrate, depositing a SOT layer on the substrate; patterning a magnetic tunnel junction pattern onto a photoresist above the SOT layer; curing the surface of the photoresist, and depositing a MTJ stack layer on the SOT layer; removing the photoresist on the SOT layer using a stripping process; depositing a dielectric layer on the SOT layer and the MTJ stack layer, patterning the dielectric layer, etching the dielectric layer, and transferring a desired pattern to the dielectric layer; and depositing an electrode layer on the patterned dielectric layer, patterning the electrode layer, and etching to form a SOT-MRAM device. By patterning the photoresist and then depositing a film stack, the present invention avoids device open circuits caused by etching the SOT layer, optimizes the sidewall morphology of the MTJ tunnel junction, eliminates sidewall damage and defects caused by etching, and improves the stability of the SOT-MRAM device.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memory, and in particular to a SOT-MRAM device and a method for forming the same. Background Art

[0002] The core of the traditional STT-MRAM (spin transfer torque magnetic random access memory) cell is a magnetic tunnel junction (MTJ) stack, which includes a pinning layer, a pinned layer above the pinning layer, a tunnel layer above the pinned layer, and a free layer above the tunnel layer. The write current must flow through the tunnel layer, causing damage to the tunnel layer, causing the STT-MRAM cell to encounter reliability issues. Therefore, SOT-MRAM (spin orbit torque magnetic random access memory) was developed. Since the write current does not flow through the tunnel layer, the reliability of SOT-MRAM is higher than that of STT-MRAM.

[0003] MTJ etching usually adopts RIE (reactive ion etching) or IBE (ion beam etching). In order to avoid RIE chemical corrosion that damages its electromagnetic properties, MTJ etching generally prefers IBE. However, due to the metal top electrode covering the upper part and the material forming the MTJ also containing metal elements, IBE etching is accompanied by sidewall metal deposition and plasma bombardment, which will cause serious short circuit and magnetic damage.

[0004] Therefore, MTJ tunnel junction etching presents two major challenges: short circuits and damage. Tunnel junctions are composed of metal materials, and some metal etching products are not volatile gases but solid residues. These residues easily adhere to the sidewalls of the tunnel junction, causing device short circuits. This is the number one challenge in tunnel junction etching. The second is damage. The etching materials during the etching process, whether chlorine- or fluorine-based gases in reactive ion etching (RIE) or inert gas plasma in ion beam etching (IBE), can damage the surface materials of the device, thereby degrading device performance. Halogen gases in RIE can continuously penetrate into the device, disrupting the magnetic properties of the MTJ. Ion beam etching can destroy the lattice structure of the cell surface, forming a damage layer on the surface, which can also cause magnetic damage. In particular, MTJ tunnel junction etching in SOT-MRAM should minimize damage to the SOT layer.

[0005] Chemical corrosion in RIE chemical etching or plasma bombardment in IBE plasma physical etching will damage the surface magnetic layer of the MTJ side wall. The resistance, TMR (tunneling magnetoresistance) and thermal stability of the damaged magnetic layer will deteriorate compared to a normal MTJ. At the same time, the halogen elements or oxygen and nitrogen ions present in the damaged magnetic layer will affect the performance or life of the finished device through diffusion during subsequent high-temperature processing or use. Summary of the Invention

[0006] In view of the defects or improvement needs of the above-mentioned technologies, the present invention provides a SOT-MRAM device and a method for forming the same, which adopts the method of depositing the MTJ tunnel junction after patterning the photoresist to replace the traditional continuous film layer etching, thereby avoiding device open circuit caused by etching of the SOT layer and metal redeposition on the side walls of the MTJ stack during the etching process.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for forming a SOT-MRAM device, comprising the following steps:

[0008] Step S1: providing a substrate and depositing a SOT layer on the substrate;

[0009] Step S2: performing photolithography on the SOT layer to pattern a magnetic tunnel junction pattern onto the photoresist above the SOT layer;

[0010] Step S3: curing the surface of the photoresist to form a cured layer;

[0011] Step S4: depositing an MTJ stack layer on the SOT layer having the patterned photoresist, wherein the MTJ stack layer starts from the upper surface of the SOT layer and includes, from bottom to top, a free layer, a tunnel junction barrier layer, a reference layer, a pinning layer, and a capping layer;

[0012] Step S5: removing the photoresist on the SOT layer and the film stack on the photoresist by a stripping process, and retaining the MTJ stack layer deposited on the SOT layer;

[0013] Step S6: depositing a dielectric layer on the SOT layer and the MTJ stack layer;

[0014] Step S7: performing patterning on the dielectric layer, etching the dielectric layer with a gas, transferring the desired pattern to the dielectric layer, and stopping the etching at the upper surface of the MTJ stack layer;

[0015] Step S8: depositing an electrode layer on the patterned dielectric layer;

[0016] Step S9: performing patterning on the electrode layer, etching the electrode layer with a gas, and transferring the desired pattern to the electrode layer to form a SOT-MRAM device.

[0017] As a further preference, the SOT layer has a thickness of 5 to 10 nm.

[0018] As a further preference, the photoresist has a thickness of 90 nm to 700 nm.

[0019] As a further preference, the thickness of the MTJ stack layer is 20 to 40 nm.

[0020] As a further preference, the dielectric layer material is any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, or a composite material formed by two or more of the above.

[0021] As a further preference, the dielectric layer is formed by chemical vapor deposition or atomic layer deposition, and the dielectric layer has a thickness of 40 nm to 200 nm.

[0022] As a further preference, the etching gas used in step S7 is one or a mixed gas formed by two or more of CF4, CHF3, SF6, and Ar.

[0023] As a further preference, the electrode layer material is an alloy formed by one or more of tantalum, ruthenium, platinum, gold, and chromium.

[0024] As a further preference, the etching gas used in step S9 is one or a mixed gas formed by two or more of CF4, CHF3, CCl4, BCl3, Ar, and Kr.

[0025] A memory including a SOT-MRAM device is manufactured by any one of the methods described above.

[0026] Compared with the prior art, the present invention has the following advantages or beneficial effects:

[0027] (1) The present invention optimizes the design of the preparation process of the SOT-MRAM magnetic tunnel junction and adopts the method of depositing the MTJ tunnel junction after patterning the photoresist to replace the traditional continuous film layer etching. It can effectively avoid the device open circuit caused by the etching of the SOT layer and the metal redeposition on the side wall of the MTJ stack during the etching process.

[0028] (2) The method for forming the SOT-MRAM device of the present invention does not include an etching process for the MTJ stack layer. The photoresist curing increases the hardness of the photoresist surface, reduces the line roughness of the photoresist, optimizes the sidewall morphology of the MTJ tunnel junction, eliminates the sidewall damage and defects caused by etching, and improves the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of a method for forming a SOT-MRAM device of the present invention;

[0030] Figure 2 It is a cross-sectional schematic diagram of the SOT layer after the photoresist is patterned in the present invention;

[0031] Figure 3 is a schematic cross-sectional view of the patterned MTJ stacked layer structure of the present invention;

[0032] Figure 4 is a schematic cross-sectional view of the present invention after the dielectric layer is deposited;

[0033] Figure 5 is a schematic cross-sectional view of the patterned deposited dielectric layer of the present invention;

[0034] Figure 6 is a schematic cross-sectional view of the present invention after depositing the electrode layer;

[0035] Figure 7 is a schematic cross-sectional view of the patterned deposited electrode layer of the present invention;

[0036] In the figure, 101 is a substrate, 102 is a SOT layer, 103 is an MTJ stack layer, 104 is an electrode layer, 201 is a photoresist, and 301 is a dielectric layer. DETAILED DESCRIPTION

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] In the description of the present invention, it should be understood that the terms "upper", "lower", "front" and "rear" etc. indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0039] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0040] In this embodiment, combined with Figure 1 As shown in the flowchart of the SOT-MRAM device forming method of the present invention, a SOT-MRAM device forming method includes the following steps:

[0041] Step S1: providing a substrate (101), and depositing a SOT layer (102) on the substrate (101);

[0042] Furthermore, as a preferred embodiment, the SOT layer (102) has a thickness of 5 to 10 nm.

[0043] Step S2: performing photolithography on the SOT layer (102) to pattern a magnetic tunnel junction pattern onto the photoresist (201) above the SOT layer (102);

[0044] Furthermore, as a preferred embodiment, the photoresist (201) has a thickness of 90 nm to 700 nm.

[0045] Specifically, a layer of photoresist (201) with a thickness of 90nm to 700nm is covered on the SOT layer (102), and the desired magnetic tunnel junction pattern is patterned on the photoresist (201), such as Figure 2 shown.

[0046] Step S3: curing the surface of the photoresist (201) to form a cured layer.

[0047] Specifically, the method for curing the surface of the photoresist (201) is ultraviolet irradiation, HBr / Ar reaction, oxidation or nitridation reaction, etc., to form a thin solidified layer, which increases the hardness of the surface of the photoresist (201) and reduces the line roughness of the photoresist (201), so that the pattern of the photoresist (201) can maintain a good sidewall morphology.

[0048] Step S4: depositing an MTJ stacking layer (103) on the SOT layer (102) having the patterned photoresist (201), wherein the MTJ stacking layer (103) starts from the upper surface of the SOT layer (102) and sequentially comprises a free layer, a tunnel junction barrier layer, a reference layer, a pinning layer, and a cover layer from bottom to top;

[0049] Furthermore, as a preferred embodiment, the thickness of the MTJ stack layer (103) is 20 to 40 nm.

[0050] Step S5: using a stripping process to remove the photoresist (201) on the SOT layer (102) and the film stack on the photoresist (201), and retaining the MTJ stack layer (103) deposited on the SOT layer (102);

[0051] Specifically, step S5 adopts a lift-off process to remove the photoresist (201) remaining on the SOT layer (102) and the film stack on the photoresist (201) together, such as Figure 3 As shown, the retained MTJ stacking layer (103) is the required magnetic tunnel junction pattern. Compared with the traditional etching process, the lift-off process is simpler and easier to implement, and no metal deposits will be formed on the sidewalls of the MTJ stacking layer (103) due to etching, thereby avoiding the short circuit problem of the device.

[0052] Step S6: depositing a dielectric layer (301) on the SOT layer (102) and the MTJ stack layer (103), such as Figure 4 As shown;

[0053] Furthermore, as a preferred embodiment, the material of the dielectric layer (301) is any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, or a composite material formed by two or more of the above.

[0054] Furthermore, as a preferred embodiment, the dielectric layer (301) is formed by chemical vapor deposition or atomic layer deposition, and the thickness of the dielectric layer (301) is 40 nm to 200 nm.

[0055] Step S7: performing a patterning process on the dielectric layer (301), etching the dielectric layer (301) with a gas, transferring a desired pattern to the dielectric layer (301), and stopping the etching at the upper surface of the MTJ stack layer (103);

[0056] Furthermore, as a preferred embodiment, the etching gas used in step S7 is one or a mixture of two or more of CF4, CHF3, SF6, and Ar.

[0057] Specifically, different etching gases can be used to etch the dielectric layer (301) according to the different materials used for the dielectric layer (301). In the SOT-MRAM device, the dielectric layer (301) plays the role of insulation isolation. The schematic diagram of the dielectric layer (301) after patterning is as follows: Figure 5 As shown, the opening formed above the SOT layer (102) is used to lead out the bottom electrode, and the opening formed above the MTJ stack layer (103) is used to lead out the top electrode.

[0058] Step S8: depositing an electrode layer (104) on the patterned dielectric layer (301), such as Figure 6 As shown;

[0059] Furthermore, as a preferred embodiment, the material of the electrode layer (104) is an alloy formed by one or more of tantalum, ruthenium, platinum, gold, and chromium.

[0060] Step S9: performing a patterning process on the electrode layer (104), etching the electrode layer (104) with a gas, and transferring a desired pattern to the electrode layer (104) to form a SOT-MRAM device.

[0061] Furthermore, as a preferred embodiment, the etching gas used in step S9 is one or a mixed gas formed by two or more of CF4, CHF3, CCl4, BCl3, Ar, and Kr.

[0062] Specifically, depending on the material used for the electrode layer (104), the electrode layer (104) can be etched using an etching gas such as a fluorine-based, chlorine-based or inert gas. The schematic diagram of the electrode layer (104) after patterning is shown in FIG. Figure 7 As shown, in the SOT-MRAM device, the electrode layer (104) plays the role of transmitting current, wherein the electrode layer (104) formed above the SOT layer (102) is the bottom electrode, and the electrode layer (104) formed above the MTJ stack layer (103) is the top electrode.

[0063] The SOT-MRAM device and its formation method provided by the present invention avoid device open circuit caused by etching of the SOT layer and metal redeposition on the sidewalls of the MTJ stack during the etching process; optimize the sidewall morphology of the MTJ tunnel junction, eliminate sidewall damage and defects caused by etching, and improve the stability of the SOT-MRAM device.

[0064] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for forming a SOT-MRAM device, characterized in that: The following steps are involved: Step S1: providing a substrate and depositing a SOT layer on the substrate; Step S2: performing photolithography on the SOT layer to pattern a magnetic tunnel junction pattern onto the photoresist above the SOT layer; Step S3: performing a curing treatment on the surface of the photoresist to form a cured layer, wherein the curing treatment allows the pattern of the photoresist to maintain a sidewall morphology; Step S4: depositing an MTJ stack layer on the SOT layer having the patterned photoresist, wherein the MTJ stack layer starts from the upper surface of the SOT layer and includes, from bottom to top, a free layer, a tunnel junction barrier layer, a reference layer, a pinning layer, and a capping layer; Step S5: removing the photoresist on the SOT layer and the film stack on the photoresist by a stripping process, and retaining the MTJ stack layer deposited on the SOT layer; Step S6: depositing a dielectric layer on the SOT layer and the MTJ stack layer; Step S7: performing patterning on the dielectric layer, etching the dielectric layer with a gas, transferring the desired pattern to the dielectric layer, and stopping the etching at the upper surface of the MTJ stack layer; Step S8: depositing an electrode layer on the patterned dielectric layer; Step S9: performing patterning on the electrode layer, etching the electrode layer with a gas, and transferring the desired pattern to the electrode layer to form a SOT-MRAM device.

2. The method for forming a SOT-MRAM device according to claim 1, wherein: The thickness of the SOT layer is 5-10 nm.

3. The method for forming a SOT-MRAM device according to claim 1, wherein: The thickness of the photoresist is 90nm to 700nm.

4. The method for forming a SOT-MRAM device according to claim 1, wherein: The thickness of the MTJ stack layer is 20-40 nm.

5. The method for forming a SOT-MRAM device according to claim 1, wherein: The dielectric layer material is any one of silicon oxide, silicon nitride, carbon nitride, silicon carbonitride, silicon oxynitride and aluminum oxide, or a composite material formed by two or more of the above.

6. The method for forming a SOT-MRAM device according to any one of claims 1 or 5, wherein: The dielectric layer is formed by chemical vapor deposition or atomic layer deposition, and the thickness of the dielectric layer is 40nm to 200nm.

7. The method for forming a SOT-MRAM device according to claim 1, wherein: The etching gas used in step S7 is one of CF4, CHF3, SF6, and Ar, or a mixture of two or more thereof.

8. The method for forming a SOT-MRAM device according to claim 1, wherein: The electrode layer material is an alloy formed by one or more of tantalum, ruthenium, platinum, gold and chromium.

9. The method for forming a SOT-MRAM device according to claim 1, wherein: The etching gas used in step S9 is one or a mixture of two or more of CF4, CHF3, CCl4, BCl3, Ar, and Kr.

10. A memory device comprising a SOT-MRAM device, characterized in that: The SOT-MRAM device is manufactured by the method according to any one of claims 1 to 9.

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