An integrated circuit for soft-switching clamping

Abstract

This invention discloses an integrated circuit for soft-switching clamping, comprising a first unit, a second unit, a third unit, a soft-switching clamping unit, and a first transformer. The first unit includes a rectifier and filter circuit for rectifying and filtering AC voltage to obtain a DC bus voltage. The first transformer couples the primary and secondary windings and transfers energy to the secondary winding. The second unit includes a first resistor, a resistor divider, a first switch, a first capacitor, a fifth capacitor, a fourth diode, and a QR controller. The resistor divider includes a second resistor and a third resistor, and transfers energy to the secondary winding by switching the first switch on and off. The first resistor is a current sampling resistor, sampling the current signal and providing it to the QR controller. The resistor divider provides a demagnetizing signal to the QR controller.

Description

Technical Field

[0001] This invention belongs to the field of circuit technology and is used in high-frequency, high-power-density flyback topology. Together with the main switch in QR operating mode, it forms a full-range soft-switching circuit for use in, but not limited to, fast charging or LED lighting, to drive second-generation or third-generation semiconductor MOSFETs. Background Technology

[0002] QR mode flyback topologies are widely used in switching power supplies below 150W, such as in fast charging or LED lighting. A conventional QR flyback primary side includes a main switch MOSFET and an RCD clamping circuit. The main switch Q1 experiences capacitive discharge through C1 during turn-on and hard switching off during turn-off. This is particularly pronounced at high frequencies (above 100kHz), where losses increase significantly with further frequency increases, limiting further increases in operating frequency and hindering the achievement of high power density per unit volume. Simultaneously, the RCD clamping circuit constantly discharges through resistor R, representing a fixed loss and further limiting overall efficiency.

[0003] With the accelerated commercialization of third-generation semiconductors, novel semiconductor devices such as gallium nitride and silicon carbide can only fully realize their superior performance by operating in the high-frequency range. Therefore, developing driving topologies suitable for third-generation semiconductors has become an urgent issue. This invention addresses this problem by providing an alternative solution. Summary of the Invention

[0004] The problem solved by this invention is to provide a soft-switching topology suitable for high-frequency, high-power-density applications, applicable to, but not limited to, driving third-generation semiconductor power devices. To this end, based on the existing flyback QR topology, the original RCD clamping portion is improved and integrated into a single IC to achieve a soft-switching effect.

[0005] To achieve the above objectives, the present invention provides the following technical solution: an integrated circuit for soft-switching clamping, comprising a first unit, a second unit, a third unit, a soft-switching clamping unit, and a first transformer. The first unit includes a rectifier and filter circuit for rectifying and filtering AC voltage to obtain a DC bus voltage. The first transformer couples the primary and secondary windings and transfers energy to the secondary winding. The second unit includes a first resistor, a resistor divider, a first switch, a first capacitor, a fifth capacitor, a fourth diode, and a QR controller. The resistor divider includes a second resistor and a third resistor, and transfers energy to the secondary winding through the switching on and off of the first switch. The first resistor is a current sampling resistor, sampling the current signal and providing it to the QR controller. The resistor divider provides a demagnetizing signal to the QR controller. The fourth diode and the fifth capacitor provide auxiliary power to the QR controller.

[0006] The third unit includes a secondary sampling feedback unit, a fifth diode, and a fourth capacitor. It samples the secondary circuit and provides a control signal to the QR controller through the secondary sampling feedback unit. The QR controller is used to receive the control signal and drive the first switch. The fifth diode and the fourth capacitor are used for secondary rectification and filtering. The soft-switching clamping unit includes a first integrated circuit and a third capacitor. The third capacitor is connected to the drain (D) terminal of the first switch. The other pin of the third capacitor is connected to the third pin of the first integrated circuit. The first pin of the first integrated circuit is connected to the drain (D) terminal of the first switch. The fifth, sixth, seventh, and eighth pins of the first integrated circuit are connected to the DC bus of the first unit's rectification and filtering.

[0007] The technical effects and advantages of the present invention are as follows: The soft-switching clamping circuit provided by the present invention not only realizes the function of the traditional RCD clamping circuit, but also provides zero-voltage turn-on and turn-off conditions for the main switch, and also realizes soft-switching on and off without the need for additional drive and power supply circuits. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating the application of the present invention.

[0009] Figure 2 This is a diagram of the external pins and package of the present invention (SO-8).

[0010] Figure 3 This is the internal circuit diagram of the present invention.

[0011] Figure 4 This is a waveform diagram of the first switch DS of the present invention. Detailed Implementation

[0012] like Figures 1 to 4 As shown, an integrated circuit for soft-switching clamping includes a first unit 10, a second unit 20, a third unit 30, a soft-switching clamping unit 40, and a first transformer T1.

[0013] The first unit 10 includes a rectifier and filter circuit 11, which is used to rectify and filter AC voltage to obtain DC bus voltage.

[0014] The first transformer T1 couples the primary and secondary windings and transfers energy to the secondary winding.

[0015] The second unit 20 includes a first resistor R1, a resistor divider, a first switch Q1, a first capacitor C1, a fifth capacitor C5, a fourth diode D4, and a QR controller 21. The resistor divider includes a second resistor R2 and a third resistor R3. Energy is transferred to the secondary side through the switching of the first switch Q1. The first resistor R1 is a current sampling resistor, which samples the current signal and sends it to the QR controller 21. The resistor divider provides a demagnetizing signal to the QR controller 21. The fourth diode D4 and the fifth capacitor C5 provide auxiliary power to the QR controller 21.

[0016] The third unit 30 includes a secondary sampling feedback unit 31, a fifth diode D5, and a fourth capacitor C4. The secondary sampling feedback unit 31 provides a control signal to the QR controller 21. The QR controller 21 is used to receive the control signal and drive the first switch Q1. The fifth diode D5 and the fourth capacitor C4 are used for secondary rectification and filtering.

[0017] The soft-switching clamping unit 40 includes a first integrated circuit 41 and a third capacitor C3.

[0018] The first integrated circuit 41 includes an internal circuit 50, which includes a first diode D1, a second diode D2, a third diode D3, a second capacitor C2, a second switch Q2, and a first Zener diode ZD1. The second capacitor C2 is connected in series with the input capacitor Ciss2 of the second switch Q2. The first diode D1 provides a reverse recovery path for Ciss2. The second diode D2 can block reverse discharge of Ciss2 before the second switch Q2 needs to be turned off. The third diode D3 provides a reverse recovery path for the second capacitor C2. The first Zener diode ZD1 is connected in parallel between the gate and source terminals of the second switch Q2 to provide clamping protection. The second switch Q2 is connected to pins 5, 6, and 7 of the first integrated circuit 41. And the eighth pin is connected, the source (S) of the second switch Q2 is connected to the third pin of the first integrated circuit 41, the gate (G) of the second switch Q2 is connected to the fourth pin of the first integrated circuit 41, the aperture (A) of the third diode D3 is connected to the source (S) of the second switch Q2, the base (K) of the third diode D3 is connected to the aperture (A) of the second diode D2 and one pin of the second capacitor C2, the other pin of the second capacitor C2 is connected to the base (K) of the first diode D1 and then connected to the first pin of the first integrated circuit 41, the base (K) of the second diode D2, the aperture (A) of the first diode D1 and the base (K) of the first Zener diode ZD1 are connected to the gate (G) of the second switch Q2, and the aperture (A) of the first Zener diode ZD1 is connected to the source (S) of the second switch Q2.

[0019] The fifth pin 5, the sixth pin 6, the seventh pin 7, and the eighth pin 8 of the first integrated circuit 41 are the drain terminals of the second switching transistor Q2 in the internal circuit 50 of the IC, and are connected to the positive terminal of the bus voltage of the first unit 10.

[0020] The third capacitor C3 is connected to the drain (D) terminal of the first switch Q1, and the other terminal of the third capacitor C3 is connected to the third terminal 3 of the first integrated circuit 41. The first terminal 1 of the first integrated circuit 41 is connected to the drain (D) terminal of the first switch Q1.

[0021] The first diode D1 is a 400V withstand voltage ultrafast recovery diode, analog to ES1G.

[0022] The second diode D2 and the third diode D3 are high-frequency switching transistors, analogous to 1N4148.

[0023] The first Zener diode ZD1 is a 27V Zener diode with a maximum power consumption of 500mW.

[0024] The second capacitor C2 is 100pF / 500V.

[0025] The second switch Q2 is a 7A 650V N-channel cool MOSFET with an input capacitance of approximately 433pF between its gate and source (GS), a DS on-resistance of 0.55 ohms (tested at 25°C), a withstand voltage of 650V, a gate-source drive threshold of 2-4V, and a drive limit of + / -30V. All of the above components are packaged within an SO-8 chip. The chip pin definitions are as follows: Pin 1 (CLMP) of the first integrated circuit 41 is connected to the drain (D) of the first switch Q1; Pin 2 (2) of the first integrated circuit 41 is undefined; Pin 3 (3) of the first integrated circuit 41 is the source (S) of the built-in MOSFET, and in actual use, it is connected to one pin of an external clamping capacitor C3. The other pin of the third capacitor C3 is connected to the drain (D) of the first switch Q1.

[0026] The fourth pin 4 is the gate of the built-in MOSFET. When using it, a bypass capacitor should be connected between GT and S depending on the magnitude of the clamping voltage, or it can be left unconnected. When unconnected, the voltage between GT and S is about 1 / 5 of the clamping voltage. When using it, be careful not to let this voltage exceed the 30V peak value, otherwise an additional bypass capacitor must be added between GT and S pins.

[0027] When the internal circuit 50 of the first integrated circuit 41 is actually working, it clamps the first switch Q1 when it is turned off and creates the conditions for soft switching on. The first capacitor C1 is connected in parallel with the first switch Q1. The first capacitor C1 includes the output capacitor of the first switch Q1 and the sum of the two, plus any additional capacitors added if necessary.

[0028] In practical implementation, assuming that at time t0, the voltage across the first capacitor C1 is approximately zero, the QR controller 21 turns on the first switch Q1, and the first transformer T1 begins to store energy until time t1.

[0029] At time t1, the first switch Q1 is turned off. Because of the presence of the first capacitor C1, the first switch Q1 is turned off with zero voltage. Let the primary inductance of the first transformer T1 be Lp = Lm + Ll, where Lm is the primary magnetizing inductance and Ll is the leakage inductance. Then Lp resonates with the first capacitor C1 until time t2.

[0030] At time t2, the voltage between the drain and source terminals of the first switch Q1 rises to the bus voltage Vbus. At this time, the second capacitor C2 and the input capacitor Ciss2 of the second switch Q2 are connected in series and then in parallel with the third capacitor C3. Their equivalent parallel capacitance is then connected in parallel with the first capacitor C1, and they all participate in resonance. At this time, the body diode of the second switch Q2 turns on and begins to conduct, which is a zero-voltage turn-on. As the voltage of Ciss2 rises to the conduction threshold of the second switch Q2, the second switch Q2 turns on with zero voltage, preparing for the subsequent process, until time t3.

[0031] At time t3, the voltage between the primary and secondary terminals of the first switch Q1 reaches Vds = Vbus + n*Vo (Vo is the output voltage, and n is the primary-secondary turns ratio). Energy stored in the primary inductor begins to transfer to the secondary. At this time, the inductor Lm of the first transformer T1 is clamped by the secondary, leaving only the leakage inductance Ll resonating with the equivalent capacitance of the first capacitor C1 / / the third capacitor C3 / / (the second capacitor C2 + Ciss2). The voltage surges rapidly, then drops back to Vds = Vbus + n*Vo at time t4. This voltage is maintained for energy transfer until time t5.

[0032] At time t5, since energy transfer is complete and the secondary side is disconnected from the circuit, and because the second switch Q2 was previously turned on, the equivalent capacitance of the first capacitor C1 / / the third capacitor C3 / / the second capacitor C2 begins to resonate with the primary inductance Lp (=Lm+Ll), transferring energy from the first capacitor C1, the second capacitor C2, and the third capacitor C3 to Lp. During this process, Ciss2 is blocked by the second diode D2, maintaining its initial voltage until Vciss2 (voltage on the input capacitor of the second switch Q2) = VC3 (voltage on the third capacitor C3), where the third diode D3 provides a reverse recovery path for the second capacitor C2. When Vciss2 = VC3, the equivalent capacitance of Ciss2 / / the first capacitor C1 / / the second capacitor C2 / / the third capacitor C3 begins to resonate with Lp, where the first diode D1 provides a path for Ciss2 (this is only to clarify the resonance process; the influence of Ciss2 is ignored in actual calculations to simplify the calculation process). This process continues until time t6.

[0033] At time T6, when the voltage V(ciss2) is less than the threshold voltage Vth of the second switch Q2, the second switch Q2 is turned off. Because Vth is very small, it is turned off at approximately zero voltage. At this time, Ciss2, the second capacitor C2, and the third capacitor C3 are disconnected from the circuit, and their energy is transferred to Lp. Lp and the first capacitor C1 continue to resonate until time t7.

[0034] At time t7, there are two possibilities: either the current in Lp decreases to zero and the voltage Vds is also approximately zero, in which case turning on the first switch Q1 results in zero-voltage turn-on; or the current in Lp is not zero, and the anti-parallel diode of the first switch Q1 turns on, also resulting in zero-voltage turn-on. This process continues into the next cycle. By appropriately selecting parameters to ensure the system operates primarily in the first scenario, conduction losses and duty cycle loss can be minimized.

[0035] Mode 1 (t0-t1): Assume that at time t0, the voltage Vds reaches its minimum value Vlow, and the inductor current is 0. At this time, the first switch Q1 is turned on (ZVZC turn-on). At time t1, the first switch Q1 is turned off because the first capacitor C1 is present, and the first switch Q1 is turned off at zero voltage. Let ton = t1 - t0, and the inductor current Ipeak at time t1 be...

[0036] Vbus*ton=Lp*Ipeak------ (1)

[0037] We get ton = t1 - t0 = Lp * Ipeak / Vbus

[0038] Mode 2 (t1-t2): From time t1 to time t2, Lp resonates with the first capacitor C1. At time t2, the voltage Vds of the first switch Q1 is Vbus. Let tr1 = t2 - t1, because the first capacitor C1 is rapidly charged, it can be approximated as being charged to Vbus by a constant current Ipeak.

[0039] C1*Vbus=Ipeak*tr1------- (2)

[0040] We get tr1 = t2 - t1 = C1 * Vbus / Ipeak

[0041] Mode 3 (t2-t3): At time t2, after the voltage Vds of the first switch Q1 reaches Vbus, the equivalent capacitance of the second capacitor C2 connected in series with Ciss2 and the third capacitor C3 are connected in parallel and resonate together with the first capacitor C1. Due to parameter settings, Ciss has a small influence and is ignored for ease of analysis. Moreover, for a given mode, if the start time is set to zero, the initial state of the mode corresponds to the initial state at time 0, which does not affect the analysis. Therefore, let time t2 correspond to time 0 at the start of mode 3. Then, for any time t∈(0, t3-t2), the inductor current is iL(t), the inductor voltage is uL(t), the voltage on the third capacitor C3 is uC3(t), the voltage on the first capacitor C1 is uC1(t), and iL(0)=Ipeak, uL(0)=0, uc3(0)=0, uc1(0)=Vbus. At time t3, uL(t3-t2) = -VRF = -n*Vo, where n is the transformer turns ratio and Vo is the output voltage.

[0042] uL(t)=Lp*d(iL(t)) / d(t) ---(3)

[0043] iL(t)=(C2+C3)*d(uc3(t)) / d(t)+C1*d(uc1(t)) / d(t) ----(4)

[0044] Where, uL(t) = -uc3(t) ---- (5)

[0045] uC1(t)=Vbus-uL(t) ----(6)

[0046] Substituting (5) and (6) into the above equation, we get...

[0047] iL(t)=-(C1+C2+C3)*d(uL(t)) / d(t) ----(7)

[0048] uL(t)=-Lp*(C1+C2+C3)*d(uL(t))” / d(t) ---(8)

[0049] Solving the above differential equation yields

[0050] uL(t)=A1*cos(ω1*t)+A2*sin(ω1*t) ---(9)

[0051] ω1=(Lp*(C1+C2+C3))^(-1 / 2),

[0052] Where A1 and A2 are undetermined coefficients.

[0053] When t=0, uL(0)=0, iL(0)=Ipeak, substituting these values, we get A1=0, A2=-Ipeak / [(C1+C2+C3)*ω1].

[0054] =-Ipeak*[Lp / (C1+C2+C3)]^(1 / 2)

[0055] =-Ipeak*Z0

[0056] Where Z0=[Lp / (C1+C2+C3)]^(1 / 2) is the characteristic impedance of the line.

[0057] Therefore, we obtain

[0058] iL(t)=Ipeak*cos(ω1*t) -----(10)

[0059] uL(t)=-Ipeak*Z0*sin(ω1*t) -----(11)

[0060] Therefore, the voltage and current at time t∈(0, t3-t2) and t=t3-t2 are...

[0061] iL(t3-t2)=Ipeak*cos[ω1*(t3-t2)]

[0062] uL(t3-t2)=-Ipeak*Z0*sin[ω1*(t3-t2)]

[0063] In this mode, because the second capacitor C2 and Ciss2 are connected in series, when the voltage on Ciss2 resonates to the turn-on threshold of the second switch Q2, the second switch Q2 turns on, preparing for the subsequent mode.

[0064] Mode 4 (t3-t4): This mode is the spike clamping stage, determining the maximum stress on the first switch Q1. At time t3, because the voltage on the primary inductor has reached the reflected voltage VRF = n*Vo, Lm is disengaged due to secondary clamping, and only L1 and the parallel equivalent capacitance of the first capacitor C1 / second capacitor C2 / third capacitor C3 resonate. By time t4, the voltage on Lp returns to VRF, and the voltage on the leakage inductance is 0. Similarly, as mentioned above, for t∈(0, t4-t3), we have

[0065] uLl(t)-VRF=-uc3(t) ----(12)

[0066] iLl(t)=(C1+C2+C3)*d(uc3(t)) / dt

[0067] =-(C1+C2+C3)*d(uLl(t)) / dt ---(13)

[0068] uLl(t)=Ll*d(iLl(t)) / dt ----(14)

[0069] Substituting (13) into (14) further yields

[0070] uLl(t)=-Ll*(C1+C2+C3)*d[ul(t)]” / dt

[0071] Where, iLl(0) = iL(t3-t2) = Ipeak*cos(ω1*(t3-t2))

[0072] Solving the above three equations, we get

[0073] uLl(t)=A11*cos(ω2*t)+A22*sin(ω2*t) ----(15)

[0074] Where A11 and A22 are undetermined coefficients. ω2=Ll*(C1+C2+C3))^(-1 / 2)

[0075] Substituting (15) into iLl(t) = -(C1+C2+C3)*d(uLl(t)) / dt, we get

[0076] iLl(t)=-(C1+C2+C3)*[A22*ω2*cos(ω2*t)-A11*ω2*sin(ω2*t)]

[0077] ---(16)

[0078] When t=0, uLl(0))=0, iLl(0)=Ipeak*cos(ω1*(t3-t2)).

[0079] We obtain A11=0, A22=-Ipeak*cos(ω1*(t3-t2)) / [(C1+C2+C3)*ω2]=-Ipeak*cos(ω1*(t3-t2))*Z01, where Z01=[Ll / (C1+C2+C3)]^(1 / 2), which is the characteristic impedance of the circuit at this time.

[0080] Therefore, we obtain

[0081] uLl(t)=-Ipeak*cos(ω1*(t3-t2))*Z01*sin(ω2*t)

[0082] iLl(t)=Ipeak*cos(ω1*(t3-t2))*cos(ω2*t)

[0083] Discussion: When d(uLl(t)) / dt=0, uLl(t) reaches its maximum value, resulting in ω2*ta=π / 2, and thus ta=π / (2*ω2). t4-t3=2*ta=π / ω2.

[0084] uLl(ta)=-Ipeak*cos[ω2*(t3-t2)]*Z01

[0085] Mode 5 (t4-t5): This mode is the flyback energy transfer stage. It can be simply derived from the volt-second balance equation.

[0086] n*Vo*(t5-t4)=Vbus*(t3-t2) ----- (17)

[0087] We get t5-t4=Vbus*(t3-t2) / [n*Vo*(t5-t4)]

[0088] In this mode, uC3(t) = -uL(t) = -n*Vo is clamped until time t5.

[0089] Mode 6 (t5-t6): At time t5, energy transfer in the first transformer T1 is complete. Because the second switch Q2 in Mode 3 has already turned on, the first capacitor C1, the second capacitor C2, and the third capacitor C3 resonate with Lp, and energy begins to transfer in the reverse direction to Lp until time t6, when the voltage of the third capacitor C3 becomes 0. At this time, the second switch Q2 turns off, and the second capacitor C2 and the third capacitor C3 are disconnected from the resonant circuit. For t∈(0, t6-t5), we have

[0090] uC3(t)=-uL(t) ----(18)

[0091] iL(t)=(C1+C2+C3)*d(uC3(t)) / dt ----(19)

[0092] uL(t)=Lp*d(iL(t)) / dt ----(20)

[0093] get

[0094] uL(t)=-Lp*(C1+C2+C3)*d(uL(t))” / dt ----(21)

[0095] Solving equation (21) yields

[0096] uL(t)=B1*cos(ω1*t)+B2*sin(ω1t) ----(22)

[0097] iL(t)=-(C1+C2+C3)*[B2*ω1*cos(ω1*t)-B1*ω1*sin(ω1*t)]----(23)

[0098] Where B1 and B2 are undetermined constants, and ω1=[Lp*(C1+C2+C3)]^(-1 / 2)

[0099] Substituting iL(0) = 0 and uL(0) = -VRF = -n*Vo at t = 0 into (22) and (23) we get

[0100] B1=-n*Vo, B2=0

[0101] Then uL(t)=-n*Vo*cos(ω1*t)-----(24)

[0102] At time t6, uC3(t6-t5)=0, then ω1*(t6-t5)=π / 2, thus obtaining...

[0103] t6-t5=π / (2*ω1)

[0104] iL(π / (2*ω1))=-(C1+C2+C3)*(n*Vo*ω1)

[0105] =-n*Vo / Z0,

[0106] Where Z0=[Lp / (C1+C2+C3)]^(1 / 2) is the characteristic impedance of the line, and a negative value indicates that the current direction is opposite to the set direction.

[0107] Mode 7 (t6-t7): Second resonance stage. As mentioned above, at time t6, the second capacitor C2 and the third capacitor C3 disconnect from the system, leaving only Lp resonating with the first capacitor C1. During this stage, for t∈(0, t7-t6)...

[0108] Vbus=uL(t)+uC1(t) -----(25)

[0109] uL(t)=Lp*d(iL(t)) / dt -----(27)

[0110] iL(t)=C1*d(uC1(t)) / dt ----(28)

[0111] From the above three equations, we can obtain

[0112] uL(t)=-Lp*C1*d(uL(t))” / dt ----(29)

[0113] Therefore, we obtain

[0114] uL(t)=B11*cos(ω3*t)+B22*sin(ω3*t) ----(30)

[0115] iL(t)=-C1*[B22*ω3*cos(ω3*t)-B11*ω3*sin(ω3*t)]

[0116] Where B11 and B22 are undetermined constants, and ω3 = (Lp*C1)^(-1 / 2),

[0117] From the initial state, at t=0, corresponding to time t6, we can obtain from the previous mode...

[0118] uL(0) = 0, iL(0) = -n*Vo / Z0, thus obtaining

[0119] B11=0,B22=n*Vo / (Z0*C1*ω3)=n*Vo*Z02 / Z0, where Z02=(Lp / C1)^(1 / 2),

[0120] get

[0121] uL(t)=n*Vo*Z02 / Z0*sin(ω3*t)---(31)

[0122] iL(t)= -(n*Vo / Z0)*cos(ω3*t)

[0123] discuss:

[0124] A. At time t7, uC1(t7-t6) = 0, from which we obtain

[0125] uL(t7-t6)=n*Vo*Z02 / Z0*sin[ω3*(t7-t6)]=Vbus,

[0126] We get t7-t6=arcsin[(Vbus*Z0) / (n*Vo*Z02)] / ω3

[0127] B. At time t7, iL(t7-t6)=0, so ω3*(t7-t6)=π / 2.

[0128] (t7-t6)=π / (2*ω3)

[0129] uL(t7-t6) = n*Vo*Z02 / Z0, therefore

[0130] uC1(t)=Vbus-uL(t7-t6)=Vbus- n*Vo*Z02 / Z0.

Claims

1. An integrated circuit for soft-switching clamping, characterized in that: It includes the first unit, the second unit, the third unit, the soft-switching clamping unit, and the first transformer. The first unit includes a rectifier and filter circuit, which is used to rectify and filter the AC voltage to obtain the DC bus voltage. The first transformer couples the primary and secondary windings and transfers energy to the secondary winding. The second unit includes a first resistor, a resistor divider, a first switch, a first capacitor, a fifth capacitor, a fourth diode, and a QR controller. The resistor divider includes a second resistor and a third resistor. Energy is transferred to the secondary side through the switching on and off of the first switch. The first resistor is a current sampling resistor, sampling the current signal and sending it to the QR controller. The resistor divider provides a demagnetizing signal to the QR controller. The fourth diode and the fifth capacitor provide auxiliary power to the QR controller. The third unit includes a secondary sampling feedback unit, a fifth diode, and a fourth capacitor. It samples the secondary circuitry and provides control signals to the QR controller via the secondary sampling feedback unit. The QR controller receives the control signals and drives the first switch. The fifth diode and the fourth capacitor are used for secondary rectification and filtering. The soft-switching clamping unit includes a first integrated circuit and a third capacitor. The third capacitor is connected to the drain (D) terminal of the first switch, and the other terminal of the third capacitor is connected to the third terminal of the first integrated circuit. The first terminal of the first integrated circuit is connected to the drain (D) terminal of the first switch, and the fifth, sixth, seventh, and eighth terminals of the first integrated circuit are connected to the DC bus of the first unit's rectifier and filter.

2. The integrated circuit for soft-switching clamping according to claim 1, characterized in that: The first integrated circuit includes internal IC circuitry, which includes a first diode, a second diode, a third diode, a second capacitor, a second switching transistor, and a first Zener diode. The second capacitor is connected in series with the input capacitor Ciss2 of the second switching transistor. The first diode provides a reverse recovery path for Ciss2. The second diode can block reverse discharge of Ciss2 before the second switching transistor needs to be turned off. The third diode provides a reverse recovery path for the second capacitor. The first Zener diode is connected in parallel between the gate and source terminals of the second switching transistor to provide clamping protection.

3. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The drain (D) of the second switching transistor is connected to pins 5, 6, 7, and 8 of the first integrated circuit. The source (S) of the second switching transistor is connected to pin 3 of the first integrated circuit. The gate (G) of the second switching transistor is connected to pin 4 of the first integrated circuit. The aperture (A) of the third diode is connected to the source (S) of the second switching transistor. The base (K) of the third diode is connected to the aperture (A) of the second diode and one pin of the second capacitor. The other pin of the second capacitor is connected to the base (K) of the first diode and then connected together to pin 1 of the first integrated circuit. The base (K) of the second diode, the aperture (A) of the first diode, and the base (K) of the first Zener diode are connected together to the gate (G) of the second switching transistor. The aperture (A) of the first Zener diode is connected to the source (S) of the second switching transistor.

4. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The first diode is a 400V withstand voltage ultrafast recovery diode.

5. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The second diode and the third diode are high-frequency switching transistors.

6. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The first Zener diode is a 27V Zener diode with a maximum power consumption of 500mW.

7. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The second switching transistor is a 7A 650V N-channel cool MOSFET.

8. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The second pin of the first integrated circuit is undefined.

9. The integrated circuit for soft-switching clamping according to claim 2, characterized in that: The fourth pin of the first integrated circuit is the gate of the built-in MOSFET. When in use, a capacitor is bypassed between pins 4 and 3 or left unconnected, depending on the magnitude of the clamping voltage.

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