A low-loss substrate and method of manufacture

Abstract

The application discloses a low-loss substrate and a preparation method thereof, wherein the low-loss substrate comprises a substrate layer and a first defect layer on the substrate layer; a second defect layer is arranged on the side of the first defect layer away from the substrate layer, the surface of the second defect layer has a convex structure, and the height of the convex structure is a preset height; in the case that the first defect layer and / or the second defect layer is generated by double-sided deposition, an incomplete thermal oxidation is performed, a stress adjustment layer is obtained on the side of the substrate layer away from the first defect layer, a first oxide layer is obtained on the side of the second defect layer away from the first defect layer, and the density of the first oxide layer is a preset density; and a piezoelectric single crystal layer is arranged on the side of the first oxide layer away from the second defect layer. The low-loss substrate improves the overall appearance of a wafer by adjusting the thickness of the stress adjustment layer. In addition, the grain size of the second defect layer is large, and the oxide layer structure obtained from the second defect layer is more dense, which is beneficial to the bonding of the piezoelectric single crystal layer and the oxide layer.

Description

Technical Field

[0001] This application relates to the field of surface acoustic wave filters, and in particular to a low-loss substrate and its fabrication method. Background Technology

[0002] Surface acoustic wave (SAW) filters are widely used in radio frequency (RF) front-ends. To reduce RF losses and improve device performance, high-resistivity silicon is often chosen as the substrate material. When the oxide insulating layer is in direct contact with the high-resistivity silicon substrate, a conductive layer is induced at the interface under high-frequency conditions, known as parasitic surface conductance (PSC). To mitigate the adverse effects of PSC, existing technologies incorporate a polycrystalline silicon carrier trapping layer between the high-resistivity silicon substrate and the oxide layer. This layer utilizes grain boundaries in the polycrystalline silicon to pin the mobile carriers in the PSC layer, thereby restoring the high-resistivity characteristics of the substrate.

[0003] However, adding polysilicon has certain negative impacts. On the one hand, the grown polysilicon has a large surface roughness, making bonding difficult. On the other hand, the polysilicon layer deposited on the silicon substrate will generate unwanted internal stress, resulting in poor substrate morphology and affecting subsequent processes. Summary of the Invention

[0004] This application provides a low-loss substrate and its preparation method, which can at least improve the problems of difficult bonding and poor substrate structure morphology.

[0005] This invention provides a low-loss substrate, comprising:

[0006] A substrate layer and a first defect layer located on the substrate layer; a second defect layer is provided on the side of the first defect layer away from the substrate layer, and the surface of the second defect layer has a protrusion structure with a preset height.

[0007] In the case where the first defect layer and / or the second defect layer are formed by double-sided deposition, after incomplete thermal oxidation, a stress adjustment layer is obtained on the side of the substrate layer away from the first defect layer, and a first oxide layer is obtained on the side of the second defect layer away from the first defect layer, with the density of the first oxide layer being a preset density.

[0008] A piezoelectric single crystal layer is provided on the side of the first oxide layer away from the second defect layer.

[0009] Optionally, when the first defect layer is formed by double-sided deposition, the stress adjustment layer includes a third defect layer and a second oxide layer; the third defect layer is the structure corresponding to the first defect layer, and the second oxide layer is the structure obtained by incomplete thermal oxidation of part of the third defect layer;

[0010] When the second defect layer is generated by double-sided deposition, the stress adjustment layer includes a fourth defect layer and a third oxide layer; the fourth defect layer is the structure corresponding to the second defect layer, and the third oxide layer is the structure obtained by incomplete thermal oxidation of part of the fourth defect layer.

[0011] When both the first and second defect layers are formed by double-sided deposition, the stress adjustment layer includes a third defect layer, a fourth defect layer, and a third oxide layer.

[0012] Optionally, the substrate material includes monocrystalline silicon; the resistivity of the substrate is not less than 1000 ohm-cm.

[0013] Optionally, the materials of the first defect layer and the second defect layer include polycrystalline silicon; the polycrystalline silicon grains have a columnar structure.

[0014] Optionally, the grain size of the second defect layer is larger than that of the first defect layer.

[0015] Optionally, the thickness of the first defect layer is 800-1000 nanometers; the thickness of the second defect layer is 400-600 nanometers; and the thickness of the first oxide layer is 400-600 nanometers.

[0016] This invention provides a method for fabricating a low-loss substrate, comprising:

[0017] At a first temperature, a first defect layer is grown on the substrate layer;

[0018] At a second temperature, a second defect layer is grown on the first defect layer to obtain a defect wafer; the first defect layer and / or the second defect layer are formed by double-sided deposition.

[0019] At the third temperature, the defective wafer is subjected to incomplete thermal oxidation to obtain a stress adjustment layer on the side of the substrate layer away from the first defect layer and a first oxide layer on the side of the second defect layer away from the first defect layer.

[0020] A piezoelectric single crystal layer is grown on the first oxide layer to obtain a bonding structure;

[0021] Adjusting the thickness of the stress adjustment layer improves the morphology of the bonding structure, regulates the internal stress of the wafer, and obtains a low-loss substrate.

[0022] Optionally, when the first defect layer is generated by double-sided deposition, a third defect layer corresponding to the first defect layer is obtained. At this time, the defect wafer includes a third defect layer, a substrate layer, a first defect layer, and a second defect layer stacked sequentially. After incomplete thermal oxidation, part of the third defect layer generates a second oxide layer. At this time, the stress adjustment layer includes the third defect layer and the second oxide layer.

[0023] When the second defect layer is generated by double-sided deposition, a fourth defect layer corresponding to the second defect layer is obtained. At this time, the defect wafer includes a fourth defect layer, a substrate layer, a first defect layer, and a second defect layer stacked in sequence. After incomplete thermal oxidation, a third oxide layer is generated in part of the fourth defect layer. At this time, the stress adjustment layer includes the fourth defect layer and the third oxide layer.

[0024] When both the first and second defect layers are generated by double-sided deposition, the defect wafer includes a fourth defect layer, a third defect layer, a substrate layer, a first defect layer, and a second defect layer stacked sequentially; after incomplete thermal oxidation, the stress adjustment layer includes a third defect layer, a fourth defect layer, and a third oxide layer.

[0025] Optionally, the first temperature is 550-640 degrees Celsius; the second temperature is 650-750 degrees Celsius; and the third temperature is 900-1100 degrees Celsius.

[0026] Alternatively, methods for growing piezoelectric single crystal layers include ion beam stripping and transfer or bonding polishing.

[0027] The beneficial effects of this invention are as follows: First, at least one of the first and second defect layers is formed by double-sided deposition. Incomplete thermal oxidation on this basis allows for the formation of a stress-adjusting layer on the side of the substrate layer furthest from the piezoelectric single-crystal layer. This allows for adjustment of the internal stress of the wafer by adjusting the thickness of the stress-adjusting layer, thereby improving the overall wafer morphology. Second, the second defect layer has a larger grain size and fewer grain boundaries than the first defect layer. The oxide layer structure obtained from the second defect layer through incomplete thermal oxidation is more compact, which is beneficial for bonding between the piezoelectric single-crystal layer and the oxide layer, reducing device losses. Third, the rough surface of the second defect layer can suppress the generation of clutter in surface acoustic wave devices. Attached Figure Description

[0028] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a low-loss substrate provided in an embodiment of the present invention;

[0030] Figure 2 This is a transmission electron microscope image of a local structure of a low-loss substrate provided in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of another low-loss substrate provided in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of another low-loss substrate provided in an embodiment of the present invention;

[0033] Figure 5 This is a schematic flowchart of a low-loss substrate fabrication method provided in an embodiment of the present invention;

[0034] Figure 6(a) is a structural diagram of a wafer provided in an embodiment of the present invention;

[0035] Figure 6(b) is another structural diagram of a wafer provided in an embodiment of the present invention;

[0036] Figure 6(c) is another structural diagram of a wafer provided in an embodiment of the present invention;

[0037] Figure 7(a) is a structural diagram of another wafer provided in an embodiment of the present invention;

[0038] Figure 7(b) is another structural diagram of another wafer provided in an embodiment of the present invention;

[0039] Figure 7(c) is another structural diagram of another wafer provided in an embodiment of the present invention;

[0040] The corresponding labels in the figure are: 1-substrate layer; 2-first defect layer; 3-second defect layer; 4-stress adjustment layer; 5-first oxide layer; 6-piezoelectric single crystal layer; 21-third defect layer; 31-fourth defect layer; 211-second oxide layer; 311-third oxide layer; 101-defect wafer; 102-bonding structure; 103-low loss substrate. Detailed Implementation

[0041] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0043] Example 1

[0044] Please see Figure 1 , Figure 1 This is a schematic diagram of a low-loss substrate provided in an embodiment of the present invention. The low-loss substrate includes a substrate layer 1 and a first defect layer 2 located on the substrate layer 1. The substrate layer 1 is made of monocrystalline silicon, and its resistivity is not less than 1000 ohm-cm. A second defect layer 3 is provided on the side of the first defect layer 2 away from the substrate layer 1. Both the first defect layer 2 and the second defect layer 3 are made of polycrystalline silicon with columnar grains, the difference being that the second defect layer 3 has a larger grain size than the first defect layer 2. Optionally, the grain size of the first defect layer 2 is 10-150 nanometers, and the grain size of the second defect layer 3 is 150-300 nanometers. Due to the larger grain size, for a given volume, the number of grains in the second defect layer 3 is relatively fewer, and the number of grain boundaries (the interface between two adjacent grains) is also correspondingly fewer.

[0045] When the first defect layer 2 and / or the second defect layer 3 are formed by double-sided deposition, a stress adjustment layer 4 is obtained on the side of the substrate layer 1 away from the first defect layer 2 after incomplete thermal oxidation, and a first oxide layer 5 is obtained on the side of the second defect layer 3 away from the first defect layer 2. Optionally, the thickness of the first defect layer 2 is 800-1000 nm, the thickness of the second defect layer 3 is 400-600 nm, and the thickness of the first oxide layer 5 is 400-600 nm. In addition, a piezoelectric single crystal layer 6 is provided on the side of the first oxide layer 5 away from the second defect layer 3. Optionally, the material of the piezoelectric single crystal layer 6 includes lithium niobate (LN) or lithium tantalate (LT).

[0046] Because the second defect layer 3 has a larger grain size and fewer grain boundaries than the first defect layer 2, the first oxide layer 5 obtained by incomplete thermal oxidation of part of the second defect layer 3 will be more dense. The density of the first oxide layer 5 is a preset density, optionally 2190-2270 kg / m³. The dense first oxide layer 5 is beneficial for bonding with the piezoelectric single crystal layer 6 and can also reduce device losses.

[0047] like Figure 2 As shown, the surface of the second defect layer 3 has an undulating protrusion structure, the height of which is a preset height. Optionally, the preset height is 10-100 nanometers. When the low-loss substrate provided in this embodiment of the invention is used as a surface acoustic wave device, the leakage acoustic waves from the piezoelectric single crystal layer 6 will be reflected at the smooth interface between the substrate layer 1 and the first defect layer 2, forming a parasitic mode, which will interfere with the device of the piezoelectric single crystal layer 6. The rough surface of the second defect layer 3 can scatter these leakage acoustic waves, thereby suppressing the generation of clutter in the surface acoustic wave device.

[0048] Since at least one of the first defect layer 2 and the second defect layer 3 is obtained by double-sided deposition, in one embodiment, when the first defect layer 2 is generated by double-sided deposition, the stress adjustment layer 4 includes a third defect layer 21 and a second oxide layer 211, wherein the third defect layer 21 is the structure corresponding to the first defect layer 2, and the second oxide layer 211 is the structure obtained by partially thermally oxidizing the third defect layer 21.

[0049] As another implementation method, such as Figure 3 As shown, when the second defect layer 3 is formed by double-sided deposition, the stress adjustment layer 4 includes a fourth defect layer 31 and a third oxide layer 311, wherein the fourth defect layer 31 is the structure corresponding to the second defect layer 3, and the third oxide layer 311 is the structure obtained by partially thermally oxidizing the fourth defect layer 31.

[0050] As another implementation method, such as Figure 4 As shown, when both the first defect layer 2 and the second defect layer 3 are formed by double-sided deposition, the stress adjustment layer 4 includes a third defect layer 21, a fourth defect layer 31 and a third oxide layer 311.

[0051] Regardless of the composition of the stress adjustment layer 4, its purpose remains the same: to balance the internal stress of the low-loss substrate by adjusting the thickness of the stress adjustment layer 4, thereby ultimately improving the morphology of the low-loss substrate.

[0052] Example 2

[0053] This invention provides a method for preparing a low-loss substrate. Figure 5 The preparation method shown includes:

[0054] S501: At the first temperature, a first defect layer 2 is grown on the substrate layer 1.

[0055] In one implementation method, the single-crystal silicon substrate 1 is first cleaned to obtain a smooth surface. Then, silicon tetrahydrogenate gas and nitrogen gas are introduced under a first temperature and a first pressure to grow a first defect layer 2 with a thickness of 800-1000 nanometers on the substrate 1 with a smooth surface.

[0056] Optionally, the first temperature is 550-640 degrees Celsius, and the first pressure is 0.2-0.4 Torr.

[0057] S502: At the second temperature, a second defect layer 3 is grown on the first defect layer 2 to obtain a defect wafer 101; the first defect layer 2 and / or the second defect layer 3 are generated by double-sided deposition.

[0058] In one implementation, silicon tetrahydrogenase gas and nitrogen gas are introduced at a second temperature and a second pressure, thereby growing a second defect layer 3 with a thickness of 400-6000 nanometers on the first defect layer 2.

[0059] Specifically, "the first defect layer 2 and / or the second defect layer 3 are formed by double-sided deposition" includes three cases. The first case is that when the first defect layer 2 is formed by double-sided deposition, a third defect layer 21 corresponding to the first defect layer 2 is obtained, as shown in Figure 6(a). At this time, the defect wafer 101 includes the third defect layer 21, the substrate layer 1, the first defect layer 2 and the second defect layer 3, which are stacked in sequence.

[0060] The second type: When the second defect layer 3 is generated by double-sided deposition, a fourth defect layer 31 corresponding to the second defect layer 3 is obtained, as shown in Figure 6(b). At this time, the defect wafer 101 includes the fourth defect layer 31, the substrate layer 1, the first defect layer 2 and the second defect layer 3 stacked in sequence.

[0061] The third type: When the first defect layer 2 and the second defect layer 3 are both generated by double-sided deposition, a third defect layer 21 corresponding to the first defect layer 2 is obtained, and a fourth defect layer 31 corresponding to the second defect layer 3 is also obtained, as shown in Figure 6(c). At this time, the defect wafer 101 includes the fourth defect layer 31, the third defect layer 21, the substrate layer 1, the first defect layer 2, and the second defect layer 3 stacked in sequence.

[0062] Optionally, the second temperature is 650-750 degrees Celsius, and the second pressure is 0.2-0.4 Torr. The second temperature is higher than the first temperature, so that the grain size of the second defect layer 3 is larger than the grain size of the first defect layer 2.

[0063] S503: At a third temperature, the defective wafer 101 is subjected to incomplete thermal oxidation to obtain a stress adjustment layer 4 on the side of the substrate layer 1 away from the first defect layer 2, and a first oxide layer 5 on the side of the second defect layer 3 away from the first defect layer 2.

[0064] Optionally, the third temperature is 900-1100 degrees Celsius, and the thickness of the first oxide layer 5 is 500-600 mm.

[0065] Corresponding to the three composition scenarios of the defective wafer 101 described above, the stress adjustment layer 4 also has three composition scenarios. First scenario: When the defective wafer 101 includes a third defect layer 21, a substrate layer 1, a first defect layer 2, and a second defect layer 3 stacked sequentially, after incomplete thermal oxidation, part of the third defect layer 21 generates a second oxide layer 211, as shown in Figure 7(a). In this case, the stress adjustment layer 4 includes the third defect layer 21 and the second oxide layer 211.

[0066] The second type: When the defective wafer 101 includes a fourth defect layer 31, a substrate layer 1, a first defect layer 2 and a second defect layer 3 stacked in sequence, after incomplete thermal oxidation, part of the fourth defect layer 31 generates a third oxide layer 311, as shown in Figure 7(b). At this time, the stress adjustment layer 4 includes the fourth defect layer 31 and the third oxide layer 311.

[0067] The third type: When the defective wafer 101 includes a fourth defect layer 31, a third defect layer 21, a substrate layer 1, a first defect layer 2, and a second defect layer 3 stacked in sequence, after incomplete thermal oxidation, part of the fourth defect layer 31 generates a third oxide layer 311, as shown in Figure 7(c). At this time, the stress adjustment layer 4 includes the third defect layer 21, the fourth defect layer 31, and the third oxide layer 311.

[0068] S504: A piezoelectric single crystal layer 6 is grown on the first oxide layer 5 to obtain a bonding structure 102.

[0069] Optionally, methods for growing the piezoelectric single crystal layer 6 include ion beam stripping and transfer or bonding polishing.

[0070] Specifically, ion beam stripping and transfer includes:

[0071] The first step involves ion implantation into the piezoelectric single-crystal wafer to form a defect layer within it. The energy of the implanted ions is 20-2000 kiloelectron volts, and the dose of the implanted ions is 1 eV. 15 -1e 17Ions / square centimeter. The types of implanted ions include hydrogen ions and / or helium ions. When the material of the piezoelectric single crystal layer 6 is lithium niobate (i.e., the piezoelectric single crystal wafer is a lithium niobate wafer), helium ions are implanted. When the material of the piezoelectric single crystal layer 6 is lithium tantalate (i.e., the piezoelectric single crystal wafer is a lithium tantalate wafer), any one of the following can be used: implanting helium ions, implanting hydrogen ions, or implanting both hydrogen ions and helium ions simultaneously.

[0072] The second step is to bond the piezoelectric single crystal wafer to the first oxide layer 5.

[0073] The third step involves heat-treating the structure formed by bonding the piezoelectric single crystal wafer to the first oxide layer 5, so that the piezoelectric single crystal wafer is peeled off along the defect layer to form the piezoelectric single crystal layer 6. Optionally, the heat treatment temperature is 100-300 degrees Celsius.

[0074] Specifically, bond polishing includes:

[0075] The first step is to provide a piezoelectric single crystal wafer and bond the piezoelectric single crystal wafer to the first oxide layer 5.

[0076] The second step is to prepare a piezoelectric single crystal layer 6 by grinding and thinning.

[0077] S505: Adjust the thickness of the stress adjustment layer 4 to improve the morphology of the bonding structure 102, adjust the internal stress of the wafer, and obtain a low-loss substrate 103.

[0078] The methods for adjusting the thickness of the stress adjustment layer 4 include grinding to reduce the thickness or chemical mechanical polishing (CMP).

[0079] Specifically, grinding and thinning include:

[0080] In the first case: when the ideal wafer morphology can be obtained without adjusting the thickness of the stress adjustment layer 4 too much, the thickness of the oxide layer can be adjusted, and the adjustment range is 0-600 mm.

[0081] Specifically, when the stress adjustment layer 4 includes the third defect layer 21 and the second oxide layer 211, "adjusting the thickness of the oxide layer" refers to adjusting the thickness of the second oxide layer 211. When the stress adjustment layer 4 includes the fourth defect layer 31 and the third oxide layer 311, "adjusting the thickness of the oxide layer" refers to adjusting the thickness of the third oxide layer 311. When the stress adjustment layer 4 includes the third defect layer 21, the fourth defect layer 31, and the third oxide layer 311, "adjusting the thickness of the oxide layer" refers to adjusting the thickness of the third oxide layer 311.

[0082] In the second scenario: when the second oxide layer 211 or the third oxide layer 311 has been removed and the thickness of the stress adjustment layer 4 still needs to be adjusted, the thickness of the defect layer needs to be adjusted, with an adjustment range of 0-500 mm.

[0083] Specifically, when the stress adjustment layer 4 includes the third defect layer 21 and the second oxide layer 211, "adjusting the thickness of the defect layer" refers to adjusting the thickness of the third defect layer 21. When the stress adjustment layer 4 includes the fourth defect layer 31 and the third oxide layer 311, "adjusting the thickness of the defect layer" refers to adjusting the thickness of the fourth defect layer 31. When the stress adjustment layer 4 includes the third defect layer 21, the fourth defect layer 31, and the third oxide layer 311, "adjusting the thickness of the defect layer" refers to adjusting the thickness of the fourth defect layer 31 or adjusting the thickness of the fourth defect layer 31 and the third defect layer 21.

[0084] As can be seen from the embodiments provided by the present invention above, the present invention, based on the formation of a defect layer through double-sided deposition and incomplete thermal oxidation, can form a stress adjustment layer on the side of the substrate layer away from the piezoelectric single crystal layer. This allows for adjustment of the internal stress of the wafer by adjusting the thickness of the stress adjustment layer, thereby improving the overall morphology of the wafer. Furthermore, the second defect layer has a larger grain size and fewer grain boundaries than the first defect layer. The oxide layer structure obtained by incomplete thermal oxidation of the second defect layer is more compact, which is beneficial for bonding between the piezoelectric single crystal layer and the oxide layer, reducing device losses. Simultaneously, the rough surface of the second defect layer can suppress the generation of clutter in surface acoustic wave devices.

[0085] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0086] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0087] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0088] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A low-loss substrate, characterized in that, The system includes a substrate layer (1) and a first defect layer (2) located on the substrate layer (1). The first defect layer (2) is grown on the substrate layer (1) at a first temperature. A second defect layer (3) is provided on the side of the first defect layer (2) away from the substrate layer (1). The second defect layer (3) is grown on the first defect layer (2) at a second temperature. The surface of the second defect layer (3) has a protrusion structure, and the height of the protrusion structure is a preset height. The preset height is 10nm-100nm. The second temperature is greater than the first temperature, and the grain size of the second defect layer (3) is greater than the grain size of the first defect layer (2). The materials of the first defect layer (2) and the second defect layer include polycrystalline silicon. When the first defect layer (2) and / or the second defect layer (3) are formed by double-sided deposition, a stress adjustment layer (4) is obtained on the side of the substrate layer (1) away from the first defect layer (2) after incomplete thermal oxidation, and a first oxide layer (5) is obtained on the side of the second defect layer (3) away from the first defect layer (2), wherein the density of the first oxide layer (5) is a preset density; the preset density is 2190 kg / m³. 3 -2270kg / m 3 The stress adjustment layer (4) is obtained by incomplete thermal oxidation at a third temperature. A piezoelectric single crystal layer (6) is provided on the side of the first oxide layer (5) away from the second defect layer (3), forming a bonding structure (102). The stress adjustment layer (4) is used to improve the morphology of the bonding structure (102) in order to adjust the internal stress of the wafer when the thickness of the stress adjustment layer (4) is adjusted.

2. The low-loss substrate according to claim 1, characterized in that, When the first defect layer (2) is formed by double-sided deposition, the stress adjustment layer (4) includes a third defect layer (21) and a second oxide layer (211); the third defect layer (21) is the structure corresponding to the first defect layer (2), and the second oxide layer (211) is the structure obtained by partially thermally oxidizing the third defect layer (21); When the second defect layer (3) is formed by double-sided deposition, the stress adjustment layer (4) includes a fourth defect layer (31) and a third oxide layer (311); the fourth defect layer (31) is the structure corresponding to the second defect layer (3), and the third oxide layer (311) is the structure obtained by partially thermally oxidizing the fourth defect layer (31); When both the first defect layer (2) and the second defect layer (3) are formed by double-sided deposition, the stress adjustment layer (4) includes the third defect layer (21), the fourth defect layer (31) and the third oxide layer (311).

3. The low-loss substrate according to claim 1, characterized in that, The substrate layer (1) is made of monocrystalline silicon; The resistivity of the substrate layer (1) is not less than 1000 ohm-cm.

4. The low-loss substrate according to claim 1, characterized in that, The polycrystalline silicon grains have a columnar structure.

5. The low-loss substrate according to claim 1, characterized in that, The thickness of the first defect layer (2) is 800-1000 nanometers; The thickness of the second defect layer (3) is 400-600 nanometers; The thickness of the first oxide layer (5) is 400-600 nanometers.

6. A method for fabricating a low-loss substrate, characterized in that, include: At a first temperature, a first defect layer (2) is grown on the substrate layer (1); At a second temperature, a second defect layer (3) is grown on the first defect layer (2) to obtain a defect wafer (101); the first defect layer (2) and / or the second defect layer (3) are formed by double-sided deposition; the second temperature is greater than the first temperature, and the grain size of the second defect layer (3) is greater than the grain size of the first defect layer (2); the materials of the first defect layer (2) and the second defect layer (3) include polycrystalline silicon; the surfaces of the first defect layer (2) and the second defect layer (3) have a protrusion structure, and the height of the protrusion structure is a preset height; the preset height is 10nm-100nm; At a third temperature, the defective wafer (101) undergoes incomplete thermal oxidation to obtain a stress adjustment layer (4) on the side of the substrate layer (1) away from the first defect layer (2), and a first oxide layer (5) on the side of the second defect layer (3) away from the first defect layer (2); the density of the first oxide layer (5) is a preset density; the preset density is 2190 kg / m³. 3 -2270kg / m 3 ; A piezoelectric single crystal layer (6) is grown on the first oxide layer (5) to obtain a bonding structure (102); The thickness of the stress adjustment layer (4) is adjusted to improve the morphology of the bonding structure (102), adjust the internal stress of the wafer, and obtain a low-loss substrate.

7. The method for preparing a low-loss substrate according to claim 6, characterized in that, When the first defect layer (2) is formed by double-sided deposition, a third defect layer (21) corresponding to the first defect layer (2) is obtained. At this time, the defect wafer (101) includes the third defect layer (21), the substrate layer (1), the first defect layer (2) and the second defect layer (3) stacked in sequence. After incomplete thermal oxidation, a second oxide layer (211) is formed in part of the third defect layer (21). At this time, the stress adjustment layer (4) includes the third defect layer (21) and the second oxide layer (211). When the second defect layer (3) is formed by double-sided deposition, a fourth defect layer (31) corresponding to the second defect layer (3) is obtained. At this time, the defect wafer (101) includes the fourth defect layer (31), the substrate layer (1), the first defect layer (2) and the second defect layer (3) stacked in sequence. After incomplete thermal oxidation, a third oxide layer (311) is formed in part of the fourth defect layer (31). At this time, the stress adjustment layer (4) includes the fourth defect layer (31) and the third oxide layer (311). When the first defect layer (2) and the second defect layer (3) are both generated by double-sided deposition, the defect wafer (101) includes the fourth defect layer (31), the third defect layer (21), the substrate layer (1), the first defect layer (2) and the second defect layer (3) stacked in sequence; after incomplete thermal oxidation, the stress adjustment layer (4) includes the third defect layer (21), the fourth defect layer (31) and the third oxide layer (311).

8. The method for preparing a low-loss substrate according to claim 6, characterized in that, The first temperature is 550-640 degrees Celsius; The second temperature is 650-750 degrees Celsius; The third temperature is 900-1100 degrees Celsius.

9. The method for preparing a low-loss substrate according to claim 6, characterized in that, The method for growing the piezoelectric single crystal layer (6) includes ion beam stripping and transfer or bonding grinding.

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