Quality factor enhanced active filter and electronic device

Abstract

The application discloses a quality factor enhanced active filter and electronic equipment, and relates to the technical field of integrated circuit band pass filters. The quality factor enhanced active filter comprises a subtraction circuit, a first second-order quality factor enhanced active filter circuit and a second second-order quality factor enhanced active filter circuit which are electrically connected with the subtraction circuit. The first second-order quality factor enhanced active filter circuit and the second second-order quality factor enhanced active filter circuit each comprise variable gain sub-circuits, inductance-capacitance parallel resonance sub-circuits and negative resistance feedback sub-circuits which are electrically connected with each other. The subtraction circuit is connected with the variable gain sub-circuit. The application has the technical effects of a large gain adjustment range, unchanged center frequency points during gain and Q value adjustment, tunable center frequency, good rectangular coefficient and high linearity, and can be integrated and used in radio frequency front-end equipment.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit bandpass filter technology, and more particularly to a quality factor enhancement active filter and electronic device. Background Technology

[0002] With the continuous improvement of CMOS (Complementary Metal-Oxide-Semiconductor) technology, feature sizes are constantly decreasing, transistor characteristic frequencies are increasing, and noise figures and linearity are improving to some extent. Meanwhile, CMOS technology, due to its advantages such as low cost, low power consumption, miniaturization, high integration, and high reliability, is becoming the future development trend of radio frequency integrated circuits. Chip area is extremely valuable; using on-chip reconfigurable filters can significantly reduce the number of RF front-end filters, while also leveraging high frequency selectivity in the receiver chain to address interference issues as early as possible.

[0003] Currently, Q-enhanced filters are highly attractive due to the smaller size and higher quality factor of the inductor L at high frequencies. On-chip integrated filters based on Q-enhanced LC resonant cavities (circuits formed by connecting inductors and capacitors in a resonant state) are therefore very appealing. The tunability of Q-enhanced filters is crucial, especially the tunability of gain, Q value, and center frequency.

[0004] However, traditional Q-enhancement filters have a small adjustable gain range and low adjustment accuracy, which reduces the reliability and stability of Q-enhancement filters. Summary of the Invention

[0005] The purpose of this invention is to provide a quality factor enhancement active filter and electronic device to solve the problems of small adjustment gain range and low adjustment accuracy of existing Q enhancement filters, which reduce the reliability and stability of Q enhancement filters.

[0006] In a first aspect, the present invention provides a quality factor enhancement active filter, the quality factor enhancement active filter comprising:

[0007] Subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second second-order quality factor enhancement active filter circuit, which are respectively electrically connected to the subtraction circuit.

[0008] Both the first second-order quality factor enhancement active filter circuit and the second second-order quality factor enhancement active filter include a variable gain sub-circuit, an inductor-capacitor parallel resonant sub-circuit, and a negative resistance feedback sub-circuit that are electrically connected to each other; the subtraction circuit and the variable gain sub-circuit are connected.

[0009] The subtraction circuit is used to improve the bandpass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second second-order quality factor enhancement active filter circuit to the fourth order, and to improve the rectangular coefficient of the quality factor enhancement active filter.

[0010] Both of the variable gain sub-circuits adopt a common source cascode structure, which is used to adjust the gain of the quality factor enhancement active filter circuit within a large range and suppress center frequency drift.

[0011] The inductor-capacitor parallel resonator circuit is used to adjust and control the resonant center frequency by changing its capacitance value.

[0012] The negative resistance feedback sub-circuit is used to adjust the quality factor of the active filter.

[0013] The quality factor enhancement active filter provided in this embodiment of the invention, using the above technical solution, includes a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second second-order quality factor enhancement active filter circuit electrically connected to the subtraction circuit. Both the first and second second-order quality factor enhancement active filter circuits include a variable gain sub-circuit, an inductor-capacitor parallel resonant sub-circuit, and a negative resistance feedback sub-circuit, all electrically connected to each other. The subtraction circuit and the variable gain sub-circuit are connected. The subtraction circuit is used to subtract the voltage of the first and second second-order quality factor enhancement active filter circuits. The bandpass filter frequency selectivity of the path is improved to the fourth order, increasing the rectangular coefficient of the enhanced active filter by improving the quality factor; both variable gain sub-circuits adopt a common source cascode structure, used to adjust the gain of the enhanced active filter circuit within a large range and suppress center frequency drift; the inductor-capacitor parallel resonant sub-circuit is used to adjust and control the resonant center frequency by changing its capacitance value; the negative resistance feedback sub-circuit is used to adjust the quality factor of the active filter, so that this application has the technical effects of large gain adjustment range, unchanged center frequency when adjusting gain and Q value, tunable center frequency, good rectangular coefficient and high linearity, which facilitates integration and can be used in RF front-end equipment.

[0014] In one possible implementation, the common gate of the common-source cascode structure corresponding to the variable gain sub-circuit in the two second-order quality factor enhanced active filter circuits is connected to the control voltage, the drain of the common-source cascode structure is connected in parallel with the inductor-capacitor parallel resonant circuit and the negative resistance feedback sub-circuit, and the source of the common-source cascode structure is connected to the tail current source, which is implemented by a fixed-bias N-type common-source metal-oxide-semiconductor transistor.

[0015] In one possible implementation, the current source in the two second-order quality factor enhancement active filter circuits forms a negative resistance feedback sub-circuit with the two transistors. The current source is implemented by an N-type common-source metal-oxide-semiconductor transistor. The change in current is achieved by changing the gate voltage of the N-type common-source metal-oxide-semiconductor transistor, thereby controlling the change in quality factor.

[0016] In one possible implementation, the subtraction circuit includes a fifteenth common-source transistor, a sixteenth common-source transistor, a seventeenth common-source transistor, and an eighteenth common-source transistor;

[0017] The drain of the fifteenth common-source transistor is connected to the source and output port of the seventeenth common-source transistor, and the source of the fifteenth common-source transistor is connected to ground. The drain of the sixteenth common-source transistor is connected to the source and output port of the eighteenth common-source transistor, and the source of the sixteenth common-source transistor is connected to ground. The source of the seventeenth common-source transistor is connected to the power supply, and the source of the eighteenth common-source transistor is connected to the power supply.

[0018] In one possible implementation, the variable gain sub-circuit corresponding to the first second-order quality factor enhancement active filter circuit includes a first common-source transistor, a second common-source transistor, a third common-gate transistor, a fourth common-gate transistor, and a first current source; the variable gain sub-circuit corresponding to the second second-order quality factor enhancement active filter circuit includes an eighth common-source transistor, a ninth common-source transistor, a tenth common-gate transistor, an eleventh common-gate transistor, and a second current source.

[0019] The first common-source transistor and the second common-source transistor are used to input differential radio frequency signals. The drains of the first common-source transistor and the second common-source transistor are respectively connected to the sources of the third common-gate transistor and the fourth common-gate transistor, and their other ends are connected to the first current source. The gates of the third common-gate transistor and the fourth common-gate transistor are connected to the first resistor control voltage. The eighth common-source transistor and the ninth common-source transistor are used to input differential radio frequency signals. The drains of the eighth common-source transistor and the ninth common-source transistor are respectively connected to the sources of the tenth common-gate transistor and the eleventh common-gate transistor, and their other ends are connected to the second current source. The gates of the tenth common-gate transistor and the eleventh common-gate transistor are connected to the second resistor control voltage.

[0020] The drains of the third common gate transistor and the fourth common gate transistor are connected to the corresponding inductor-capacitor parallel resonator circuit. One end of the corresponding negative resistance feedback sub-circuit is connected to the inductor-capacitor parallel resonator circuit, and the other end is connected to the first current source.

[0021] The drains of the tenth common gate transistor and the eleventh common gate transistor are connected to the corresponding inductor-capacitor parallel resonator circuit. One end of the corresponding negative resistance feedback sub-circuit is connected to the inductor-capacitor parallel resonator circuit, and the other end is connected to the second current source.

[0022] The gate of the seventeenth common-source transistor is connected to the drain of the tenth common-gate transistor, the gate of the fifteenth common-source transistor is connected to the drain of the third common-gate transistor, the gate of the sixteenth common-source transistor is connected to the drain of the fourth common-gate transistor, and the gate of the eighteenth common-source transistor is connected to the drain of the eleventh common-gate transistor.

[0023] In one possible implementation, the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor all operate in the linear region, while the third common-gate transistor, the fourth common-gate transistor, the tenth common-gate transistor, and the eleventh common-gate transistor operate in the saturation region. By changing the first resistor control voltage and the second resistor control voltage, the transconductance of the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor will change exponentially with the control voltage, while the load resistance and current remain unchanged. The voltage gain of the circuit changes, thereby achieving gain control. At the same time, the use of the first current source and the second current source improves the linearity.

[0024] In one possible implementation, the inductor-capacitor parallel resonator circuit includes a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor, a capacitor array, a first inductor, and a second inductor.

[0025] The first inductor is connected in parallel with the capacitor array and the first and second variable capacitors connected in series. The center plug is connected to the power supply. The first capacitor control voltage is connected to the connection point of the first and second variable capacitors. The second inductor is connected in parallel with the capacitor array and the third and fourth variable capacitors connected in series. The center plug is connected in series with the nineteenth common-source transistor with its drain and gate shorted. The second capacitor control voltage is connected to the connection point of the third and fourth variable capacitors.

[0026] In one possible implementation, the negative resistance feedback sub-circuit includes a fifth common-source transistor, a sixth common-source transistor, a seventh common-source transistor, a twelfth common-source transistor, a thirteenth common-source transistor, and a fourteenth common-source transistor.

[0027] The drain of the sixth common-source transistor is connected to the gate of the seventh common-source transistor. The source of the sixth common-source transistor is connected to the drain of the fifth common-source transistor. The drain of the seventh common-source transistor is connected to the gate of the sixth common-source transistor. The source of the seventh common-source transistor is connected to the drain of the fifth common-source transistor. The source of the fifth common-source transistor is connected to ground. The gate of the fifth common-source transistor is connected to the first current control voltage. The drain of the thirteenth common-source transistor is connected to the gate of the fourteenth common-source transistor. The source of the thirteenth common-source transistor is connected to the drain of the twelfth common-source transistor. The drain of the fourteenth common-source transistor is connected to the gate of the thirteenth common-source transistor. The source of the fourteenth common-source transistor is connected to the drain of the twelfth common-source transistor. The source of the twelfth common-source transistor is connected to ground. The gate of the twelfth common-source transistor is connected to the second current control voltage.

[0028] In one possible implementation, the first common-source transistor, the second common-source transistor, the third common-gate transistor, the fourth common-gate transistor, the fifth common-source transistor, the sixth common-source transistor, the seventh common-source transistor, the eighth common-source transistor, the ninth common-source transistor, the tenth common-gate transistor, the eleventh common-gate transistor, the twelfth common-source transistor, the thirteenth common-source transistor, the fourteenth common-source transistor, the fifteenth common-source transistor, the sixteenth common-source transistor, the seventeenth common-source transistor, and the eighteenth common-source transistor are all N-type metal-oxide-semiconductor transistors, and their substrates are all connected to the corresponding ground.

[0029] The nineteenth common-source transistor is a P-type metal-oxide-semiconductor transistor, with its substrate connected to the corresponding power supply.

[0030] In a second aspect, the present invention also provides an electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, cause the device to perform a quality factor enhancement active filter as described in any possible implementation of the first aspect.

[0031] The beneficial effects of the electronic device provided in the second aspect are the same as those of the quality factor enhancement active filter described in the first aspect or any possible implementation of the first aspect, and will not be repeated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0033] Figure 1This paper shows a schematic diagram of the overall circuit structure of a quality factor enhancement active filter provided in an embodiment of this application.

[0034] Figure 2 A schematic diagram of the circuit structure of a first-order second-order quality factor enhancement active filter circuit provided in an embodiment of this application is shown.

[0035] Figure 3 This paper presents a schematic diagram of a simulation curve showing that the center frequency remains unchanged during gain adjustment of a Q-enhanced active filter provided in an embodiment of this application.

[0036] Figure 4 This paper shows a simulation diagram of a Q-enhanced active filter with a tunable center frequency according to an embodiment of the present application.

[0037] Figure 5 This paper shows a simulation diagram of a Q-enhanced active filter with a center frequency of 3 GHz and tunable bandwidth, provided in an embodiment of this application.

[0038] Figure 6 The diagram shows a simulation data graph of a Q-enhanced active filter provided in an embodiment of this application;

[0039] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Attached image description:

[0042] 01-Subtraction circuit; 02-First and second-order quality factor enhancement active filter circuit; 03-Second-order quality factor enhancement active filter circuit; A-Variable gain sub-circuit; B-Inductor-capacitor parallel resonant sub-circuit; C-Negative resistance feedback sub-circuit. Detailed Implementation

[0043] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0044] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0046] Figure 1 This illustration shows a schematic diagram of the overall circuit structure of a quality factor enhancement active filter according to an embodiment of this application. The quality factor enhancement active filter includes:

[0047] Subtraction circuit 01, and a first second-order quality factor enhancement active filter circuit 02 and a second second-order quality factor enhancement active filter circuit 03, which are respectively electrically connected to the subtraction circuit 01.

[0048] Both the first second-order quality factor enhancement active filter circuit 02 and the second second-order quality factor enhancement active filter 03 include a variable gain sub-circuit A, an inductor-capacitor parallel resonant sub-circuit B, and a negative resistance feedback sub-circuit C, which are electrically connected to each other; the subtraction circuit 01 is connected to the variable gain sub-circuit A.

[0049] The subtraction circuit is used to improve the bandpass filtering frequency selectivity of the first second-order quality factor enhancement active filter circuit and the second second-order quality factor enhancement active filter circuit to the fourth order, and to improve the rectangular coefficient of the quality factor enhancement active filter.

[0050] Both of the variable gain sub-circuits adopt a common source cascode structure, which is used to adjust the gain of the quality factor enhancement active filter circuit within a large range and suppress center frequency drift.

[0051] The inductor-capacitor parallel resonator circuit is used to adjust and control the resonant center frequency by changing its capacitance value.

[0052] The negative resistance feedback sub-circuit is used to adjust the quality factor of the active filter.

[0053] The quality factor enhancement active filter provided in this embodiment of the invention includes a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second second-order quality factor enhancement active filter circuit electrically connected to the subtraction circuit. Both the first and second second-order quality factor enhancement active filter circuits include a variable gain sub-circuit, an inductor-capacitor parallel resonant sub-circuit, and a negative resistance feedback sub-circuit, all electrically connected to each other. The subtraction circuit and the variable gain sub-circuit are connected. The subtraction circuit is used to perform bandpass filtering on the first and second second-order quality factor enhancement active filter circuits. The frequency selectivity is improved to the fourth order, increasing the rectangular coefficient of the enhanced active filter. Both variable gain sub-circuits adopt a common-source, common-gate structure, which is used to adjust the gain of the enhanced active filter circuit within a large range and suppress center frequency drift. The inductor-capacitor parallel resonant sub-circuit is used to adjust and control the resonant center frequency by changing its capacitance value. The negative resistance feedback sub-circuit is used to adjust the quality factor of the active filter, so that this application has the technical effects of a large gain adjustment range, constant center frequency when adjusting gain and Q value, tunable center frequency, good rectangular coefficient, and high linearity, which facilitates integration and can be used in RF front-end equipment.

[0054] Optionally, in the two second-order quality factor enhancement active filter circuits (first second-order quality factor enhancement active filter circuit 02 and second second-order quality factor enhancement active filter circuit 03), the common gate of the common-source cascode structure corresponding to the variable gain sub-circuit is connected to the control voltage, the drain of the common-source cascode structure is connected in parallel with the inductor-capacitor parallel resonant circuit and the negative resistance feedback sub-circuit, and the source of the common-source cascode structure is connected to the tail current source, which is implemented by a fixed-bias N-type common-source metal-oxide-semiconductor transistor.

[0055] Optionally, in the two second-order quality factor enhancement active filter circuits, the current source and the two transistors form a negative resistance feedback sub-circuit. The current source is implemented by an N-type common-source metal-oxide-semiconductor transistor. By changing the gate voltage of the N-type common-source metal-oxide-semiconductor transistor, the current is changed, thereby controlling the change of the quality factor.

[0056] Optional, see Figure 1The subtraction circuit 01 includes a fifteenth common-source transistor M15, a sixteenth common-source transistor M16, a seventeenth common-source transistor M17, and an eighteenth common-source transistor M18;

[0057] The drain of the fifteenth common-source transistor M15 is connected to the source and output port of the seventeenth common-source transistor M17, and the source of the fifteenth common-source transistor M15 is connected to ground GND. The drain of the sixteenth common-source transistor M16 is connected to the source and output port of the eighteenth common-source transistor M18, and the source of the sixteenth common-source transistor M16 is connected to ground GND. The source of the seventeenth common-source transistor M17 is connected to power supply VDD, and the source of the eighteenth common-source transistor M18 is connected to power supply VDD.

[0058] In this application, the center frequency of the second-order Q-enhanced active filter circuit is ω;

[0059]

[0060] In formula (1), C is the total capacitance in the circuit and L is the inductance.

[0061] The center frequency of the first second-order Q-enhanced active filter circuit is ω1, and the waveforms of the LC resonant cavity and negative resistance transfer function are as follows:

[0062]

[0063] The center frequency of the second-order Q-enhanced active filter circuit is ω2, and the waveforms of the LC resonant cavity and negative resistance transfer function are as follows:

[0064]

[0065] Subtracting the two functions (2) and (3), we obtain the waveform function of the fourth-order Q-enhanced active filter as follows:

[0066]

[0067]

[0068] In the formula, Q1 and Q2 represent the quality factors of the second-order Q-enhanced active circuit.

[0069] Optional, Figure 2 This paper shows a schematic diagram of the circuit structure of a first-order second-order quality factor enhancement active filter circuit according to an embodiment of this application. See also: Figure 1 or Figure 2The variable gain sub-circuit A corresponding to the first second-order quality factor enhancement active filter circuit 02 includes a first common-source transistor M1, a second common-source transistor M2, a third common-gate transistor M3, a fourth common-gate transistor M4, and a first current source Itail1; the variable gain sub-circuit A corresponding to the second second-order quality factor enhancement active filter circuit 03 includes an eighth common-source transistor M8, a ninth common-source transistor M9, a tenth common-gate transistor M10, an eleventh common-gate transistor M11, and a second current source Itail2.

[0070] The first common-source transistor M1 and the second common-source transistor M2 are used to input differential radio frequency signals. The drains of the first common-source transistor M1 and the second common-source transistor M2 are connected to the sources of the third common-gate transistor M3 and the fourth common-gate transistor M4, respectively, and their other ends are connected to the first current source Itail1. The gates of the third common-gate transistor M3 and the fourth common-gate transistor M4 are connected to the first resistor control voltage Vcr1crontrol. The eighth common-source transistor M8 and the ninth common-source transistor M9 are used to input differential radio frequency signals. The drains of the eighth common-source transistor M8 and the ninth common-source transistor M9 are connected to the sources of the tenth common-gate transistor M10 and the eleventh common-gate transistor M11, respectively, and their other ends are connected to the second current source Itail2. The gates of the tenth common-gate transistor M10 and the eleventh common-gate transistor M11 are connected to the second resistor control voltage Vcr2crontrol. The tail current source is implemented by a fixed-bias N-type common-source MOS transistor.

[0071] In this application, the gain of two second-order Q-enhanced active filter circuits can be controlled by changing the first resistor control voltage Vcr1crontrol and the second resistor control voltage Vcr2crontrol, respectively.

[0072] It should be noted that, see Figure 1 The input impedance matching network includes a first resistor R1 and a second resistor R2, which are connected in series. The two ends are connected to the input differential RF signal, and the middle is connected to the bias voltage. This can ensure the matching degree of the filter. Since the matching of the filter is very important, it plays a very important role in the transmission of signal power and gain. Input matching can ensure maximum power transmission and thus improve the utilization of the signal.

[0073] In this application, the variable gain sub-circuit, the inductor-capacitor (LC) parallel resonant sub-circuit, and the negative resistance feedback sub-circuit are subtracted by a subtraction circuit to form a fourth-order Q (quality factor) enhanced active filter circuit.

[0074] Optional, see Figure 1 or Figure 2 The drains of the third common gate transistor M3 and the fourth common gate transistor M4 are connected to the corresponding inductor-capacitor parallel resonator circuit B. One end of the corresponding negative resistance feedback sub-circuit C is connected to the inductor-capacitor parallel resonator circuit B, and the other end is connected to the first current source Itail1.

[0075] Optional, see Figure 1 The drains of the tenth common gate transistor M10 and the eleventh common gate transistor M11 are connected to the corresponding inductor-capacitor parallel resonator circuit B. One end of the corresponding negative resistance feedback sub-circuit C is connected to the inductor-capacitor parallel resonator circuit B, and the other end is connected to the second current source Itail2.

[0076] Optional, see Figure 1 The gate of the seventeenth common-source transistor M17 is connected to the drain of the tenth common-gate transistor M10, the gate of the fifteenth common-source transistor M15 is connected to the drain of the third common-gate transistor M3, the gate of the sixteenth common-source transistor M16 is connected to the drain of the fourth common-gate transistor M4, and the gate of the eighteenth common-source transistor M18 is connected to the drain of the eleventh common-gate transistor M11.

[0077] Optionally, the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor all operate in the linear region, while the third common-gate transistor, the fourth common-gate transistor, the tenth common-gate transistor, and the eleventh common-gate transistor operate in the saturation region. By changing the first resistor control voltage and the second resistor control voltage, the transconductance of the first common-source transistor, the second common-source transistor, the eighth common-source transistor, and the ninth common-source transistor will change exponentially with the control voltage, while the load resistance and current remain unchanged. The voltage gain of the circuit changes, thereby achieving gain control. At the same time, the use of the first current source and the second current source improves the linearity.

[0078] Optional, see Figure 1 The inductor-capacitor parallel resonator circuit B includes a first variable capacitor C1, a second variable capacitor C2, a third variable capacitor C3, a fourth variable capacitor C4, a capacitor array, a first inductor L1 and a second inductor L2, and also includes a nineteenth common-source transistor M19.

[0079] See Figure 1The first inductor L1 is connected in parallel with the capacitor array and the first variable capacitor C1 and the second variable capacitor C2 connected in series. The center plug is connected to the power supply VDD. The first capacitor control voltage Vcc1control is connected to the connection point of the first variable capacitor C1 and the second variable capacitor C2. The second inductor L2 is connected in parallel with the capacitor array and the third variable capacitor C3 and the fourth variable capacitor C4 connected in series. The center plug is connected in series with the nineteenth common-source transistor M19, which is shorted between its drain and gate, and the power supply VDD. The second capacitor control voltage Vcc2control is connected to the connection point of the third variable capacitor C3 and the fourth variable capacitor C4.

[0080] Furthermore, in this application, the capacitor array mainly consists of six pairs of discretely adjustable switched capacitors. Each switched capacitor primarily comprises an NMOS transistor, resistors, and a fixed capacitor. Two resistors are connected in series, with their ends connected in parallel with the NMOS transistor, and then their ends are connected in series with the fixed capacitors. The two resistors are grounded in the middle, and the gate of the NMOS transistor is connected to the switching control voltage.

[0081] In this application, the capacitance value of the variable capacitor C can be adjusted by changing the first capacitor control voltage Vcc1control and the second capacitor control voltage Vcc2control through the capacitor array switch, thereby achieving the adjustment and control of the resonant center frequency.

[0082] Optional, see Figure 1 The negative resistance feedback sub-circuit C includes a fifth common-source transistor M5, a sixth common-source transistor M6, a seventh common-source transistor M7, a twelfth common-source transistor M12, a thirteenth common-source transistor M13, and a fourteenth common-source transistor M14. By controlling the gate voltage of the fifth common-source transistor M5, the current is changed, thereby controlling the change of the Q value.

[0083] Among them, see Figure 1The drain of the sixth common-source transistor M6 is connected to the gate of the seventh common-source transistor M7. The source of the sixth common-source transistor M6 is connected to the drain of the fifth common-source transistor M5. The drain of the seventh common-source transistor M7 is connected to the gate of the sixth common-source transistor M6. The source of the seventh common-source transistor M7 is connected to the drain of the fifth common-source transistor M5. The source of the fifth common-source transistor M5 is connected to ground. The gate of the fifth common-source transistor M5 is connected to the first current control voltage Vci1control. The thirteenth common-source transistor... The drain of transistor M13 is connected to the gate of the fourteenth common-source transistor M14. The source of the thirteenth common-source transistor M13 is connected to the drain of the twelfth common-source transistor M12. The drain of the fourteenth common-source transistor M14 is connected to the gate of the thirteenth common-source transistor M13. The source of the fourteenth common-source transistor M14 is connected to the drain of the twelfth common-source transistor M12. The source of the twelfth common-source transistor M12 is connected to ground. The gate of the twelfth common-source transistor M12 is connected to the second current control voltage Vci2control.

[0084] Optionally, the first common-source transistor M1, the second common-source transistor M2, the third common-gate transistor M3, the fourth common-gate transistor M4, the fifth common-source transistor M5, the sixth common-source transistor M6, the seventh common-source transistor M7, the eighth common-source transistor M8, the ninth common-source transistor M9, the tenth common-gate transistor M10, the eleventh common-gate transistor M11, the twelfth common-source transistor M12, the thirteenth common-source transistor M13, the fourteenth common-source transistor M14, the fifteenth common-source transistor M15, the sixteenth common-source transistor M16, the seventeenth common-source transistor M17, and the eighteenth common-source transistor M18 are all N-type metal-oxide-semiconductor transistors, and their substrates are all connected to the corresponding ground.

[0085] The nineteenth common-source transistor M19 is a P-type metal-oxide-semiconductor transistor, with its substrate connected to the corresponding power supply.

[0086] Example, Figure 3 This paper presents a schematic diagram of a simulation curve showing that the center frequency remains unchanged during gain adjustment of a Q-enhanced active filter according to an embodiment of this application. Figure 3 The image shows the S21 simulation curve obtained from the Cadence simulation software tool based on the SMIC 55nm CMOS process. Figure 3 This demonstrates that when the gain of two second-order Q-enhanced active filters is adjusted, the center frequency of both the second-order and fourth-order Q-enhanced active filters remains unchanged. The dashed line represents the curve of the second-order Q-enhanced active filter, and the solid line represents the curve of the Q-enhanced active filter of this invention.

[0087] Example, Figure 4 This paper presents a simulation diagram showing the tunable center frequency of a Q-enhanced active filter according to an embodiment of this application. Figure 5 This paper presents a simulation diagram of a Q-enhanced active filter with a center frequency of 3 GHz and tunable bandwidth, according to an embodiment of this application. Figure 6 This paper shows a data graph of simulation data for a Q-enhanced active filter provided in an embodiment of this application. Figure 4 and Figure 5 The S21 simulation curve is obtained from the Cadence simulation software tool based on the SMIC 55nm CMOS process. Figure 6 The simulation data is shown as obtained from the simulation curves. Figure 4 , Figure 5 , Figure 6 This demonstrates the capabilities of Q-enhanced active filters in terms of harmonicity and linearity.

[0088] from Figure 3 , Figure 4 , Figure 5 and Figure 6 As can be seen, this application has the technical advantages of a large gain adjustment range, constant center frequency when gain and Q value change, tunable center frequency, good rectangular coefficient and high linearity, which makes it easy to integrate and can be used in RF front-end equipment.

[0089] Compared to the gain amplification structure in traditional fourth-order Q-enhanced active filter circuits based on subtraction circuit synthesis, which directly controls the variable resistor to adjust the gain and Q value, resulting in different load capacitances on the LC resonator and causing frequency drift, the common-source, common-gate, and negative-resistance current source structure used in this invention not only has a good gain adjustment range but also shows no significant change in the center frequency when adjusting the gain and Q value, thus exhibiting significant advantages.

[0090] The quality factor enhancement active filter provided in this embodiment of the invention includes a subtraction circuit, and a first second-order quality factor enhancement active filter circuit and a second second-order quality factor enhancement active filter circuit electrically connected to the subtraction circuit. Both the first and second second-order quality factor enhancement active filter circuits include a variable gain sub-circuit, an inductor-capacitor parallel resonant sub-circuit, and a negative resistance feedback sub-circuit, all electrically connected to each other. The subtraction circuit and the variable gain sub-circuit are connected. The subtraction circuit is used to perform bandpass filtering on the first and second second-order quality factor enhancement active filter circuits. The frequency selectivity is improved to the fourth order, increasing the rectangular coefficient of the enhanced active filter. Both variable gain sub-circuits adopt a common-source, common-gate structure, which is used to adjust the gain of the enhanced active filter circuit within a large range and suppress center frequency drift. The inductor-capacitor parallel resonant sub-circuit is used to adjust and control the resonant center frequency by changing its capacitance value. The negative resistance feedback sub-circuit is used to adjust the quality factor of the active filter, so that this application has the technical effects of a large gain adjustment range, constant center frequency when adjusting gain and Q value, tunable center frequency, good rectangular coefficient, and high linearity, which facilitates integration and can be used in RF front-end equipment.

[0091] This invention provides a quality factor enhancement active filter, applied to a system including a controller and at least one detection circuit electrically connected to the controller, such as... Figures 1 to 6 To avoid repetition, the hardware implementation method of any of the reservoir computing models shown will not be described in detail here.

[0092] The electronic device in this embodiment of the invention can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, a mobile electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc., while a non-mobile electronic device can be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This embodiment of the invention does not impose specific limitations.

[0093] The electronic device in this embodiment of the invention can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this embodiment of the invention does not impose specific limitations.

[0094] Figure 7 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention is shown. Figure 7 As shown, the electronic device 100 includes a processor 110.

[0095] like Figure 7 As shown, the processor 110 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention.

[0096] like Figure 7 As shown, the electronic device 100 may further include a communication line 140. The communication line 140 may include a path for transmitting information between the components.

[0097] Optional, such as Figure 7 As shown, the above-mentioned electronic device may also include a communication interface 120. There may be one or more communication interfaces 120. The communication interface 120 can use any transceiver-like device for communicating with other devices or communication networks.

[0098] Optional, such as Figure 7 As shown, the electronic device may further include a memory 130. The memory 130 stores computer execution instructions for implementing the present invention, and its execution is controlled by a processor. The processor executes the computer execution instructions stored in the memory to implement the method provided in the embodiments of the present invention.

[0099] like Figure 7As shown, memory 130 can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 130 can exist independently and be connected to processor 110 via communication line 140. Memory 130 can also be integrated with processor 110.

[0100] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0101] In a specific implementation, as one example, such as Figure 7 As shown, processor 110 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 in the CPU.

[0102] In a specific implementation, as one example, such as Figure 7 As shown, the terminal device may include multiple processors, such as Figure 7 The first processor 1101 and the second processor 1102 are included. Each of these processors can be a single-core processor or a multi-core processor.

[0103] Figure 8 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Figure 8 As shown, the chip 200 includes one or more processors 110.

[0104] Optional, such as Figure 8 As shown, the chip also includes a communication interface 120 and a memory 130. The memory 130 may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

[0105] In some implementations, such as Figure 8 As shown, memory 130 stores the following elements: execution modules or data structures, or subsets thereof, or extended sets thereof.

[0106] In embodiments of the present invention, such as Figure 8 As shown, the corresponding operation is executed by calling the operation instructions stored in the memory (which can be stored in the operating system).

[0107] like Figure 8 As shown, the processor 110 controls the processing operations of any one of the terminal devices. The processor 110 can also be called a central processing unit (CPU).

[0108] like Figure 8 As shown, memory 130 may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory 130 may also include NVRAM. For example, in an application, memory, communication interfaces, and memory are coupled together via a bus system, which may include, in addition to a data bus, a power bus, a control bus, and a status signal bus, etc. However, for clarity, in... Figure 8 The general labeled all buses as Bus System 240.

[0109] like Figure 8As shown, the methods disclosed in the above embodiments of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0110] On the one hand, a computer-readable storage medium is provided, which stores instructions that, when executed, implement the functions performed by the terminal device in the above embodiments.

[0111] On the one hand, a chip is provided that is used in a terminal device. The chip includes at least one processor and a communication interface. The communication interface and at least one processor are coupled together. The processor is used to run instructions to implement the functions performed by the hardware implementation method of the reservoir computing model in the above embodiments.

[0112] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0113] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0114] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A quality factor enhanced active filter, characterized by, The quality factor enhanced active filter comprises: a subtraction circuit, and a first second-order quality factor enhanced active filter circuit and a second second-order quality factor enhanced active filter circuit which are electrically connected with the subtraction circuit respectively; The first second-order quality factor enhanced active filter circuit and the second second-order quality factor enhanced active filter circuit each comprise variable gain sub-circuits, inductance-capacitance parallel resonance sub-circuits and negative resistance feedback sub-circuits which are electrically connected with each other in pairs; and the subtraction circuit is connected with the variable gain sub-circuit. The subtraction circuit is used for increasing the band-pass filter frequency of the first second-order quality factor enhanced active filter circuit and the second second-order quality factor enhanced active filter circuit to the fourth order, and increasing the rectangular coefficient of the quality factor enhanced active filter. The two variable gain sub-circuits each adopt a common-source common-gate structure, are used for adjusting the gain of the quality factor enhanced active filter circuit, and suppress the center frequency point drift. The inductance-capacitance parallel resonance sub-circuit is used for adjusting and controlling the resonance center frequency by changing the capacitance value. The negative resistance feedback sub-circuit is used for adjusting the quality factor of the active filter.

2. The quality factor enhanced active filter of claim 1, wherein, The common gate of the common-source common-gate structure corresponding to the variable gain sub-circuit in the two second-order quality factor enhanced active filter circuits is connected with a control voltage, the drain of the common-source common-gate structure is connected with the inductance-capacitance parallel resonance sub-circuit and the negative resistance feedback sub-circuit in parallel, the source of the common-source common-gate structure is connected with a tail current source, and the tail current source is realized by an N-type common-source metal oxide semiconductor transistor with fixed bias.

3. The quality factor enhanced active filter of claim 1, wherein, The current source and the two transistors form the negative resistance feedback sub-circuit in the two second-order quality factor enhanced active filter circuits, the current source is realized by an N-type common-source metal oxide semiconductor transistor, the change of the current is realized by changing the gate voltage of the N-type common-source metal oxide semiconductor transistor, and thus the change of the quality factor is controlled.

4. The quality factor enhanced active filter of claim 1, wherein, The subtraction circuit comprises a fifteenth common-source transistor, a sixteenth common-source transistor, a seventeenth common-source transistor and an eighteenth common-source transistor. The drain of the fifteenth common-source transistor is connected with the source of the seventeenth common-source transistor and an output port respectively, the source of the fifteenth common-source transistor is connected with the ground, the drain of the sixteenth common-source transistor is connected with the source of the eighteenth common-source transistor and the output port respectively, the source of the sixteenth common-source transistor is connected with the ground, the source of the seventeenth common-source transistor is connected with a power supply, and the source of the eighteenth common-source transistor is connected with the power supply.

5. The quality factor enhanced active filter of claim 4, wherein, The variable gain sub-circuit corresponding to the first second-order quality factor enhanced active filter circuit comprises a first common-source transistor, a second common-source transistor, a third common-gate transistor, a fourth common-gate transistor and a first current source; and the variable gain sub-circuit corresponding to the second second-order quality factor enhanced active filter circuit comprises an eighth common-source transistor, a ninth common-source transistor, a tenth common-gate transistor, an eleventh common-gate transistor and a second current source. The first common source transistor and the second common source transistor are used for inputting differential radio frequency signals, the drain of the first common source transistor and the drain of the second common source transistor are connected with the source of the third common gate transistor and the source of the fourth common gate transistor respectively, and the other ends are connected with the first current source; the gate of the third common gate transistor and the gate of the fourth common gate transistor are connected with the first resistance control voltage. The drain of the third common gate transistor and the drain of the fourth common gate transistor are connected with the corresponding inductance-capacitance parallel resonance sub-circuit, and one end of the corresponding negative resistance feedback sub-circuit is connected with the inductance-capacitance parallel resonance sub-circuit, and the other end is connected with the first current source. The drain of the tenth common gate transistor and the drain of the eleventh common gate transistor are connected with the corresponding inductance-capacitance parallel resonance sub-circuit, and one end of the corresponding negative resistance feedback sub-circuit is connected with the inductance-capacitance parallel resonance sub-circuit, and the other end is connected with the second current source. The gate of the seventeenth common source transistor is connected with the drain of the tenth common gate transistor, the gate of the fifteenth common source transistor is connected with the drain of the third common gate transistor, the gate of the sixteenth common source transistor is connected with the drain of the fourth common gate transistor, and the gate of the eighteenth common source transistor is connected with the drain of the eleventh common gate transistor.

6. The quality factor enhanced active filter of claim 5, wherein, The first common source transistor, the second common source transistor, the eighth common source transistor and the ninth common source transistor all work in a linear region, the third common gate transistor, the fourth common gate transistor, the tenth common gate transistor and the eleventh common gate transistor work in a saturation region, the first resistance control voltage and the second resistance control voltage are changed, the transconductance of the first common source transistor, the second common source transistor, the eighth common source transistor and the ninth common source transistor will change exponentially with the control voltage, the load resistance and the current remain unchanged, the voltage gain of the circuit changes, thereby realizing gain control, and the first current source and the second current source are used to improve linearity.

7. The quality factor enhanced active filter of claim 5, wherein, The inductance-capacitance parallel resonance sub-circuit comprises a first variable capacitor, a second variable capacitor, a third variable capacitor, a fourth variable capacitor, a capacitor array, a first inductor and a second inductor. The first inductor is connected in parallel with the capacitor array and the first and second variable capacitors connected in series, a center tap is connected to a power supply, a first capacitor control voltage is connected to the junction of the first and second variable capacitors, the second inductor is connected in parallel with the capacitor array and the third and fourth variable capacitors connected in series, a center tap is connected in series with a nineteenth common source transistor having a short between the drain and gate and a power supply, a second capacitor control voltage is connected to the junction of the third and fourth variable capacitors.

8. The quality factor enhanced active filter of claim 7, wherein, The negative resistance feedback sub-circuit comprises a fifth common source transistor, a sixth common source transistor, a seventh common source transistor, a twelfth common source transistor, a thirteenth common source transistor and a fourteenth common source transistor; The drain of the sixth common source transistor is connected to the gate of the seventh common source transistor, the source of the sixth common source transistor is connected to the drain of the fifth common source transistor, the drain of the seventh common source transistor is connected to the gate of the sixth common source transistor, the source of the seventh common source transistor is connected to the drain of the fifth common source transistor, the source of the fifth common source transistor is connected to ground, the gate of the fifth common source transistor is connected to a first current control voltage, the drain of the thirteenth common source transistor is connected to the gate of the fourteenth common source transistor, the source of the thirteenth common source transistor is connected to the drain of the twelfth common source transistor, the drain of the fourteenth common source transistor is connected to the gate of the thirteenth common source transistor, the source of the fourteenth common source transistor is connected to the drain of the twelfth common source transistor, the source of the twelfth common source transistor is connected to ground, and the gate of the twelfth common source transistor is connected to a second current control voltage.

9. The quality factor enhanced active filter of claim 8, wherein, The first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth and eighteenth common source transistors are all N-type metal oxide semiconductor transistors, and the substrates are all connected to corresponding grounds; The nineteenth common source transistor is a P-type metal oxide semiconductor transistor, and the substrate is connected to a corresponding power supply.

10. An electronic device, comprising: comprising: one or more processors; and one or more machine readable media having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to perform the quality factor enhancement active filter of any of claims 1-9.

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