Sampling and holding circuit and method

Abstract

The present invention discloses a sampling and holding circuit and method, which can amplify an input signal. The method includes the following steps: enabling the upper electrodes of a plurality of first (second) capacitors to receive a first (second) input signal during a sampling period, and enabling the lower electrodes of at least a part of the plurality of first (second) capacitors to receive the second (first) input signal during the sampling period; enabling the upper electrodes of the plurality of first (second) capacitors not to receive the first (second) input signal during a holding period, and enabling the lower electrodes of the plurality of first (second) capacitors to receive a first set (second set) of reference signals during the holding period, so that the plurality of first (second) capacitors provide a first (second) sampling voltage to the upper electrodes of the plurality of first (second) capacitors through charge redistribution during the holding period, wherein the first and second input signals are two complementary signals of a differential input signal.

Description

Technical Field

[0001] The present invention relates to a sampling and holding circuit, and more particularly to a sampling and holding circuit capable of amplifying an input signal. Background Art

[0002] In an analog-to-digital conversion process, a programmable gain amplifier (PGA) is often used to amplify an analog signal, or to adjust the peak-to-peak value of the analog signal, so as to provide an amplified analog signal to an analog-to-digital converter (ADC), enabling the analog-to-digital converter to convert the amplified analog input signal into a digital signal without distortion.

[0003] However, a programmable gain amplifier typically includes an operational amplifier, resistors, and capacitors, and has the characteristics of large circuit area and high power consumption. If the signal can be amplified by other existing circuits in the analog-to-digital conversion (such as a sampling and holding circuit), the analog-to-digital conversion can be implemented in a more economical way.

[0004] In addition, even if the programmable gain amplifier is retained, considering the limitation of the output swing of the programmable gain amplifier, if the signal can be further amplified by other existing circuits in the analog-to-digital conversion (such as a sampling and holding circuit), the effect of the analog-to-digital conversion will be better. Summary of the Invention

[0005] One object of the present disclosure is to provide a sampling and holding circuit and method capable of amplifying an input signal.

[0006] An embodiment of the sampling and holding circuit of the present disclosure includes a control circuit, a first input switch, a first group of switches, a first capacitor array, a second input switch, a second group of switches, and a second capacitor array. The control circuit is used to generate a first input switch control signal and a first group of switch control signals, and generate a second input switch control signal and a second group of switch control signals. The first (second) input switch is used to conduct during a sampling period according to the first (second) input switch control signal to receive a first (second) input signal, and is used to not conduct during a holding period according to the first group (second group) of switch control signals. The first group (second group) of switches is used to determine the conduction state of the first group (second group) of switches according to the first group (second group) of switch control signals. The first (second) capacitor array includes a plurality of first (second) capacitors coupled to the first (second) input switch and the first group (second group) of switches. The upper electrodes of the plurality of first (second) capacitors receive the first (second) input signal via the first (second) input switch during the sampling period; the lower electrodes of at least a part of the plurality of first (second) capacitors receive the second (first) input signal via the first group (second group) of switches during the sampling period; the upper electrodes of the plurality of first (second) capacitors do not receive the first (second) input signal during the holding period; the lower electrodes of the plurality of first (second) capacitors receive a first group (second group) of reference signals via the first group (second group) of switches during the holding period; the plurality of first (second) capacitors provide a first (second) sampling voltage to the upper electrodes of the plurality of first (second) capacitors through charge redistribution during the holding period. The above-mentioned first input signal and second input signal are, for example, two complementary signals of a differential input signal; since the upper and lower electrodes of at least a part of the plurality of first (second) capacitors receive the first (second) and second (first) input signals respectively during the sampling period, at least a part of the plurality of first (second) capacitors is equivalently sampled up to twice the first (second) input signal, thereby achieving the effect of amplifying the input signal.

[0007] An embodiment of the sampling and holding method of the present disclosure includes the following steps: enabling the upper electrodes of a plurality of first (second) capacitors to receive a first (second) input signal during a sampling period, and enabling the lower electrodes of at least a part of the plurality of first (second) capacitors to receive the second (first) input signal during the sampling period; enabling the upper electrodes of the plurality of first (second) capacitors not to receive the first (second) input signal during a holding period, and enabling the lower electrodes of the plurality of first (second) capacitors to receive a first set (second set) of reference signals during the holding period, so that the plurality of first (second) capacitors provide a first (second) sampling voltage to the upper electrodes of the plurality of first (second) capacitors through charge redistribution during the holding period. The above-mentioned first input signal and second input signal are, for example, two complementary signals of a differential input signal; since the upper electrodes and lower electrodes of at least a part of the plurality of first (second) capacitors receive the first (second) and second (first) input signals respectively during the sampling period, at least a part of the plurality of first (second) capacitors is equivalently upsampled to twice the first (second) input signal, thereby achieving the effect of amplifying the input signal.

[0008] Another embodiment of the sampling and holding method of the present disclosure includes the following steps: enabling the upper electrodes of a plurality of first (second) capacitors to receive a first (second) input signal during a sampling period, and enabling the lower electrodes of at least a part of the plurality of first (second) capacitors to receive a first (second) reference signal during the sampling period; enabling the upper electrodes of the plurality of first (second) capacitors not to receive the first (second) input signal during a holding period, and enabling the lower electrodes of the plurality of first (second) capacitors to receive a first set (second set) of reference signals during the holding period, so that the plurality of first (second) capacitors provide a first (second) sampling voltage to the upper electrodes of the plurality of first (second) capacitors through charge redistribution during the holding period. The above-mentioned first input signal and second input signal are, for example, two complementary signals of a differential input signal. The above-mentioned first reference signal and second reference signal are different; for example, the first (second) reference signal is, for example, x times the second (first) input signal, where x is a positive number; since the upper electrodes and lower electrodes of at least a part of the plurality of first (second) capacitors receive the first (second) reference signal respectively during the sampling period, at least a part of the plurality of first (second) capacitors is equivalently upsampled to (1 + x) times the first (second) input signal, thereby achieving the effect of amplifying the input signal.

[0009] Regarding the features, implementation and effects of the present invention, the following provides a detailed description of the preferred embodiments in conjunction with the drawings. Description of the Drawings

[0010] Figure 1 An embodiment of the sampling and holding circuit of the present disclosure is shown;

[0011] Figure 2 Illustrates Figure 1 an example of the sampling period of the sampling and holding circuit;

[0012] Figure 3 Illustrates Figure 1 an example of the holding period of the sampling and holding circuit;

[0013] Figure 4A Illustrates another embodiment of the sampling and holding circuit of the present disclosure;

[0014] Figure 4B Illustrates Figure 4A a variation of the embodiment;

[0015] Figure 5 Illustrates an embodiment of the sampling and holding method of the present disclosure; and

[0016] Figure 6 Illustrates another embodiment of the sampling and holding circuit of the present disclosure. Detailed Description

[0017] The present disclosure discloses a sampling and holding circuit and method capable of amplifying an input signal in an economical manner.

[0018] Figure 1 Illustrates an embodiment of the sampling and holding circuit of the present disclosure; Figure 2 Illustrates Figure 1 an example of the sampling phase of the sampling and holding circuit; Figure 3 Illustrates Figure 1 an example of the hold phase of the sampling and holding circuit. Figure 1 The sampling and holding circuit 100 of can be applied to a successive approximation register type analog-to-digital converter (SAR ADC); however, on the premise that it is feasible to implement, Figure 1 the sampling and holding circuit 100 of can be applied to other types of analog-to-digital converters or other circuits. Figure 1 The sampling and holding circuit 100 of includes a control circuit 110, a first input switch 120, a first set of switches 130, a first capacitor array 140, a second input switch 150, a second set of switches 160, and a second capacitor array 170. These circuits are described separately below.

[0019] Please refer to Figures 1 to 3 . The control circuit 110 is used to generate a first input switch control signal (S1) and a first set of switch control signals (S SET1 ), and generate a second input switch control signal (S2) and a second set of switch control signals (S SET2)。In this embodiment, S1 and S2 are the same two signals used to control the conduction states of the first input switch 120 and the second input switch 150; S SET1 and S SET2 are two sets of signals with the same sampling period and holding period, but S SET1 and S SET2 will have different control levels during the comparison period of a SAR ADC according to the comparison between the voltage of the first capacitor array 140 and the voltage of the second capacitor array 170. Since the SAR ADC and its comparison period are not within the scope of the present invention, they will not be described in detail in this specification.

[0020] Please refer to Figures 1 to 3 . The first input switch 120 is used to conduct according to S1 during the sampling period to receive a first input signal (V IP ), and is used to not conduct according to S1 during the holding period; similarly, the second input switch 150 is used to conduct according to S2 during the sampling period to receive a second input signal (V IN ), and is used to not conduct according to S2 during the holding period. In addition, the conduction state of the first group of switches 130 is determined by S SET1 ; similarly, the conduction state of the second group of switches 160 is determined by S SET2 .

[0021] Please refer to Figures 1 to 3 . The first capacitor array 140 includes a plurality of first capacitors (C 1_1 , C 1_2 , C 1_3 , …, C 1_(N-1) , C 1_N ) coupled to the first input switch 120 and the first group of switches 130, where the upper electrodes of the plurality of first capacitors receive V IP via the first input switch 120 during the sampling period; at least a part (e.g., Figure 2 of C 1_1 ) of the lower electrodes of the plurality of first capacitors receive V IN via the first group of switches 130 during the sampling period; the upper electrodes of the plurality of first capacitors do not receive V IP during the holding period; the lower electrodes of the plurality of first capacitors receive a first group of reference signals (REF SET1 ) (e.g., M reference voltages V R and K ground voltages GND assigned by the control circuit 110, where M and K are determined by S SET1 of the control circuit 110) via the first group of switches 130 during the holding period; the plurality of first capacitors provide a first sampling voltage (V XP)On the upper electrodes of the plurality of first capacitors. Similarly, the second capacitor array 170 includes a plurality of second capacitors (C 2_1 , C 2_2 , C 2_3 , …, C 2_(N-1) , C 2_N ) that couple the second input switch 150 to the second set of switches 160, wherein the upper electrodes of the plurality of second capacitors receive V IN via the second input switch 150 during the sampling period; at least a portion of the plurality of second capacitors (e.g., Figure 2 's C 2_1 )'s lower electrodes receive V IP via the second set of switches 160 during the sampling period; the upper electrodes of the plurality of second capacitors do not receive V IN during the holding period; the lower electrodes of the plurality of second capacitors receive a second set of reference signals (REF SET2 ) (e.g., P reference voltages V R and Q ground voltages GND assigned by the control circuit 110, where P and Q are determined by S SET2 of the control circuit 110) via the second set of switches 160 during the holding period; the plurality of second capacitors provide a second sampled voltage (V XN ) at the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period. It should be noted that REF SET1 and REF SET2 are determined according to design and implementation requirements and belong to known / self-developed technologies, which are not the subject of discussion in this invention.

[0022] Please refer to Figures 1 to 3 . In this embodiment, V IP and V IN are two complementary signals of a differential input signal. Since at least a portion of the plurality of first capacitors (e.g., Figure 2 's C 1_1 )'s upper and lower electrodes receive V IP and V IN respectively during the sampling period, this at least a portion is equivalently upsampled to twice V IP (V IP - V IN = V IP + V IP = 2V IP ), thus achieving the effect of amplifying the input signal. Similarly, since at least a portion of the plurality of second capacitors (e.g., Figure 2 's C 2_1 )'s upper and lower electrodes receive V IN and V IP respectively during the sampling period, this at least a portion is equivalently upsampled to VIN Twice of (V IN - V IP = V IN + V IN = 2V IN ), thus achieving the effect of amplifying the input signal.

[0023] Please refer to Figure 2 and Figure 3 . The plurality of first capacitors is composed of at least a part of the aforementioned plurality of first capacitors (e.g., Figure 2 C of 1_1 ) and the remaining part of the plurality of first capacitors (e.g., Figure 2 and Figure 3 C of 1_2 , C 1_3 , …, C 1_(N-1) , C 1_N ). The lower electrodes of the remaining part of the plurality of first capacitors receive REF SET1 via the first group of switches 130 during the sampling period. Similarly, the plurality of second capacitors is composed of at least a part of the aforementioned plurality of second capacitors (e.g., Figure 2 C of 2_1 ) and the remaining part of the plurality of second capacitors (e.g., Figure 2 and Figure 3 C of 2_2 , C 2_3 , …, C 2_(N-1) , C 2_N ). The lower electrodes of the remaining part of the plurality of second capacitors receive REF SET2 via the second group of switches 160 during the sampling period. It should be noted that the capacitance values of the plurality of first (second) capacitors are determined according to implementation requirements; for example, the capacitance of at least a part of the plurality of first (second) capacitors is not less than the capacitance of the remaining part of the plurality of first (second) capacitors; for another example, the capacitance values of the plurality of first (second) capacitors are decreasing capacitance values according to the requirements of the SAR ADC.

[0024] Please refer to Figures 1 to 3 . In an exemplary implementation, V IP is (V CM + dV), V IN is (V CM - dV), where V CM is a common-mode voltage and dV is a signal voltage; the capacitance value of at least a part of the plurality of first capacitors (e.g., Figure 2 C of 1_1 ) is the same as that of the remaining part of the plurality of first capacitors (e.g., Figure 2 and Figure 3 C of 1_2 , C1_3 ,..., C 1_(N-1) , C 1_N ) has a capacitance ratio of where C U is a unit capacitance value; during the sampling period, the lower electrodes of the remaining part of the plurality of first capacitors receive a reference voltage V R , so the charge taken by the plurality of first capacitors is as shown in the following formula (1):

[0025] Q = (xC U )(V IP - V IN ) + (yC U )(V IP - V R )

[0026] = (xC U )(2dV) + (yC U )(V CM + dV - V R )

[0027] = (xC U )(2dV) + (yC U )V CM + (yC U )dV - (yC U )V R

[0028] = (2xC U + yC U )(dV) + (yC U )(V CM - V R )

[0029] Formula (1)

[0030] During the holding period, the voltage of the upper electrodes of the plurality of first capacitors is the aforementioned first sampling voltage V XP , the lower electrodes of at least a part of the plurality of first capacitors receive a ground voltage GND, and the lower electrodes of the remaining part of the plurality of first capacitors receive the reference voltage V R , so the charge stored by the plurality of first capacitors is as shown in the following formula (2):

[0031] Q = (xC U )(V XP - 0) + (yC U )(V XP - V R ) = (x + y)C U V XP - yC U VR

[0032] Equation (2)

[0033] Based on charge conservation, Equation (1) should be equal to Equation (2). Therefore, V XP can be expressed as follows:

[0034]

[0035] If the aforementioned ratio equals 1 (i.e., x = y), V XP can be expressed as follows:

[0036]

[0037] Assume that the common-mode voltage V CM is 0.5V and the reference voltage V R is 1.1V. The first sampling voltage V XP of Equation (4) will be The first sampling voltage of the prior art will be relatively small (e.g., under the condition that other conditions remain unchanged (V IP = V CM + dV; x = y; V CM = 0.5V; V R = 1.1V), the lower electrodes of at least a part of the plurality of first capacitors receive the reference voltage V R during the sampling period, thereby obtaining the stored charge

[0038] Q1 = (xC U )(V IP - V R ) + (yC U )(V IP - V R ) = (x + y) × C U × (V IP - V R ).

[0039] The lower electrodes of at least a part of the plurality of first capacitors receive the ground voltage GND during the holding period, thereby obtaining the stored charge

[0040] Q2 = (xC U )(V XP - 0) + (yC U )(V XP - V R ) = (x + y)C U V XP - yC U V R .

[0041] Based on charge conservation, Q1 = Q2, thus obtaining the first sampling voltage of the prior art as (dV - 0.05V)); as described above, the first sampling voltage of this embodiment is higher than that of the prior art, and the signal amplification effect is significant.

[0042] Since those with ordinary knowledge in the art can derive the second sampling voltage V XP based on the derivation description of the foregoing first sampling voltage V XN , repeated and redundant descriptions are omitted here.

[0043] Figure 4A Shows another embodiment of the sampling and holding circuit of the present disclosure. Compared with the embodiment of Figure 1 , in the first (second) capacitor array 410 (420) of the sampling and holding circuit 400 (sampling period) of Figure 4A , the lower electrodes of all the first (second) capacitors receive the second (first) input signal V IN (V IP ) during the sampling period, so more charges can be captured, thereby achieving a stronger signal amplification effect. Figure 4B Shows a variant (sampling period) of the embodiment of Figure 4A ; compared with Figure 4A , the circuit for receiving the input signal V Figure 4B of IN (V IP ) is slightly different.

[0044] In an alternative embodiment, the first input signal V IP is a signal voltage, and the second input signal V IN is a fixed voltage, where the signal voltage generally varies with time. In an alternative embodiment, the first input signal V IP and the second input signal V IN are two complementary signals of a differential input signal, and the lower electrodes of at least a part of the plurality of first (second) capacitors receive a first (second) reference signal during the sampling period, and the first reference signal is different from the second reference signal; for example, the first (second) reference signal is, for example, x times the second (first) input signal, where x is a positive number.

[0045] Figure 5 Shows an embodiment of the sampling and holding method of the present disclosure, including the following steps:

[0046] S510: Make the upper electrodes of a plurality of first capacitors receive a first input signal during a sampling period, and make at least a part of the lower electrodes of the plurality of first capacitors receive a second input signal during the sampling period;

[0047] S520: During a holding period, the upper electrodes of the plurality of first capacitors do not receive the first input signal, and the lower electrodes of the plurality of first capacitors receive a first set of reference signals during the holding period, so that the plurality of first capacitors provide a first sampled voltage at the upper electrodes of the plurality of first capacitors through charge redistribution during the holding period;

[0048] S530: During the sampling period, the upper electrodes of the plurality of second capacitors receive the second input signal, and the lower electrodes of at least a part of the plurality of second capacitors receive the first input signal during the sampling period; and

[0049] S540: During the holding period, the upper electrodes of the plurality of second capacitors do not receive the second input signal, and the lower electrodes of the plurality of second capacitors receive a second set of reference signals during the holding period, so that the plurality of second capacitors provide a second sampled voltage at the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period.

[0050] Figure 6 Another embodiment of the sampling and holding method according to the present disclosure is shown, including the following steps:

[0051] S610: During a sampling period, the upper electrodes of the plurality of first capacitors receive a first input signal, and the lower electrodes of at least a part of the plurality of first capacitors receive a first reference signal during the sampling period;

[0052] S620: During a holding period, the upper electrodes of the plurality of first capacitors do not receive the first input signal, and the lower electrodes of the plurality of first capacitors receive a first set of reference signals during the holding period, so that the plurality of first capacitors provide a first sampled voltage at the upper electrodes of the plurality of first capacitors through charge redistribution during the holding period;

[0053] S630: During the sampling period, the upper electrodes of the plurality of second capacitors receive the second input signal, and the lower electrodes of at least a part of the plurality of second capacitors receive a second reference signal during the sampling period, where the second reference signal is different from the first reference signal; and

[0054] S640: During the holding period, the upper electrodes of the plurality of second capacitors do not receive the second input signal, and the lower electrodes of the plurality of second capacitors receive a second set of reference signals during the holding period, so that the plurality of second capacitors provide a second sampled voltage at the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period.

[0055] Since those with ordinary knowledge in the art can refer to Figures 1 to 4B the disclosure of the embodiments of Figure 5 and Figure 6 to understand the details and variations of the embodiments of Figures 1 to 4BThe technical features of the embodiments can be reasonably applied to Figure 5 and Figure 6 in the embodiments, so repeated and redundant descriptions are omitted here. It should be noted that Figure 5 and Figure 6 The steps have no order restriction on the premise that they are implemented feasibly.

[0056] Please note that on the premise that it is possible to implement, those with ordinary knowledge in the technical field can selectively implement some or all of the technical features in any of the foregoing embodiments, or selectively implement the combination of some or all of the technical features in multiple of the foregoing embodiments, thereby increasing the flexibility when implementing the present invention.

[0057] In summary, the present invention can amplify the input signal in an economical way.

[0058] Although the embodiments of the present invention are as described above, these embodiments are not used to limit the present invention. Those with ordinary knowledge in the technical field can change the technical features of the present invention according to the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to what is defined in the claims of this specification.

[0059]

Symbol Explanation

[0060] 100: Sampling and Holding Circuit

[0061] 110: Control Circuit

[0062] 120: First Input Switch

[0063] 130: First Group of Switches

[0064] 140: First Capacitor Array

[0065] 150: Second Input Switch

[0066] 160: Second Group of Switches

[0067] 170: Second Capacitor Array

[0068] C 1_1 、C 1_2 、C 1_3 、…、C 1_(N-1) 、C 1_N : Multiple First Capacitors

[0069] C 2_1 、C 2_2 、C 2_3 、…、C 2_(N-1) 、C 2_N : Multiple Second Capacitors

[0070] S1: First input switch control signal

[0071] S2: Second input switch control signal

[0072] S SET1 : First group of switch control signals

[0073] S SET2 : Second group of switch control signals

[0074] V IP : First input signal

[0075] V IN : Second input signal

[0076] REF SET1 : First group of reference signals

[0077] REF SET2 : Second group of reference signals

[0078] V XP : First sampling voltage

[0079] V XN : Second sampling voltage

[0080] 400: Sampling and holding circuit

[0081] 410: First capacitor array

[0082] 420: Second capacitor array

[0083] 510~540: Steps

[0084] 610~640: Steps.

Claims

1. A sampling and holding circuit, comprising: A control circuit for generating a first input switch control signal and a first set of switch control signals, and generating a second input switch control signal and a second set of switch control signals; A first input switch for conducting according to the first input switch control signal during a sampling period to receive a first input signal, and for not conducting according to the first set of switch control signals during a holding period; A first set of switches for determining the conduction state of the first set of switches according to the first set of switch control signals; A first capacitor array including a plurality of first capacitors coupled to the first input switch and the first set of switches, wherein the upper electrodes of the plurality of first capacitors receive the first input signal via the first input switch during the sampling period, at least a part of the lower electrodes of the plurality of first capacitors receive a second input signal via the first set of switches during the sampling period, the upper electrodes of the plurality of first capacitors do not receive the first input signal during the holding period, the lower electrodes of the plurality of first capacitors receive a first set of reference signals via the first set of switches during the holding period, and the plurality of first capacitors provide a first sampled voltage to the upper electrodes of the plurality of first capacitors through charge redistribution during the holding period; A second input switch for conducting according to the second input switch control signal during the sampling period to receive the second input signal, and for not conducting according to the second set of switch control signals during the holding period; A second set of switches for determining the conduction state of the second set of switches according to the second set of switch control signals; and A second capacitor array including a plurality of second capacitors coupled to the second input switch and the second set of switches, wherein the upper electrodes of the plurality of second capacitors receive the second input signal via the second input switch during the sampling period, at least a part of the lower electrodes of the plurality of second capacitors receive the first input signal via the second set of switches during the sampling period, the upper electrodes of the plurality of second capacitors do not receive the second input signal during the holding period, the lower electrodes of the plurality of second capacitors receive a second set of reference signals via the second set of switches during the holding period, and the plurality of second capacitors provide a second sampled voltage to the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period, wherein the plurality of first capacitors are composed of the at least a part of the plurality of first capacitors and the remaining part of the plurality of first capacitors; the lower electrodes of the remaining part of the plurality of first capacitors receive the first set of reference signals via the first set of switches during the sampling period; the plurality of second capacitors are composed of the at least a part of the plurality of second capacitors and the remaining part of the plurality of second capacitors; the lower electrodes of the remaining part of the plurality of second capacitors receive the second set of reference signals via the second set of switches during the sampling period.

2. The sampling and holding circuit according to claim 1, wherein the capacitance of at least a part of the plurality of first capacitors is not less than the capacitance of the remaining part of the plurality of first capacitors; the capacitance of at least a part of the plurality of second capacitors is not less than the capacitance of the remaining part of the plurality of second capacitors.

3. The sampling and holding circuit according to claim 1, wherein the first input signal and the second input signal are two complementary signals.

4. The sampling and holding circuit according to claim 1, wherein the first input signal is a signal voltage and the second input signal is a fixed voltage.

5. A sampling and holding method, comprising: Enabling upper electrodes of a plurality of first capacitors to receive a first input signal during a sampling period, and enabling lower electrodes of at least a part of the plurality of first capacitors to receive a second input signal during the sampling period; Enabling the upper electrodes of the plurality of first capacitors not to receive the first input signal during a holding period, and enabling the lower electrodes of the plurality of first capacitors to receive a first set of reference signals during the holding period, so that the plurality of first capacitors provide a first sampled voltage to the upper electrodes of the plurality of first capacitors through charge redistribution during the holding period; Enabling upper electrodes of a plurality of second capacitors to receive the second input signal during the sampling period, and enabling lower electrodes of at least a part of the plurality of second capacitors to receive the first input signal during the sampling period; And Enabling the upper electrodes of the plurality of second capacitors not to receive the second input signal during the holding period, and enabling the lower electrodes of the plurality of second capacitors to receive a second set of reference signals during the holding period, so that the plurality of second capacitors provide a second sampled voltage to the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period, wherein the plurality of first capacitors are composed of the at least a part of the plurality of first capacitors and the remaining part of the plurality of first capacitors; the plurality of second capacitors are composed of the at least a part of the plurality of second capacitors and the remaining part of the plurality of second capacitors; the sampling and holding method further comprises: enabling the lower electrodes of the remaining part of the plurality of first capacitors to receive the first set of reference signals during the sampling period; enabling the lower electrodes of the remaining part of the plurality of second capacitors to receive the second set of reference signals during the sampling period.

6. The sampling and holding method according to claim 5, wherein the capacitance of the at least a part of the plurality of first capacitors is not less than the capacitance of the remaining part of the plurality of first capacitors; the capacitance of the at least a part of the plurality of second capacitors is not less than the capacitance of the remaining part of the plurality of second capacitors.

7. A sampling and holding method, comprising: Enabling upper electrodes of a plurality of first capacitors to receive a first input signal during a sampling period, and enabling lower electrodes of at least a part of the plurality of first capacitors to receive a first reference signal during the sampling period; Enabling the upper electrodes of the plurality of first capacitors not to receive the first input signal during a holding period, and enabling the lower electrodes of the plurality of first capacitors to receive a first set of reference signals during the holding period, so that the plurality of first capacitors provide a first sampled voltage to the upper electrodes of the plurality of first capacitors through charge redistribution during the holding period; Enabling upper electrodes of a plurality of second capacitors to receive a second input signal during the sampling period, and enabling lower electrodes of at least a part of the plurality of second capacitors to receive a second reference signal during the sampling period, wherein the second reference signal is different from the first reference signal; And During the holding period, the upper electrodes of the plurality of second capacitors do not receive the second input signal, and the lower electrodes of the plurality of second capacitors receive a second set of reference signals during the holding period, so that the plurality of second capacitors provide a second sampled voltage to the upper electrodes of the plurality of second capacitors through charge redistribution during the holding period.

8. The sampling and holding method according to claim 7, wherein the plurality of first capacitors are composed of at least a part of the plurality of first capacitors and the remaining part of the plurality of first capacitors; the plurality of second capacitors are composed of at least a part of the plurality of second capacitors and the remaining part of the plurality of second capacitors; the sampling and holding method further includes: making the lower electrodes of the remaining part of the plurality of first capacitors receive the first set of reference signals during the sampling period; making the lower electrodes of the remaining part of the plurality of second capacitors receive the second set of reference signals during the sampling period.

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