A high-speed sampling buffer circuit for UWB systems

Abstract

The present invention discloses a high-speed sampling buffer circuit for a UWB system, comprising a driver module, a gate voltage bootstrap switch module, and a sampling module. The driver module is used to input a differential signal to be sampled and reduce the output impedance of the sampled differential signal to improve the subsequent driving capability of the gate voltage bootstrap switch module and the sampling module. The gate voltage bootstrap switch module is used to control the opening and closing of the sampling switch, controlling the gate voltage change of the sampling switch to track the changes in the output differential signal of the driver module and keep the gate-source voltage of the sampling switch constant during the changes in the output differential signal. The sampling module is used to sample the differential signal to be sampled when the sampling switch is open to obtain a sampled signal. The buffer circuit comprises a driver module, a gate voltage bootstrap switch module, and a sampling module. The driver module is composed of a high-linearity common-drain amplifier, which improves the linearity of the sampling circuit. The sampling module and the driver module use a charge-flipping structure to achieve sampling.

Description

Technical Field

[0001] The present invention belongs to the technical field of mixed signal integrated circuits, and in particular relates to a high-speed sampling buffer circuit for a UWB system. Background Art

[0002] The concept of UWB (Ultra Wide Band) was first proposed in the 1960s, using a carrier-less, narrow pulse signal for communication. UWB has significant application value in military and radar fields due to its superior security, high transmission rate, and high range resolution. The Federal Communications Commission (FCC) stipulates that the operating frequency of UWB is 3.1 to 10.6 GHz, with a transmission bandwidth greater than 500 MHz. However, to prevent interference between UWB and other communication bandwidths, the transmitter power is limited to an effective isotropic radiated power of less than -41.2 dBm / MHz. Beyond its military radar applications, UWB systems are also finding significant application in commercial scenarios such as biodetection and indoor positioning.

[0003] The front end of the ultra-wideband system inputs the received high-frequency and high-speed signal to the subsequent ADC (Analog-to-Digital Converter). In the UWB system, the ADC needs to directly sample the high-speed RF signal. The traditional sampling network structure is as follows: (1) Open-loop sampling circuit, which includes an input buffer stage and an output buffer stage, a sampling switch S and a holding capacitor CH. However, this structure is seriously affected by the charge injection effect. The charge injection of the sampling switch is related to the input signal, resulting in serious nonlinear problems. (2) Closed-loop sampling circuit structure, in order to suppress the input-related error of the sampling circuit, the sampling switch can be placed in the feedback loop so that the voltage swing of its source and drain terminals is much smaller than the signal swing of the input and output terminals. However, this structure constitutes a two-stage operational amplifier with unit gain negative feedback due to the closed-loop structure, which will greatly limit the stability and speed. In addition, the influence of parasitic capacitance will cause signal feedthrough. (3) Switched capacitor sampling circuit, which includes three MOS switches (S1, S2 and S3), a holding capacitor CH and a transconductance operational amplifier Gm. When S1 and S2 are closed, the circuit's op amp operates in unity-gain negative feedback mode, resulting in a low input impedance and forming a sampling circuit. When S1 and S2 are closed and S3 is open, the circuit switches to a hold state. This structure also affects circuit performance due to charge injection, clock feedthrough, and aperture time. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-speed sampling buffer circuit for a UWB system. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a high-speed sampling buffer circuit for a UWB system, comprising a driving module, a gate voltage bootstrap switch module and a sampling module, wherein:

[0006] The driving module is used to input the differential signal to be sampled and reduce the output impedance of the differential signal to be sampled, so as to improve the subsequent driving capability of the gate voltage bootstrap switch module and the sampling module;

[0007] The gate voltage bootstrap switch module is used to control the opening and closing of the sampling switch, and controls the gate voltage change of the sampling switch to track the change of the output differential signal of the driving module and keep the gate-source voltage of the sampling switch constant during the change of the output differential signal;

[0008] The sampling module is used to sample the differential signal to be sampled when the sampling switch is turned on, so as to obtain a sampling signal.

[0009] In one embodiment of the present invention, the driving module includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8, wherein:

[0010] The source of the first NMOS transistor NM1 and the source of the sixth NMOS transistor NM6 are both connected to the ground terminal GND, and the gate of the first NMOS transistor NM1 and the gate of the sixth NMOS transistor NM6 are both input with a first bias voltage V BIAS1 , the drain of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2, and the drain of the sixth NMOS transistor NM6 is connected to the source of the seventh NMOS transistor NM7;

[0011] The gate of the second NMOS transistor NM2 and the gate of the seventh NMOS transistor NM7 are both input with the second bias voltage V BIAS2 , the drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3 and serves as the first output terminal X1 of the entire driving module, and the drain of the seventh NMOS transistor NM7 is connected to the source of the eighth NMOS transistor NM8 and serves as the second output terminal X2 of the entire driving module;

[0012] The drain of the third NMOS transistor NM3 is connected to the source of the fourth NMOS transistor NM4, the second capacitor C2 is connected between the first input terminal X1 of the driving module and the gate of the third NMOS transistor NM3, the drain of the eighth NMOS transistor NM8 is connected to the source of the ninth NMOS transistor NM9, and the sixth capacitor C6 is connected between the second input terminal X2 of the driving module and the gate of the eighth NMOS transistor NM8;

[0013] One end of the first resistor R1 is input with a third bias voltage V BIAS3 , the other end is connected to the gate of the third NMOS transistor NM3, the first capacitor C1 is connected between the first input terminal INP of the driving module and the source of the second NMOS transistor NM2, and one end of the fourth resistor R4 inputs the third bias voltage V BIAS3 , the other end is connected to the gate of the eighth NMOS transistor NM8, and the fifth capacitor C5 is connected between the second input terminal INN of the driving module and the source of the seventh NMOS transistor NM7;

[0014] The drain of the fourth NMOS transistor NM4 is connected to the source of the fifth NMOS transistor NM5, and one end of the second resistor R2 is input with a fourth bias voltage V BIAS4 , the other end is connected to the gate of the fourth NMOS tube NM4; the drain of the ninth NMOS tube NM9 is connected to the source of the tenth NMOS tube NM10, and one end of the fifth resistor R5 inputs the fourth bias voltage V BIAS4 , the other end is connected to the gate of the ninth NMOS transistor NM9;

[0015] The drain of the fifth NMOS transistor NM5 and the drain of the tenth NMOS transistor NM10 are both connected to the power supply terminal VDD, and one end of the third resistor R3 inputs the fifth bias voltage V BIAS5 , the other end is connected to the gate of the fifth NMOS tube NM5; one end of the sixth resistor R6 inputs the fifth bias voltage V BIAS5 , the other end is connected to the gate of the tenth NMOS transistor NM10;

[0016] The third capacitor C3 is connected between the first input terminal INP of the driving module and the gate of the fourth NMOS transistor NM4, the fourth capacitor C4 is connected between the gate of the fourth NMOS transistor NM4 and the gate of the fifth NMOS transistor NM5, the seventh capacitor C7 is connected between the second input terminal INN of the driving module and the gate of the ninth NMOS transistor NM9, and the eighth capacitor C8 is connected between the gate of the ninth NMOS transistor NM9 and the gate of the tenth NMOS transistor NM10.

[0017] In one embodiment of the present invention, the gate voltage bootstrap switch module includes a first gate voltage bootstrap unit, a first switch tube M1, a second gate voltage bootstrap unit and a second switch tube M2, wherein:

[0018] The input end of the first gate voltage bootstrap unit is connected to the first output end X1 of the driving module and inputs the first clock signal CLKP and the second clock signal CLKN respectively. The output end X3 of the first gate voltage bootstrap unit is connected to the gate of the first switch tube M1. The drain of the first switch tube M1 is connected to the first output end X1 of the driving module.

[0019] The input end of the second gate voltage bootstrap unit is connected to the second output end X2 of the driving module and inputs the first clock signal CLKP and the second clock signal CLKN respectively. The output end X4 of the second gate voltage bootstrap unit is connected to the gate of the second switch tube M2, and the drain of the second switch tube M2 is connected to the second output end X2 of the driving module.

[0020] In one embodiment of the present invention, the first gate voltage bootstrap switch unit includes a first PMOS transistor PM1, a second PMOS transistor PM2, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, a fifteenth NMOS transistor NM15, a sixteenth NMOS transistor NM16, a seventeenth NMOS transistor NM17, an eighteenth NMOS transistor NM18, a nineteenth NMOS transistor NM19, a twentieth NMOS transistor NM20, a ninth capacitor C9, a tenth capacitor C10, and an inverter I1, wherein:

[0021] The gate of the first PMOS transistor PM1 and the gate of the eleventh NMOS transistor NM11 are both input with the first clock signal CLKP; the gate of the twelfth NMOS transistor NM12 is input with the second clock signal CLKN;

[0022] The source of the first PMOS transistor PM1, the gate and drain of the thirteenth NMOS transistor NM13, the drain of the fourteenth NMOS transistor NM14, and the gate of the eighteenth NMOS transistor NM18 are all connected to the power supply terminal; the drain of the first PMOS transistor PM1 is simultaneously connected to the drain of the eleventh NMOS transistor NM11, the gate of the second PMOS transistor PM2, and the drain of the fifteenth NMOS transistor NM15; the ninth capacitor C9 is connected between the source of the thirteenth NMOS transistor NM13 and the gate of the twelfth NMOS transistor NM12; the tenth capacitor C10 is connected between the source of the fourteenth NMOS transistor NM14 and the drain of the twelfth NMOS transistor NM12; the source of the twelfth NMOS transistor NM12 is connected to the ground terminal;

[0023] The source of the second PMOS transistor PM2 is connected to the source of the fourteenth NMOS transistor NM14, the drain of the second PMOS transistor PM2 is connected to the drain of the eighteenth NMOS transistor NM18, the source of the eighteenth NMOS transistor NM18 is connected to the drain of the nineteenth NMOS transistor NM19, the source of the nineteenth NMOS transistor NM19 is connected to the ground terminal, and the inverter I1 is connected between the gate of the eleventh NMOS transistor NM11 and the gate of the nineteenth NMOS transistor NM19;

[0024] The source of the fifteenth NMOS transistor NM15 and the source of the sixteenth NMOS transistor NM16 are both connected to the drain of the twelfth NMOS transistor NM12, and the gate of the fifteenth NMOS transistor NM15 is respectively connected to the gate of the sixteenth NMOS transistor NM16, the gate of the seventeenth NMOS transistor NM17, and the drain of the eighteenth NMOS transistor NM18;

[0025] The drain of the sixteenth NMOS transistor NM16 and the drain of the seventeenth NMOS transistor NM17 are simultaneously connected to the first output terminal X1 of the driving module, the substrate of the sixteenth NMOS transistor NM16 is connected to the source of the seventeenth NMOS transistor NM17 and the drain of the twentieth NMOS transistor NM20, the source of the twentieth NMOS transistor NM20 is connected to the ground terminal, the gate of the twentieth NMOS transistor NM20 inputs the substrate modulation clock signal Bulk_ctr, and the gate of the seventeenth NMOS transistor NM17 serves as the output terminal X3 of the first gate voltage bootstrap switch unit and is connected to the gate of the first switch transistor M1.

[0026] In one embodiment of the present invention, the first clock signal CLKP and the second clock signal CLKN are inverted signals, and the substrate modulation clock signal Bulk_ctr is a clock signal obtained by delaying the second clock signal CLKN by a predetermined amount.

[0027] In one embodiment of the present invention, the sampling module includes an eleventh capacitor C11, a twelfth capacitor C12, a twenty-first NMOS transistor NM21, a twenty-second NMOS transistor NM22, a twenty-third NMOS transistor NM23, a twenty-fourth NMOS transistor NM24, a twenty-fifth NMOS transistor NM25, a twenty-sixth NMOS transistor NM26, and an operational amplifier I2, wherein:

[0028] The eleventh capacitor C11 is connected between the source of the first switch tube M1 and the positive input terminal of the operational amplifier I2, and the twelfth capacitor C12 is connected between the source of the second switch tube M2 and the negative input terminal of the operational amplifier I2;

[0029] The gate of the twenty-first NMOS transistor NM21 and the gate of the twenty-second NMOS transistor NM22 are both input with the first clock signal CLKP, the drain of the twenty-first NMOS transistor NM21 and the drain of the twenty-second NMOS transistor NM22 are both input with the common mode voltage VCM, the source of the twenty-first NMOS transistor NM21 is connected to the positive input terminal of the operational amplifier I2, and the source of the twenty-second NMOS transistor NM22 is connected to the negative input terminal of the operational amplifier I2;

[0030] The gates of the twenty-third NMOS transistor NM23 and the twenty-fourth NMOS transistor NM24 are both input with the second clock signal CLKN, the drain of the twenty-third NMOS transistor NM23 is connected to the source of the first switch transistor M1, the source of the twenty-third NMOS transistor NM23 is connected to the drain of the twenty-fifth NMOS transistor NM25, the drain of the twenty-fourth NMOS transistor NM24 is connected to the source of the second switch transistor M2, and the source of the twenty-fourth NMOS transistor NM24 is connected to the drain of the twenty-sixth NMOS transistor NM26;

[0031] The gate of the twenty-fifth NMOS transistor NM25 and the gate of the twenty-sixth NMOS transistor NM26 are both input with the first clock signal CLKP, and the source of the twenty-fifth NMOS transistor NM25 and the source of the twenty-sixth NMOS transistor NM26 are both input with the common mode voltage VCM;

[0032] The positive output terminal of the operational amplifier I2 serves as the first output terminal OUTP of the sampling module, and the negative output terminal of the operational amplifier I2 serves as the second output terminal OUTN of the sampling module.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. The high-speed sampling buffer circuit for the UWB system of the present invention comprises a driving module, a gate voltage bootstrap switch module and a sampling module. The driving module is composed of a high-linearity common-drain amplifier, which improves the linearity of the sampling circuit. The common-gate compensation structure is adopted to increase the gain of the driving module and improve the driving capability of the radio frequency signal to the subsequent stage.

[0035] 2. The dual-capacitor structure in the gate voltage bootstrap switch module enables rapid capacitor charging, improving sampling speed and making it suitable for high-speed sampling systems. The bootstrap switch tube has a low on-resistance and does not change with changes in the input signal, ensuring high linearity of the overall sampling circuit.

[0036] 3. The high-speed sampling buffer of the present invention realizes direct sampling and input of RF signals into the subsequent ADC by combining a driving module, a gate bootstrap switch and a charge flip module composed of an operational amplifier, thereby improving the data transmission rate and quality of the UWB system and meeting the UWB system's requirements for sampling circuits.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 1 is a schematic diagram of a module of a high-speed sampling buffer circuit for a UWB system provided by an embodiment of the present invention;

[0039] Figure 2 is a circuit diagram of a driving module provided by an embodiment of the present invention;

[0040] Figure 3 1 is a circuit diagram of a high-speed sampling buffer circuit for a UWB system provided by an embodiment of the present invention;

[0041] Figure 4 is a circuit diagram of a first gate voltage bootstrap switch unit provided by an embodiment of the present invention;

[0042] Figure 5 is a timing diagram of related signals provided by an embodiment of the present invention;

[0043] Figure 6 This is another timing diagram of related signals provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a high-speed sampling buffer circuit for a UWB system proposed in accordance with the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0046] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0047] Example 1

[0048] See Figure 1 , Figure 1 This is a module diagram of a high-speed sampling buffer circuit for a UWB system provided by an embodiment of the present invention. The high-speed sampling buffer circuit of this embodiment includes a driving module 1, a gate voltage bootstrap switch module 2 and a sampling module 3. The driving module 1 is used to input the differential signal to be sampled and reduce the output impedance of the differential signal to be sampled, so as to improve the subsequent driving capability of the gate voltage bootstrap switch module 2 and the sampling module 3. Specifically, the driving module 1 is used to improve the output driving capability of the front-end RF front-end circuit. Generally, the front-end circuit is an RF front-end circuit, and its output signal driving capability is weak, and it is difficult to directly drive the load of the rear-stage sampling capacitor. Therefore, the driving module 1 is introduced to isolate the RF front-end circuit from the rear-stage sampling module.

[0049] The gate voltage bootstrap switch module 2 is used to control the opening and closing of the sampling switch. It controls the gate voltage changes of the sampling switch to track the changes in the output differential signal of the driver module 1, and maintains the gate-source voltage of the sampling switch constant during the changes in the output differential signal. The gate voltage bootstrap switch module 2 is used to improve the linearity of the sampling switch. If a MOS transistor is used directly as the switch, the gate-source voltage Vgs of the switch will change with the input voltage due to the changing input signal, thereby deteriorating the linearity of the sampling switch. Therefore, the gate voltage bootstrap switch module 2 is introduced to track the gate voltage changes of the MOS switch tube with the changes in the input signal, thereby maintaining the gate-source voltage Vgs of the switch tube constant during the changes in the input signal, thereby ensuring the overall linearity of the sampling circuit.

[0050] The sampling module 3 is used to sample the differential signal to be sampled when the sampling switch is turned on to obtain a sampled signal. In other words, it is used to quantize the high-speed continuous signal output by the driving module into a low-speed discrete signal and output the quantized value through the charge inversion structure.

[0051] See Figure 2 , Figure 2: This is a circuit diagram of a driving module provided by an embodiment of the present invention. The driving module 1 of this embodiment is a common-drain amplifier, which specifically includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8.

[0052] The source of the first NMOS transistor NM1 and the source of the sixth NMOS transistor NM6 are both connected to the ground terminal GND, and the gate of the first NMOS transistor NM1 and the gate of the sixth NMOS transistor NM6 are both input with the first bias voltage V BIAS1 The drain of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2, and the drain of the sixth NMOS transistor NM6 is connected to the source of the seventh NMOS transistor NM7; the gates of the second NMOS transistor NM2 and the seventh NMOS transistor NM7 are both input with the second bias voltage V BIAS2 The drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3 and serves as the first output terminal X1 of the entire driving module 1. The drain of the seventh NMOS transistor NM7 is connected to the source of the eighth NMOS transistor NM8 and serves as the second output terminal X2 of the entire driving module 1.

[0053] The drain of the third NMOS transistor NM3 is connected to the source of the fourth NMOS transistor NM4. The second capacitor C2 is connected between the first input terminal X1 of the driving module 1 and the gate of the third NMOS transistor NM3. The drain of the eighth NMOS transistor NM8 is connected to the source of the ninth NMOS transistor NM9. The sixth capacitor C6 is connected between the second input terminal X2 of the driving module 1 and the gate of the eighth NMOS transistor NM8. One end of the first resistor R1 is input with a third bias voltage V BIAS3 The other end is connected to the gate of the third NMOS transistor NM3, the first capacitor C1 is connected between the first input terminal INP of the driving module 1 and the source of the second NMOS transistor NM2, and one end of the fourth resistor R4 inputs the third bias voltage V BIAS3 , the other end is connected to the gate of the eighth NMOS transistor NM8 , and the fifth capacitor C5 is connected between the second input terminal INN of the driving module 1 and the source of the seventh NMOS transistor NM7 .

[0054] The drain of the fourth NMOS transistor NM4 is connected to the source of the fifth NMOS transistor NM5, and one end of the second resistor R2 is input with a fourth bias voltage V BIAS4The other end is connected to the gate of the fourth NMOS tube NM4; the drain of the ninth NMOS tube NM9 is connected to the source of the tenth NMOS tube NM10, and one end of the fifth resistor R5 inputs the fourth bias voltage V BIAS4 The other end is connected to the gate of the ninth NMOS transistor NM9; the drain of the fifth NMOS transistor NM5 and the drain of the tenth NMOS transistor NM10 are both connected to the power supply terminal VDD, and one end of the third resistor R3 inputs the fifth bias voltage V BIAS5 , the other end is connected to the gate of the fifth NMOS tube NM5; one end of the sixth resistor R6 inputs the fifth bias voltage V BIAS5 , and the other end is connected to the gate of the tenth NMOS transistor NM10; the third capacitor C3 is connected between the first input terminal INP of the driving module 1 and the gate of the fourth NMOS transistor NM4, the fourth capacitor C4 is connected between the gate of the fourth NMOS transistor NM4 and the gate of the fifth NMOS transistor NM5, the seventh capacitor C7 is connected between the second input terminal INN of the driving module 1 and the gate of the ninth NMOS transistor NM9, and the eighth capacitor C8 is connected between the gate of the ninth NMOS transistor NM9 and the gate of the tenth NMOS transistor NM10.

[0055] In this embodiment, if Figure 5 As shown, the signals inputted to the first input terminal INP and the second input terminal INN of the driving module 1 are inverse signals. The signals inputted to the first output terminal X1 and the second output terminal X2 of the driving module 1 are also inverse signals.

[0056] Further, see Figure 3 , Figure 3 This is a circuit diagram of a high-speed sampling buffer circuit for a UWB system provided by an embodiment of the present invention. The gate voltage bootstrap switch module 2 of this embodiment includes a first gate voltage bootstrap unit, a first switch tube M1, a second gate voltage bootstrap unit, and a second switch tube M2. The input end of the first gate voltage bootstrap unit is connected to the first output end X1 of the driving module 1 and inputs the first clock signal CLKP and the second clock signal CLKN respectively. The output end X3 of the first gate voltage bootstrap unit is connected to the gate of the first switch tube M1, and the drain of the first switch tube M1 is connected to the first output end X1 of the driving module 1; the input end of the second gate voltage bootstrap unit is connected to the second output end X2 of the driving module 1 and inputs the first clock signal CLKP and the second clock signal CLKN respectively. The output end X4 of the second gate voltage bootstrap unit is connected to the gate of the second switch tube M2, and the drain of the second switch tube M2 is connected to the second output end X2 of the driving module 1.

[0057] Further, see Figure 4 , Figure 4This is a circuit diagram of a first gate voltage bootstrap switch unit provided by an embodiment of the present invention. The first gate voltage bootstrap switch unit includes a first PMOS transistor PM1, a second PMOS transistor PM2, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, a fifteenth NMOS transistor NM15, a sixteenth NMOS transistor NM16, a seventeenth NMOS transistor NM17, an eighteenth NMOS transistor NM18, a nineteenth NMOS transistor NM19, a twentieth NMOS transistor NM20, a ninth capacitor C9, a tenth capacitor C10, and an inverter I1.

[0058] The gate of the first PMOS transistor PM1 and the gate of the eleventh NMOS transistor NM11 are both input with the first clock signal CLKP; the gate of the twelfth NMOS transistor NM12 is input with the second clock signal CLKN; the source of the first PMOS transistor PM1, the gate and drain of the thirteenth NMOS transistor NM13, the drain of the fourteenth NMOS transistor NM14, and the gate of the eighteenth NMOS transistor NM18 are all connected to the power supply terminal; the drain of the first PMOS transistor PM1 is simultaneously connected to the drain of the eleventh NMOS transistor NM11, the gate of the second PMOS transistor PM2, and the drain of the fifteenth NMOS transistor NM15; the ninth capacitor C9 is connected between the source of the thirteenth NMOS transistor NM13 and the gate of the twelfth NMOS transistor NM18. The first and second PMOS transistors NM11 and NM12 are connected between the gate of the first NMOS transistor NM11 and the drain of the first NMOS transistor NM12, the tenth capacitor C10 is connected between the source of the fourteenth NMOS transistor NM14 and the drain of the twelfth NMOS transistor NM12, the source of the twelfth NMOS transistor NM12 is connected to the ground terminal; the source of the second PMOS transistor PM2 is connected to the source of the fourteenth NMOS transistor NM14, the drain of the second PMOS transistor PM2 is connected to the drain of the eighteenth NMOS transistor NM18, the source of the eighteenth NMOS transistor NM18 is connected to the drain of the nineteenth NMOS transistor NM19, the source of the nineteenth NMOS transistor NM19 is connected to the ground terminal, and the inverter I1 is connected between the gate of the eleventh NMOS transistor NM11 and the gate of the nineteenth NMOS transistor NM19.

[0059] The source of the fifteenth NMOS transistor NM15 and the source of the sixteenth NMOS transistor NM16 are both connected to the drain of the twelfth NMOS transistor NM12. The gate of the fifteenth NMOS transistor NM15 is respectively connected to the gate of the sixteenth NMOS transistor NM16, the gate of the seventeenth NMOS transistor NM17, and the drain of the eighteenth NMOS transistor NM18. The drain of the sixteenth NMOS transistor NM16 and the drain of the seventeenth NMOS transistor NM17 are simultaneously connected to the first output terminal X1 of the driving module 1. The substrate of the sixteenth NMOS transistor NM16 is connected to the source of the seventeenth NMOS transistor NM17 and the drain of the twentieth NMOS transistor NM20. The source of the twentieth NMOS transistor NM20 is connected to the ground terminal. The gate of the twentieth NMOS transistor NM20 inputs the substrate modulation clock signal Bulk_ctr. The gate of the seventeenth NMOS transistor NM17 serves as the output terminal X3 of the first gate voltage bootstrap switch unit and is connected to the gate of the first switch transistor M1.

[0060] Furthermore, if Figure 5 and Figure 6 As shown, the first clock signal CLKP and the second clock signal CLKN are inverted signals, and the substrate modulation clock signal Bulk_ctr is a clock signal obtained by delaying the second clock signal CLKN by a predetermined amount.

[0061] Further, see Figure 3 The sampling module 3 of this embodiment includes an eleventh capacitor C11, a twelfth capacitor C12, a twenty-first NMOS transistor NM21, a twenty-second NMOS transistor NM22, a twenty-third NMOS transistor NM23, a twenty-fourth NMOS transistor NM24, a twenty-fifth NMOS transistor NM25, a twenty-sixth NMOS transistor NM26, and an operational amplifier I2.

[0062] The eleventh capacitor C11 is connected between the source of the first switch tube M1 and the positive input terminal of the operational amplifier I2, and the twelfth capacitor C12 is connected between the source of the second switch tube M2 and the negative input terminal of the operational amplifier I2; the gate of the twenty-first NMOS tube NM21 and the gate of the twenty-second NMOS tube NM22 are both input with the first clock signal CLKP, the drain of the twenty-first NMOS tube NM21 and the drain of the twenty-second NMOS tube NM22 are both input with the common mode voltage VCM, the source of the twenty-first NMOS tube NM21 is connected to the positive input terminal of the operational amplifier I2, and the gate of the twenty-second NMOS tube NM22 is both input with the common mode voltage VCM. The source of the MOS transistor NM22 is connected to the negative input terminal of the operational amplifier I2; the gates of the twenty-third NMOS transistor NM23 and the twenty-fourth NMOS transistor NM24 are both input with the second clock signal CLKN; the drain of the twenty-third NMOS transistor NM23 is connected to the source of the first switching transistor M1; the source of the twenty-third NMOS transistor NM23 is connected to the drain of the twenty-fifth NMOS transistor NM25; the drain of the twenty-fourth NMOS transistor NM24 is connected to the source of the second switching transistor M2; and the source of the twenty-fourth NMOS transistor NM24 is connected to the drain of the twenty-sixth NMOS transistor NM26.

[0063] The first clock signal CLKP is input to the gate of the twenty-fifth NMOS transistor NM25 and the gate of the twenty-sixth NMOS transistor NM26, and the common-mode voltage VCM is input to the source of the twenty-fifth NMOS transistor NM25 and the source of the twenty-sixth NMOS transistor NM26. The positive output terminal of the operational amplifier I2 serves as the first output terminal OUTP of the sampling module, and the negative output terminal of the operational amplifier I2 serves as the second output terminal OUTN of the sampling module.

[0064] Furthermore, the high-speed sampling buffer circuit of this embodiment uses an ultra-high-bandwidth, high-linearity source follower to drive the subsequent ultra-high-speed sampling circuit, addressing the difficulty of weak RF signal output drive capability. A gate voltage bootstrap switch module is also introduced to improve the linearity of the sampling switch. Finally, an operational amplifier implements charge flipping, allowing the sampled low-speed signal to directly drive the subsequent circuit, thus forming a bridge between the RF signal and the ADC.

[0065] Driver module 1 utilizes a common-drain amplifier to achieve a drive capability exceeding 10 GHz bandwidth. By introducing a two-layer common-drain structure at the drain terminals of input transistors NM3 and NM8 and implementing signal input through AC coupling, variations in the voltage Vds between the source and drain terminals of input transistors NM3 and NM8 are minimized, thereby improving the overall linearity of the driver circuit. AC coupling also couples the signal to the common-gate transistor at the source terminals of input transistors NM3 and NM8, compensating for the gain loss of the common-drain amplifier. Ultimately, the driver module achieves a final gain exceeding 0 dB and a bandwidth exceeding 10 GHz. Low-threshold-voltage MOS transistors are introduced into gate-voltage bootstrap switch module 2 to achieve input signal tracking exceeding 10 GHz. Sampling module 3 is a charge-flip sampling circuit that directly outputs the sampled signal to drive a lower-speed ADC in the subsequent stage.

[0066] Specifically, the specific principles of the high-speed sampling buffer circuit of the embodiment of the present invention are as follows:

[0067] First, a high-drive, high-linearity common-drain amplifier drives the subsequent sampling circuit and gate voltage bootstrap circuit, improving the linearity of the sampling circuit. During the high-level period of the first clock signal CLKP, switches M1 and M2, as well as NMOS transistors NM21, NM22, NM25, and NM26, conduct, charging the input signal to sampling capacitors C11 and C12, and the lower-level board is AC-grounded. Simultaneously, NMOS transistors NM23 and NM24 are turned off, placing the circuit in the sampling phase and operational amplifier I2 in an open-loop state. During the low-level period of the first clock signal CLKP, switches M1 and M2, as well as NMOS transistors NM21, NM22, NM25, and NM26, are turned off, while NMOS transistors NM23 and NM24 are turned on. The sampled charge is transferred to the output, and the sampling circuit enters the hold phase. Ultimately, the overall sampling buffer circuit achieves a 10GHz input signal and a 60dB signal-to-noise ratio output after sampling, achieving high linearity.

[0068] like Figure 2 As shown in FIG, the driving module 1 adopts a source-follower structure to achieve low output impedance and has strong driving capability. However, due to the large fluctuation of the source-drain voltage vds in the traditional common-drain amplifier, the overall linearity is poor and it is difficult to achieve a high effective number of bits. Therefore, the following is introduced: Figure 2 The structure shown improves driver-stage linearity by stacking NMOS transistors NM4, NM5, NM9, and NM10 for a common-source input. Furthermore, while conventional common-drain amplifiers typically have a gain less than 0 dB and exhibit significant gain attenuation, this embodiment's common-drain amplifier incorporates NMOS transistors NM2 and NM7 and capacitors C1 and C5 to form a common-gate amplifier, compensating for the gain loss introduced by conventional common-drain amplifiers. Ultimately, this embodiment achieves an in-band gain greater than 0 dB, with an in-band gain ripple less than 1 dB.

[0069] The gate voltage bootstrap unit of this embodiment and the input and output signals are as follows Figure 3 and Figure 6 As shown, during the low level period of the first clock signal CLKP, NM19 is turned on to ground the output node X3. At the same time, NM12 and NM13 are turned on, and the node A is charged to 2*VDD. The acceleration NM14 is turned on, and the capacitor C10 is charged to VDD. The bootstrap switch is in the holding stage. At this time, the control signal Ctrl_o of the output node X3 outputs a low level. Figure 1 Switch M1 is in the off state. When the first clock signal CLKP rises, NM12 turns off, NM14 turns off, NM17 and PM2 turn on, capacitor C10 begins to discharge, and the voltage of output signal Ctrl_o at output node X3 becomes VDD + Vin (Vin is the voltage signal at terminal X1), tracking the input signal, thereby maintaining a constant gate-source voltage (VGS) of switch M1.

[0070] Compared with the traditional gate voltage bootstrap switching circuit, the gate voltage bootstrap unit of this embodiment introduces a dual capacitor structure to accelerate the charging of the capacitor. At the same time, the introduction of the switch tube M1 accelerates the rapid opening of the PMOS tube PM2, thereby improving the overall linearity. In addition, due to the influence of the NM17 substrate modulation effect, the linearity of the sampling circuit is reduced. Therefore, the following is adopted: Figure 3 The substrate and source terminals of NM18 and NM20 shown are short-circuited during the sampling phase, thereby further improving the linearity of the sampling circuit.

[0071] In summary, the high-speed sampling buffer circuit of the embodiment of the present invention is composed of a driving module, a gate voltage bootstrap switch module and a sampling module. The driving module is composed of a high-linearity common-drain amplifier, which improves the linearity of the sampling circuit, and adopts a common-gate compensation structure to improve the gain of the driving module and the driving ability of the RF signal to the subsequent stage. In the gate voltage bootstrap switch module, by adopting a dual-capacitor structure, the rapid charging of the capacitor is achieved, the sampling speed is improved, and it is suitable for use in a high-speed sampling system. The on-resistance of the bootstrap switch tube is small and does not change with the change of the input signal, ensuring that the overall sampling circuit has high linearity. In addition, the high-speed sampling buffer of this embodiment, by combining the charge flip module composed of the driving module, the gate bootstrap switch and the operational amplifier, realizes the direct sampling of the RF signal into the subsequent ADC, improves the data transmission rate and data transmission quality of the UWB system, and meets the requirements of the UWB system for the sampling circuit.

[0072] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-speed sampling buffer circuit for a UWB system, characterized in that: It comprises a driving module (1), a gate voltage bootstrap switch module (2) and a sampling module (3), wherein: The driving module (1) is used to input a differential signal to be sampled and reduce the output impedance of the differential signal to be sampled, so as to improve the subsequent driving capability of the gate voltage bootstrap switch module (2) and the sampling module (3); The gate voltage bootstrap switch module (2) is used to control the opening and closing of the sampling switch, controlling the gate voltage change of the sampling switch to track the change of the output differential signal of the driving module (1) and keeping the gate-source voltage of the sampling switch constant during the change of the output differential signal; The sampling module (3) is used to sample the differential signal to be sampled when the sampling switch is turned on, so as to obtain a sampling signal; The driving module (1) comprises a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, wherein: The source of the first NMOS transistor NM1 and the source of the sixth NMOS transistor NM6 are both connected to the ground terminal GND, and the gate of the first NMOS transistor NM1 and the gate of the sixth NMOS transistor NM6 are both input with a first bias voltage V BIAS1 , the drain of the first NMOS transistor NM1 is connected to the source of the second NMOS transistor NM2, and the drain of the sixth NMOS transistor NM6 is connected to the source of the seventh NMOS transistor NM7; The gate of the second NMOS transistor NM2 and the gate of the seventh NMOS transistor NM7 are both input with the second bias voltage V BIAS2 The drain of the second NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3 and serves as the first output terminal X1 of the entire driving module (1); the drain of the seventh NMOS transistor NM7 is connected to the source of the eighth NMOS transistor NM8 and serves as the second output terminal X2 of the entire driving module (1); The drain of the third NMOS transistor NM3 is connected to the source of the fourth NMOS transistor NM4, the second capacitor C2 is connected between the first input terminal X1 of the driving module (1) and the gate of the third NMOS transistor NM3, the drain of the eighth NMOS transistor NM8 is connected to the source of the ninth NMOS transistor NM9, and the sixth capacitor C6 is connected between the second input terminal X2 of the driving module (1) and the gate of the eighth NMOS transistor NM8; One end of the first resistor R1 is input with a third bias voltage V BIAS3 , the other end is connected to the gate of the third NMOS tube NM3, the first capacitor C1 is connected between the first input terminal INP of the driving module (1) and the source of the second NMOS tube NM2, and one end of the fourth resistor R4 inputs the third bias voltage V BIAS3 , the other end is connected to the gate of the eighth NMOS transistor NM8, and the fifth capacitor C5 is connected between the second input terminal INN of the driving module (1) and the source of the seventh NMOS transistor NM7; The drain of the fourth NMOS transistor NM4 is connected to the source of the fifth NMOS transistor NM5, and one end of the second resistor R2 is input with a fourth bias voltage V BIAS4 , the other end is connected to the gate of the fourth NMOS tube NM4; the drain of the ninth NMOS tube NM9 is connected to the source of the tenth NMOS tube NM10, and one end of the fifth resistor R5 inputs the fourth bias voltage V BIAS4 , the other end is connected to the gate of the ninth NMOS transistor NM9; The drain of the fifth NMOS transistor NM5 and the drain of the tenth NMOS transistor NM10 are both connected to the power supply terminal VDD, and one end of the third resistor R3 inputs the fifth bias voltage V BIAS5 , the other end is connected to the gate of the fifth NMOS tube NM5; one end of the sixth resistor R6 inputs the fifth bias voltage V BIAS5 , the other end is connected to the gate of the tenth NMOS transistor NM10; The third capacitor C3 is connected between the first input terminal INP of the driving module (1) and the gate of the fourth NMOS transistor NM4, the fourth capacitor C4 is connected between the gate of the fourth NMOS transistor NM4 and the gate of the fifth NMOS transistor NM5, the seventh capacitor C7 is connected between the second input terminal INN of the driving module (1) and the gate of the ninth NMOS transistor NM9, and the eighth capacitor C8 is connected between the gate of the ninth NMOS transistor NM9 and the gate of the tenth NMOS transistor NM10.

2. The high-speed sampling buffer circuit for a UWB system according to claim 1, wherein: The gate voltage bootstrap switch module (2) comprises a first gate voltage bootstrap unit, a first switch tube M1, a second gate voltage bootstrap unit and a second switch tube M2, wherein: The input end of the first gate voltage bootstrap unit is connected to the first output end X1 of the driving module (1) and inputs the first clock signal CLKP and the second clock signal CLKN respectively; the output end X3 of the first gate voltage bootstrap unit is connected to the gate of the first switch tube M1; and the drain of the first switch tube M1 is connected to the first output end X1 of the driving module (1); The input end of the second gate voltage bootstrap unit is connected to the second output end X2 of the driving module (1) and inputs the first clock signal CLKP and the second clock signal CLKN respectively; the output end X4 of the second gate voltage bootstrap unit is connected to the gate of the second switch tube M2; and the drain of the second switch tube M2 is connected to the second output end X2 of the driving module (1).

3. The high-speed sampling buffer circuit for a UWB system according to claim 2, wherein: The first gate voltage bootstrap switch unit includes a first PMOS transistor PM1, a second PMOS transistor PM2, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, a fifteenth NMOS transistor NM15, a sixteenth NMOS transistor NM16, a seventeenth NMOS transistor NM17, an eighteenth NMOS transistor NM18, a nineteenth NMOS transistor NM19, a twentieth NMOS transistor NM20, a ninth capacitor C9, a tenth capacitor C10, and an inverter I1, wherein: The gate of the first PMOS transistor PM1 and the gate of the eleventh NMOS transistor NM11 are both input with the first clock signal CLKP; the gate of the twelfth NMOS transistor NM12 is input with the second clock signal CLKN; The source of the first PMOS transistor PM1, the gate and drain of the thirteenth NMOS transistor NM13, the drain of the fourteenth NMOS transistor NM14, and the gate of the eighteenth NMOS transistor NM18 are all connected to the power supply terminal; the drain of the first PMOS transistor PM1 is simultaneously connected to the drain of the eleventh NMOS transistor NM11, the gate of the second PMOS transistor PM2, and the drain of the fifteenth NMOS transistor NM15; the ninth capacitor C9 is connected between the source of the thirteenth NMOS transistor NM13 and the gate of the twelfth NMOS transistor NM12; the tenth capacitor C10 is connected between the source of the fourteenth NMOS transistor NM14 and the drain of the twelfth NMOS transistor NM12; the source of the twelfth NMOS transistor NM12 is connected to the ground terminal; The source of the second PMOS transistor PM2 is connected to the source of the fourteenth NMOS transistor NM14, the drain of the second PMOS transistor PM2 is connected to the drain of the eighteenth NMOS transistor NM18, the source of the eighteenth NMOS transistor NM18 is connected to the drain of the nineteenth NMOS transistor NM19, the source of the nineteenth NMOS transistor NM19 is connected to the ground terminal, and the inverter I1 is connected between the gate of the eleventh NMOS transistor NM11 and the gate of the nineteenth NMOS transistor NM19; The source of the fifteenth NMOS transistor NM15 and the source of the sixteenth NMOS transistor NM16 are both connected to the drain of the twelfth NMOS transistor NM12, and the gate of the fifteenth NMOS transistor NM15 is respectively connected to the gate of the sixteenth NMOS transistor NM16, the gate of the seventeenth NMOS transistor NM17, and the drain of the eighteenth NMOS transistor NM18; The drain of the sixteenth NMOS transistor NM16 and the drain of the seventeenth NMOS transistor NM17 are simultaneously connected to the first output terminal X1 of the driving module (1); the substrate of the sixteenth NMOS transistor NM16 is connected to the source of the seventeenth NMOS transistor NM17 and the drain of the twentieth NMOS transistor NM20; the source of the twentieth NMOS transistor NM20 is connected to the ground terminal; the gate of the twentieth NMOS transistor NM20 inputs the substrate modulation clock signal Bulk_ctr; the gate of the seventeenth NMOS transistor NM17 is connected to the gate of the first switch transistor M1 as the output terminal X3 of the first gate voltage bootstrap switch unit.

4. The high-speed sampling buffer circuit for a UWB system according to claim 3, wherein: The first clock signal CLKP and the second clock signal CLKN are inverted signals, and the substrate modulation clock signal Bulk_ctr is a clock signal obtained by delaying the second clock signal CLKN by a predetermined amount.

5. The high-speed sampling buffer circuit for a UWB system according to claim 4, characterized in that: The sampling module (3) includes an eleventh capacitor C11, a twelfth capacitor C12, a twenty-first NMOS transistor NM21, a twenty-second NMOS transistor NM22, a twenty-third NMOS transistor NM23, a twenty-fourth NMOS transistor NM24, a twenty-fifth NMOS transistor NM25, a twenty-sixth NMOS transistor NM26 and an operational amplifier I2, wherein: The eleventh capacitor C11 is connected between the source of the first switch tube M1 and the positive input terminal of the operational amplifier I2, and the twelfth capacitor C12 is connected between the source of the second switch tube M2 and the negative input terminal of the operational amplifier I2; The gate of the twenty-first NMOS transistor NM21 and the gate of the twenty-second NMOS transistor NM22 are both input with the first clock signal CLKP, the drain of the twenty-first NMOS transistor NM21 and the drain of the twenty-second NMOS transistor NM22 are both input with the common mode voltage VCM, the source of the twenty-first NMOS transistor NM21 is connected to the positive input terminal of the operational amplifier I2, and the source of the twenty-second NMOS transistor NM22 is connected to the negative input terminal of the operational amplifier I2; The gates of the twenty-third NMOS transistor NM23 and the twenty-fourth NMOS transistor NM24 are both input with the second clock signal CLKN, the drain of the twenty-third NMOS transistor NM23 is connected to the source of the first switch transistor M1, the source of the twenty-third NMOS transistor NM23 is connected to the drain of the twenty-fifth NMOS transistor NM25, the drain of the twenty-fourth NMOS transistor NM24 is connected to the source of the second switch transistor M2, and the source of the twenty-fourth NMOS transistor NM24 is connected to the drain of the twenty-sixth NMOS transistor NM26; The gate of the twenty-fifth NMOS transistor NM25 and the gate of the twenty-sixth NMOS transistor NM26 are both input with the first clock signal CLKP, and the source of the twenty-fifth NMOS transistor NM25 and the source of the twenty-sixth NMOS transistor NM26 are both input with the common mode voltage VCM; The positive output terminal of the operational amplifier I2 serves as the first output terminal OUTP of the sampling module, and the negative output terminal of the operational amplifier I2 serves as the second output terminal OUTN of the sampling module.

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