Artificial Intelligence Hardware with Synaptic Reuse

Abstract

Synapse reuse allows multiple artificial neurons to be associated with a corresponding plurality of artificial synapses and variable gain amplifiers, thereby using less space and fewer components to implement and less power to operate than neurons with dedicated pathways for each input source. To reduce the likelihood of signal collisions and to allow independent control and interpretation of input spikes, the router is configured to connect an input source to each of the plurality of artificial neurons in conjunction with a gain configuration controller configured to set the gain on each of the plurality of variable gain amplifiers based on a time-sharing scheme and an identity of the input source transmitting the spike during a given time period.

Description

Background Art

[0001] Artificial neural networks (ANNs) are used in artificial intelligence applications to simulate the learning and recognition capabilities of the natural brain using hardware and software modeled after structures in the brain. In a neural network, various algorithms can be "taught" to perform various tasks through pattern recognition via a series of connected units or nodes called neurons. These neurons share inputs and outputs internally with other neurons in the neural network via connections called synapses. When a neural network is trained, various neurons are trained to provide different weights for different inputs received from various other neurons at these synapses.

[0002] Spiking Neural Networks (SNNs) are the third generation of ANNs that model the behavior of biological neural networks (i.e., animal brains) by transferring information between two neurons using timed action potentials, or "spikes," of information along a given synapse. SNNs are considered more biologically realistic for modeling artificial intelligence and are computationally more powerful than earlier generations of ANNs, while providing noise-robust, low-power, low-voltage implementations when integrated into hardware, such as very large-scale integration (VLSI) circuits.

[0003] When modeling SNNs in hardware, to achieve the rich nonlinear dynamics of SNNs compared to earlier generation ANNs, manufacturers are typically required to use significantly more transistors (compared to sigmoid neurons or perceptron-based ANNs), which can lead to an increase in the total memory required to express the SNN and a corresponding increase in the power consumption of such hardware implementations. Because the number of synapses typically exceeds the number of neurons in an SNN, an SNN may require a large number of hardware components (e.g., transistors) to implement, and a correspondingly large amount of space on a chip to pattern and place those hardware components. In addition to the greater space requirements to accommodate the components, as the complexity of the SNN scales, the additional components require more power to operate; resulting in bulky, difficult-to-manufacture, and very power-hungry circuits to implement the SNN. Summary of the Invention

[0004] According to one embodiment of the present invention, there is provided a circuit, comprising: a plurality of artificial neurons; a plurality of artificial synapses, wherein each of the plurality of artificial synapses is associated with a corresponding artificial neuron of the plurality of artificial neurons; a plurality of variable gain amplifiers, wherein each of the plurality of variable gain amplifiers is associated with a corresponding one of the plurality of artificial neurons; a router configured to connect at least one of a plurality of input sources to each of the plurality of artificial neurons via the corresponding variable gain amplifier and the corresponding artificial synapse; and a gain configuration controller.

[0005] The invention also provides a method for controlling the gain of a variable gain amplifier of the present invention and comprising: configuring the gain on each of the plurality of variable gain amplifiers based on a time division scheme and an identity of an input source transmitting a spike during a given time, thereby using less space, fewer components to implement, and less power to operate than a circuit including multiple dedicated paths between the input source and neurons defined therein.

[0006] In some aspects, in combination with any circuit described above or below, the number of input sources connected to a given artificial neuron in the plurality of artificial neurons is based on a time division scheme and peak transmission rates from the plurality of input sources to advantageously reduce the likelihood of signal collisions on a shared transmission path.

[0007] In some aspects, in combination with any circuit described above or below, the router and the gain configuration controller allow a first artificial neuron of the plurality of artificial neurons to receive a first spike from a first input source of the plurality of input sources at a first gain, and allow a second artificial neuron of the plurality of artificial neurons to receive the first spike from the first input source of the plurality of input sources at a second gain, wherein the second gain is set independently of the first gain to advantageously allow different neurons to interpret the effects of the input sources independently of each other.

[0008] In some aspects, in combination with any circuit described above or below, the router and the gain configuration controller allow a first artificial neuron of the plurality of artificial neurons to receive a first spike from a first input source of the plurality of input sources during a first time, and allow a second artificial neuron of the plurality of artificial neurons to receive a second spike from a second input source of the plurality of input sources at the first time, to advantageously allow independent signal reception by different neurons from different signal sources.

[0009] In some aspects, in combination with any circuit described above or below, a first input source of the plurality of input sources transmits spikes at a first transmission rate, and a second input source of the plurality of input sources transmits spikes at a second transmission rate different from the first transmission rate, to advantageously allow the circuit to accept inputs from independently operating input sources.

[0010] In some aspects, in combination with any circuit described above or below, the router includes a register configured to receive and store input spikes from the plurality of input sources and retransmit the input spikes from the register based on the time division scheme to advantageously reduce the likelihood of signal collisions on the shared transmission path.

[0011] In some aspects, in conjunction with any circuitry described above or below, a router and a gain configuration controller are controlled via a shared clock signal to advantageously align operation of the router and the gain configuration controller.

[0012] In some aspects, in combination with any circuitry described above or below, each of the plurality of variable gain amplifiers is positioned upstream of a corresponding one of the artificial synapses relative to the corresponding artificial neuron to advantageously control how the synapse interprets input based on the source from which the input is received.

[0013] In some aspects, in combination with any circuit described above or below, the plurality of artificial neurons, the plurality of artificial synapses, the plurality of variable gain amplifiers, the router, and the gain configuration controller are defined on a single integrated circuit to advantageously reduce signal delays and take advantage of the reduced space usage provided by the circuit.

[0014] According to one embodiment of the present invention, a method is provided, comprising: training neurons in a spiking neural network (SNN); assigning a time-division scheme for input sources to the neurons based on the training; assigning gains for the neurons in the time-division scheme based on the training; receiving input from the input source; setting a given gain for a given neuron based on the assigned gain and a given input source, wherein the given input is received from the given input source; and transmitting the given input to the given neuron according to the gain, thereby operating a circuit including neurons that use shared transmission paths for one or more input sources, which uses less space, fewer components to implement, and less power to operate, compared to a circuit in which a defined neuron includes several dedicated paths to input sources.

[0015] In some aspects, in combination with any of the methods described above or below, setting the given gain further comprises setting the given gain based on an identity of a given input source from which the given input is received, to advantageously allow neurons to apply different weights to signals based on the training when using a shared transmission path.

[0016] In some aspects, in combination with any of the methods described above or below, a first one of the neurons receives a first input from a first one of the input sources at a first gain, and a second one of the neurons receives the first input at a second gain different from the first gain, to advantageously allow different neurons to interpret the effects of the input sources independently of each other.

[0017] In some aspects, in combination with any of the methods described above or below, a first one of the neurons receives a first input from a first one of the input sources at a first time, and a second one of the neurons receives a second input from a second one of the input sources at a first time, to advantageously allow different neurons to independently receive signals from different signal sources.

[0018] In some aspects, in combination with any method described above or below, the method further comprises storing the received input in a register until a corresponding time in the time division scheme to advantageously utilize a time-based multiplexing mode for the shared transmission path.

[0019] In some aspects, in combination with any method described above or below, setting the given gain further comprises setting the given gain based on a corresponding time associated with a given input source from which the given input was received to advantageously utilize a time-based multiplexing pattern for the shared transmission path.

[0020] In some aspects, in combination with any of the methods described above or below, the method further includes: in response to receiving two input spikes from one of the input sources, discarding the earlier received input spike of the two input spikes from the one input source to advantageously reduce the impact or frequency of signal collisions on the shared transmission path.

[0021] In some aspects, in combination with any of the methods described above or below, the method further includes: in response to receiving at least two input spikes during a time share for transmission to one of the neurons, causing the at least two input spikes to collide, thereby advantageously requiring less control hardware software and instead relying on the robustness of the SNN to ignore or compensate for signal conflicts.

[0022] According to one embodiment of the present invention, a system is provided, comprising: a signal path including a variable gain amplifier; an artificial neuron connected to a plurality of input sources via the signal path; and a gain configuration controller configured to set a gain in the variable gain amplifier based on which of the plurality of input sources is transmitting an input spike to the artificial neuron, to advantageously allow the neuron to receive multiple inputs from multiple sources on a shared transmission path and thereby operate using less space, fewer components to implement, and less power than neurons using several dedicated transmission paths.

[0023] In some aspects, in combination with any system described above or below, the system further comprises: a router connected to the plurality of input sources and configured to connect one of the plurality of input sources at a time to the artificial neuron via the signal path to advantageously reduce the likelihood of signal collisions on the shared transmission path.

[0024] In some aspects, in combination with any system described above or below, the system further comprises: a router connecting the gain configuration controller and the plurality of input sources, wherein the router is configured to identify to the gain configuration controller which of the plurality of input sources is transmitting the input spike to advantageously control which input spikes are routed to which neurons and the gains at which those input spikes are received based on the identification of the neuron and the input source. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 An example neuron is shown receiving input from several input sources according to an embodiment of the present disclosure.

[0026] Figure 2 An example integrated circuit layout for managing several neurons to receive input from several input sources via a corresponding synapse for each neuron according to an embodiment of the present disclosure is shown.

[0027] Figures 3A-3E Different spike transmissions at different times are shown according to an embodiment of the present disclosure.

[0028] Figure 4A and 4B A circuit for an artificial neuron according to an embodiment of the present disclosure is shown.

[0029] Figure 5A and 5B A circuit for an artificial synapse according to an embodiment of the present disclosure is shown.

[0030] Figure 6 is a flow chart of a method for allocating variable gain for use when reusing a synapse according to an embodiment of the present disclosure.

[0031] Figure 7 is a flow chart of a method for applying variable gain for use when reusing a synapse according to an embodiment of the present disclosure.

[0032] Figure 8 is a flowchart of a method for manufacturing an integrated circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The present disclosure provides for implementing SNNs (spiking neural networks) in hardware by reusing synapses for multiple inputs into neurons with reduced memory usage and chip area. Instead of supplying each neuron with X synapses to receive up to X inputs, synaptic reuse allows neurons to use fewer than X synapses to receive X inputs. In various embodiments, neurons are each provided with a single input synapse to receive up to X inputs, which share the transmission path of the synapse using time division multiplexing (TDM) to regulate when and how the neuron receives spikes. Thus, the reduction in the number of synapses implemented in hardware can result in a reduction in space requirements, the number of components that need to be manufactured, and the power required to drive these components.

[0034] Figure 1 An example neuron 110 is shown receiving input from n input sources 120a-n (collectively, input sources 120) according to an embodiment of the present disclosure. Figure 4A and 4B Example circuitry for neuron 110 is discussed in greater detail, but other circuitry may be used in different embodiments.

[0035] The input source 120 can be a neuron 110 in an earlier layer of an ANN (artificial neural network), a direct feed of data into the ANN (e.g., when the neuron 110 is in the first layer of the ANN), or a feedback input from another neuron 110 in the same or later layer in the ANN. The neuron 110 receives various data from the input source 120, which are received as "spikes" in the SNN when the action potential of the associated input source 120 is met. In turn, these inputs are processed by the neuron 110 to determine when to "fire" an output spike, and can also be transmitted as an output of the SNN or as an input to another neuron 110 in the SNN.

[0036] In an SNN, a neuron 110 does not (necessarily) generate an output at every potential time interval. Instead, a neuron 110 determines whether to generate an output spike based on previously provided inputs. These inputs may decay over time, such that a sufficient number and / or strength of inputs need to be received within a given time period to overcome the action potential of the neuron 110 in order for the neuron 110 to generate an output spike for downstream consumption. Thus, the inputs received by a given neuron 110 (which may be received from input sources 120 including the other neurons 110) are received at different times depending on when the action potentials from the other neurons 110 are met.

[0037] Because neurons 110 can accept inputs sent from input sources 120 at different times, and input sources 120 do not (necessarily) send signals to neurons 110 at every potential time interval, neurons 110 can receive several inputs at different times on a shared path between input sources 120 and neurons 110. By using one (or at least a few) signal paths to provide inputs from input sources 120 to neurons 110, less hardware, less power, and less space on the integrated circuit defining neurons 110 can be used compared to an implementation that provides a dedicated signal path between each input source 120 and neuron 110. For example, on an integrated circuit having ten neurons 110 configured to receive inputs from ten input sources 120, one hundred signal paths would need to be implemented if dedicated signal paths were used, compared to only ten signal paths according to the present disclosure.

[0038] Figure 2 An example integrated circuit layout 200 is shown for managing up to m neurons 110a-m so that each of the m neurons 100a-m receives input from up to n input sources 120a-n via a corresponding synapse 210a-m (collectively, synapses 210) according to an embodiment of the present disclosure. Example circuits of synapses 210 will be described in detail in detail. Figure 5A and 5B As discussed in more detail, other circuits may be used in different embodiments.

[0039] In an SNN, not every neuron 110 in one layer must be connected to every neuron 110 in a subsequent layer. Instead, routers 220 are included to link specific input sources 120 with specific neurons 110. Included on each signal path leading from router 220 to neurons 110a-m is a corresponding variable gain amplifier 250a-m (collectively, amplifier 250) and synapse 210a-m. In various embodiments, amplifiers 250 and synapses 210 may be included on the corresponding signal paths in the order shown or in the reverse order (e.g., synapse 210 upstream or downstream of the associated amplifier 250). In various embodiments, routers 220 are configured to link or connect one or more of input sources 120a-n to one or more of neurons 110a-m based on a training phase of the SNN, which identifies which input sources 120 and neurons 110 are to be linked, which may be adjusted after any iteration of SNN training.

[0040] In some embodiments, based on the configuration of the SNN, not all neurons 110 receive inputs from all input sources 120, but the router 220 can connect any particular input source 120 to any particular neuron 110, and can connect one or more input sources 120 to a neuron 110 via a signal path. For example, at time t1, both the first input source 120a and the second input source 120b can transmit corresponding first and second spikes. In this example, the router 220 connects the first neuron 110a to the first input source 120a and the second neuron 110b to the second input source 120b, but does not connect the first neuron 110a to the second input source 120b or the second neuron 110b to the first input source 120a. Thus, the router 220 allows multiple neurons 110a to receive spikes from different input sources 120 without spike collisions. In contrast, if router 220 in the above example links first neuron 110a with first input source 120a and second input source 120b, the two spikes will collide, and first neuron 110a may lose its definition of where it receives input and how to process such input. However, when those other input sources 120 are not predicted (or allowed) to send spikes at the same time as each other or are otherwise separated in time to avoid collisions in the sent spikes, router 220 can connect different other input sources 120 to first neuron 110a. For example, when router 220 caches spikes for time-division retransmission, etc., router 220 can connect first neuron 110a with n different input sources 120a-n when each input source is constrained to send within a separate time slice of a time period.

[0041] In various embodiments, router 220 is driven according to clock signal 260 to change how various input sources 120 are connected to respective neurons 110 at respective times. For example, at time t0, router 220 may connect first input source 120a to first neuron 110a and second neuron 110b, but not to third neuron 110c. At a later time t1, router 220 may connect second input source 120b to first neuron 110a, second neuron 110b, and third neuron 110c. In such embodiments, router 220 ensures that, while several input sources 120 may be connected to each individual neuron 110 at different times, there is never more than one input source 120 connected to a given neuron 110 at any given time. Furthermore, router 220 may change which neurons 110 receive input at a given time. Thus, router 220 can establish or interrupt connections between different neurons 110 and input sources 120 according to a time-sharing scheme to prevent spikes generated from different input sources 120 outside of the allocated time windows from colliding on the shared signal path of a given neuron 110.

[0042] In some embodiments, the router 220 receives an input spike from each input source 120a-n and, after identifying the input source 120 from which the input spike was received, retransmits the input spike to all neurons 110a-m. Based on the identity of the input source 120, each neuron 110a-m receives the input spike according to an independently tuned gain for that input source 120 (including a gain that blocks or otherwise causes the input spike to fall below a reception threshold—effectively causing the neuron 110 to not receive the input spike). The independently tuned gains are based on weights learned by the neurons 110 for input spikes from the various input sources 120 during the training or learning phase of the SNN.

[0043] In various embodiments, router 220 includes an optional register 221 for receiving and storing spikes received from input sources 120 for transmission to neurons 110 at designated time shares in a time-sharing scheme. For example, in a time-sharing scheme using a one-second (s) period, register 221 can store any input received during that 1s period and transmit the stored spikes at designated time shares within that period. Register 221 can include a separate memory cell for each input source 120 to store spikes received from an individual input source 120 and subsequently retransmit them to the linked neuron 110. In some embodiments, register 221 is driven by a clock signal 260 to determine when to retransmit a spike stored in memory, at which time register 221 clears or resets the memory to zero based on whether the associated input source 120 sends another spike in the next time period, allowing the memory to contain (or not contain) the spike.

[0044] In addition, register 221 can help avoid conflicts on the signal paths from multiple input sources 120. For example, if two (or more) input spikes are received from separate input sources 120 at the same time t0, each spike can be held in a separate portion of register 221 associated with each input source 120 to be retransmitted to the destination neuron 110 at separate times (e.g., a first input spike at time t1, and a second input spike at time t2). In another example, if two (or more) input spikes are received from separate input sources 120 at the same time t0, one spike can be retransmitted or allowed to be transmitted to the destination neuron 110 at the reception time t0, while the other input spike is held in register 221 for retransmission at a later time. In some embodiments, register 221 can combine multiple signals received from one input source 120 during a time period to provide an amplified spike to the signal path. For example, if each spike is sent from an input source 120 with an amplitude of X, and one input source 120 sends two spikes in the time period, register 221 may hold and resend a spike with a value of 2X in the next time share associated with that input source 120 .

[0045] Gain configuration controller 230 controls what gain each variable gain amplifier 250a-m applies to the associated signal path at a given time based on a time division scheme.

[0046] In some embodiments, for example, the first amplifier 250a may be configured to operate at time t x Apply the gain of X at time t x+1 Apply the gain Y at time t x+2 A gain of Z is applied at time t and the pattern is repeated every three time divisions (e.g., at time t 2x At X, at time t 2x+1 At Y, at time t 2x+2 2 through m-th amplifiers 250-m apply various gains independently of the first amplifier 250a based on how the corresponding neurons 110 are trained in the SNN. Clock signal 260 drives gain configuration controller 230 to change the gains applied to amplifiers 250a-m at different times in the time-sharing scheme. In various embodiments where router 220 receives clock signal 260, router 220 and gain configuration controller 230 are driven by the same clock signal 260, thereby ensuring that the gains and input spikes are received and amplified synchronously with each other.

[0047] In some embodiments, the clock signal 260, and by extension the gain configuration controller 230 (and optionally, the router 220), controls the time division multiplexing of the signal paths between the router 220 and the neuron 110. Time division multiplexing takes advantage of the nature of SNNs, in which spikes are received infrequently from the input sources 120; the input sources 120 do not send a constant signal, but instead generate a spike once an action potential is satisfied and are otherwise inactive until the next action potential is satisfied. Thus, by managing the gains applied to a signal path according to the clock signal, the gain configuration controller 230 ensures that the neuron 110 can reuse a set of hardware defining synapses 210 shared with several input sources 120 and apply correspondingly learned weights for the input sources 120.

[0048] In some embodiments, router 220 generates a clock signal 260 based on the identity of the input source 120 from which the spike was received, which controls the gain configuration controller 230 (and, by extension, the amplifier 250) in an arbitrarily divided time-division multiplexing scheme. For example, instead of entering a new time-division every X milliseconds (ms), router 220 can signal gain configuration controller 230 to set the gain of amplifier 250 to the gain associated with the first input source 120a upon receiving an input spike from the first input source 120a. Similarly, in response to determining that the input spike is from the second input source 120b, gain configuration controller 230 sets the gain of the associated amplifier 250 to the gain associated with the second input source 120b, and so on. Thus, signal paths are multiplexed based on the received input spikes and configured to reuse synaptic hardware (e.g., amplifiers 250, synapses 210, and traces) at different times for different input sources 120.

[0049] Figures 3A-3E 10. A plurality of spike transmissions 300a-e at different times are shown in accordance with an embodiment of the present disclosure. The gain configuration controller 230 is trained as part of a learning phase of the SNN associated with the neuron 110 to uniquely set the gain of the amplifier 250 to reflect the trained weights carried by the synapse 210 for the corresponding neuron 110 for the associated input source 120.

[0050] For example, consider Figure 3A The first peak transmission 300a of the first amplifier 250a in Figure 3A, a first spike 310 is received from a first input source 120a at time t1, and a first amplifier 250a applies a first gain to the first spike 310 to output a first spike having an amplitude of 3. Similarly, the amplifier 250 amplifies a second spike 320 from a second input source 120b at time t2, a third spike 330 from a third input source 120c at time t3, and a fourth spike 340 from a fourth input source 120d at time t4 to reflect the associated gains of the input sources 120 from which the spikes were received. As shown, the amplifier 250 amplifies the second spike 320 to have an amplitude of 2, the third spike 330 to have an amplitude of 4, and the fourth spike 340 to have an amplitude of 3. The amplifier 250 can set the gain for the associated input source 120 based on the time associated with the input source 120 (e.g., as controlled by the gain configuration controller 230 driven by the clock signal) or based on the identity of the input source 120 (e.g., as determined at the router 220). As shown, the first amplifier 250a can apply several different weights, but when the learned weights are the same (e.g., the first spike 310 and the fourth spike 340), the same weights can be applied at different times / for different input sources 120.

[0051] Figure 3B A second peak transmission 300b of the second amplifier 250b is shown, which can be used in conjunction with Figure 3A The first spike transmission 300a shown in FIG is amplified for the same time t1-t4. Because the second amplifier 250b is associated with a different synapse 210 and neuron 110 than the first amplifier 250a (i.e., the second synapse 210b and the second neuron 110b rather than the first synapse 210a and the first neuron 110a), the second amplifier 250b is independently controlled to apply the learned gain of the second neuron 110b to the input spike. Therefore, although the spike is received from the same input source 120, the gain applied thereto may be different - as shown in FIG. Figure 3A and 3B However, the training of the SNN may impart the same gain to the same input source 120 at different amplifiers 250, such as, for example, applied to a signal from Figure 3A and 3B d, both resulting in an amplitude of 3 for the corresponding fourth peak 340.

[0052] Figure 3C A third peak transmission 300c of the third amplifier 250c is shown, which can be compared with Figure 3A1-t4. In various embodiments, the amplifier 250c can be tuned to a gain below the receive threshold 390 of the associated synapse 210 for one or more input sources 120. For example, the third amplifier 250c is trained to apply no gain or a gain below the receive threshold 390 of 1 for the first input source 120a at the first split at time t1. Thus, because the amplitude of the first spike 310 is less than the receive threshold 390, the third neuron 110c effectively does not receive the first spike 310.

[0053] Figure 3D A fourth peak transmission 300d of the fourth amplifier 250d is shown, which can be compared with Figure 3A The first spike transmission 300a is amplified at the same time t1-t4 as described above. In various embodiments, the router 220 can connect different input sources 120 (and different numbers) to different synapses 210 at the same time. For example, the fourth synapse 210d (corresponding to the fourth amplifier 250d and the fourth neuron 110d) is connected to the first input source 120a, the second input source 120b, and the third input source 120c, as shown in FIG. Figure 3A However, Figure 3A 1 is also connected to the fourth input source 120d, while the fourth synapse 210d is not. Similarly, the fourth synapse 210d is connected to the fifth input source 120e, while the first synapse 210a is not. Thus, at time t4, in the illustrated example, the first synapse 210a and the fourth synapse 210d receive inputs from different input sources 120.

[0054] Figure 3E The fifth peak transmission 300e of the fifth amplifier 250e is shown, which can be compared with Figure 3A The first peak transmission 300a shown in FIG is amplified at the same time t1-t4 but at a different rate. For example, similar to Figure 3A1 through 4 input sources 120a-d, but may also receive and amplify input spikes from a sixth input source 120f, which are received at a different rate or frequency than the first through fourth input spikes 310-340. As shown, the fifth amplifier 250e applies the same gain (for amplitude 2) to both the fifth input spike 350 and the sixth input spike 360 because both are received from the same input source 120 (i.e., the sixth input source 120f). The sixth input source 120f generates input spikes at a different rate than the other illustrated input sources 120, which the router 220 and gain configuration controller 230 process to apply associated gains at associated times and avoid conflicts on the single input signal path for the fifth neuron 110e.

[0055] Figure 4A A circuit for an artificial neuron 400a (collectively referred to as artificial neuron 400) according to an embodiment of the present disclosure is shown, and Figure 4B Another circuit for an artificial neuron 400b is shown, which can be used as neuron 110. As will be appreciated, in addition to Figure 4A and 4B Other circuit systems besides the artificial neuron 400 shown in FIG. 4 may also be used as the neuron 110 in various embodiments of the present disclosure; the artificial neuron 400 is provided as a non-limiting example of circuit components and configurations suitable for use as the neuron 110 .

[0056] exist Figure 4A , a first transistor 410a (collectively, transistor 410) and a second transistor 410b (both shown as p-channel) define a current mirror that receives feedback from a third transistor 410c connected to an inverter formed by a fourth transistor 410d and a fifth transistor 410e. When an activation potential is met, the fourth and fifth transistors 410d and 410e generate the output for the artificial neuron 400a. A sixth transistor 410f (which is fed with an enable voltage EN at its respective gates) is provided as a summing transistor to sum different input spikes from the respective synapses 210 over time. Furthermore, a seventh transistor 410g (which is fed with a leakage voltage VL at its respective gates) and a capacitor 420 are provided to "leak" the summed voltage from the input spikes over time, thereby causing the level of the summed input to decay over time. Leakage advantageously allows the neuron 110 to "forget" that an input was received, thereby allowing both the strength and / or frequency of the received input to be considered when determining whether to generate an output spike. Feedback advantageously allows the neuron 110 to "reset" once it has generated an output spike; requiring a new set of input spikes of sufficient strength and / or frequency to generate a subsequent output spike.

[0057] exist Figure 4B , artificial neuron 400b includes a current mirror circuit, a summing circuit, and an inverter circuit. The current mirror circuit includes a first transistor 410a and a second transistor 410b (both shown as p-channel) with gates connected to each other. The drains of the first transistor 410a and the second transistor 410b are connected to the input from the corresponding synapse 210. A third transistor 410c (shown as an n-channel) is provided as a pull-up transistor to add input spikes received from the corresponding synapse 210 over time. A fourth transistor 410d (shown as a p-channel) and a fifth transistor 410e (shown as an n-channel) form an inverter that generates an output for the artificial neuron 400a when the activation potential is met. Advantageously, the artificial neuron 400 b requires fewer circuit components (and correspondingly less manufacturing space and operating power) than a neuron 110 that includes leakage and feedback circuitry, and is time-independent; and therefore, is able to use input reception to generate output spikes over a longer period of time than a “leaky” neuron 110 that can “forget” inputs for a period of time.

[0058] Figure 5A FIG. 1 illustrates a circuit of an artificial synapse 500 a (collectively referred to as artificial synapse 500 ) according to an embodiment of the present disclosure, and Figure 5B Another circuit of an artificial synapse 500b is shown, which can be used as synapse 210. As will be appreciated, in addition to Figure 5A and 5B Other circuits besides the artificial synapse 500 shown in FIG. 5 may also be used as synapse 210 in different embodiments of the invention; artificial synapse 500 is provided as a non-limiting example of circuit components and configurations suitable for use as synapse 210 .

[0059] exist Figure 5AIn the embodiment, the first transistor 410a is connected at its gate to the input Vin from the router 220 or the corresponding amplifier 250, and the source of the first transistor 410a is grounded. The source of the second transistor 410b is connected to the drain of the first transistor 410a, and the weight input Vw is connected to the gate of the second transistor 410b, which can be changed based on the input source 120 for routing / scheduling spikes transmitted on the artificial synapse 500a. The respective sources of the third transistor 410c and the fourth transistor 410d are connected to the drain of the second transistor 410b. The gate of the third transistor 410c is connected to the threshold voltage Vthr input for the threshold level of the artificial synapse 500a, and the source of the third transistor 410c is connected to the rail carrying the collector voltage Vcc. The gate of the fourth transistor 410d is connected to the rail carrying the collector voltage Vcc via the capacitor 420. The fifth transistor 410 e is connected to a rail carrying a power supply voltage Vcc and to the drain of the fourth transistor 410 d via respective source and drain electrodes, and is connected at its gate to a voltage Vtau. In response to the action potential of the artificial synapse 500 a being satisfied by the input Vin, the output from the artificial synapse 500 a shares a node with the drains of the fourth and fifth transistors 410 d, e to carry the input to the corresponding neuron 110.

[0060] exist Figure 5B In the embodiment, the first transistor 410a is connected at its gate to the input Vin from the router 220 or the corresponding amplifier 250, and the source of the first transistor 410a is grounded. In addition, the body of the first transistor 410a is connected to the weight input Vw, which can be changed based on the input source 120 that routes / schedules to transmit spikes on the artificial synapse 500b in response to the action potential of the artificial synapse 500b being satisfied by the input Vin. The drains of the second transistor 410b and the third transistor 410c are connected to the rail connected to the corresponding neuron 110 as their input. The gates of the second transistor 410b and the third transistor 410b, 410c are connected to the complementary sign input (e.g., the sign (sign) and the inverse of the sign (sign-) respectively). The sources of the second transistor 410b and the third transistor 410c are both connected to the drain of the first transistor.

[0061] Figure 66 is a flow chart of a method 600 for assigning variable gains for use when reusing synapses 210 according to an embodiment of the present disclosure. The method 600 begins at block 610, where an operator trains an SNN comprising several neurons 110, each neuron 110 receiving input from a corresponding synapse 210 that is reused to carry input spikes from one or more input sources 120. The SNN may be trained over several iterations to determine what weight each neuron 110 assigns to each input source 120 according to different machine learning models.

[0062] At block 620 , the operator converts the weights assigned by the neuron 110 to the different input sources 120 during training into gains for use in the amplifier 250 on the signal path that includes the reusable synapse 210 .

[0063] At block 630 , the operator assigns a time-sharing scheme for input spikes from different input sources 120 to be carried on the reusable synapse 210 .

[0064] In some embodiments, the time-division scheme assigns actual times during which signals received from input sources 120 (e.g., at registers 221 of router 220) are retransmitted to neurons 110 and amplifiers 250 are set to corresponding gains assigned per block 620. In such embodiments, gain configuration controller 230 and router 220 are controlled by shared clock signal 260 to determine when to transmit spikes from a given input source 120 stored in register 221, and to what gains to set different amplifiers 250 based on the identity of the corresponding input source 120 and / or the times.

[0065] In some embodiments, the time-division scheme operates in response to the receipt of a spike and the identification of the input source 120 from which the spike was received. In such embodiments, the router 220 indicates to the gain configuration controller 230 the identification of the input source 120 from which the input spike was received, and the gain configuration controller 230 sets the gain of the amplifier 250 based on the identification. Thus, the gain of the amplifier 250 may remain so set until a subsequent input spike is received, at which time the router 220 identifies the new input source 120 to the gain configuration controller 230, which updates the gain applied by the amplifier 250. The identification of the input source 120 indicated by the router 220 to the gain configuration controller 230 may also be used to signal to the gain configuration controller 230 using the clock signal 260 when to change the gain to which the amplifier 250 is set.

[0066] At block 640, the operator allocates gains in the time-division scheme based on the training. In various embodiments, the gains to be applied to a particular amplifier 250 in response to receiving an input spike from a particular input source 120 are stored in a lookup table or other logic structure in the gain configuration controller 230. The method 600 may then end.

[0067] Figure 7 7 is a flow chart of a method 700 for applying variable gain for use when reusing synapses, according to an embodiment of the present disclosure. Method 700 begins at block 710, where a router 220 receives an input spike from a particular input source 120. Router 220 is connected to each input source 120 and each neuron 110, but may selectively link an input source 120 to a neuron 110 (i.e., not every neuron 110 is necessarily connected to every input source 120). In some embodiments, router 220 cycles through which input source 120 is connected to which neurons 110 based on a clock signal 260.

[0068] Optionally, at block 720 , if the router 220 includes a register 221 or other cache device to ensure that the input spike is forwarded to the destination neuron 110 at a predetermined time according to a time-sharing scheme, or to ensure that the input spike does not conflict with another input spike on a shared input path used by each individual neuron 110 , the router 220 may forward the input spike to the neuron 110 via the signal path without storing the input spike in the register 221 , and the method 700 may proceed to block 730 without executing block 720 .

[0069] At block 730, the gain configuration controller 230 adjusts the gain in the amplifier 250 based on the input source 120 that transmits the input spike to the neuron 110. In various embodiments, the gain configuration controller 230 sets the gain of the first amplifier 250a (corresponding to the first neuron 110a) independently of the gain of the second amplifier 250b (corresponding to the second neuron 110b) based on the learned weights that each neuron 110 assigns to input spikes from one input source 120. In some embodiments, the gain configuration controller 230 sets the gain of the first amplifier 250a (corresponding to the first neuron 110a) independently of the gain of the second amplifier 250b (corresponding to the second neuron 110b) based on the router 220 linking the first input source 120a to the first neuron 110a and the second input source 120b to the second neuron 110b and the associated weights assigned by those neurons 110 to the respective linked input sources. Thus, several input sources 120 may be linked to a given neuron 110 on a single path, with varying weights applied to the input spikes, thereby reducing the amount of hardware required to represent the neural network including the given neuron 110 .

[0070] At block 740, the input spike is transmitted to the destination neuron 110. The input spike travels from the router 220 to each destination neuron 110 on a shared signal path that includes the amplifier 250 and the synapse 210 corresponding to that one neuron 110. The amplifier 250 applies the learned gain to the input spike, and the synapse 210 determines whether to block the input spike or forward it onward to the corresponding neuron 110. The method 700 may then end.

[0071] Figure 8 FIG. 8 is a flow chart of a method 800 for manufacturing an integrated circuit according to an embodiment of the present disclosure. Figure 8 Although presented in a set order, those skilled in the art will appreciate that circuit fabrication is often performed in layers; components of the circuit are patterned and deposited from a base or substrate layer in an additive process that may form portions of different components on a given layer. The fabrication process may also include etching or ablation steps to remove material to define voids or areas where additional material is deposited in subsequent additive steps. Therefore, the elements of method 800 can be understood as being performed at least partially in parallel, with no single element being performed first / last.

[0072] At block 810, the manufacturer patterns the router 220. The router 220 connects one or more input sources 120 to one or more neurons 110 defined on the chip (e.g., per block 820). In various embodiments, the manufacturer patterns the input sources 120 like other neurons 110 defined on the chip, or may pattern traces for off-chip neurons 110 or data sources that are input to the router 220 and thus transmitted to the neurons 110 on the chip.

[0073] At block 820, the manufacturer patterns neurons 110. Neurons 110 include one or more transistors and may include resistors, capacitors, and inductors to represent the algorithm or logic operation of the SNN in a circuit, including a memory with the ability to decay or "forget" previous inputs over a period of time. Neurons 110 each include an output port on which an output spike is transmitted when the logic operation embodied by the neuron 110 is satisfied. In various embodiments, neurons 110 are linked as input sources 120 to other neurons 110 on the same or different chips.

[0074] At block 830, the manufacturer patterns a signal path between router 220 and neurons 110, the signal path including amplifiers 250 and synapses 210. Each neuron 110 is associated with a signal path including a corresponding amplifier 250 and a synapse 210. In various embodiments, synapse 210 is located upstream of amplifier 250 (i.e., further away from the corresponding neuron 110 than amplifier 250), while in other embodiments, synapse 210 is located downstream of amplifier 250 (i.e., closer to the corresponding neuron 110 than amplifier 250). Amplifier 250 can be controlled to provide a variable gain based on a control signal from gain configuration controller 230. Each synapse 210 includes at least one transistor and is configured with a threshold value to generate an output that is forwarded to the corresponding neuron 110 in response to an input spike received by synapse 210 satisfying the threshold value.

[0075] At block 840, the manufacturer patterns the gain configuration controller 230. In various embodiments, the gain configuration controller 230 is a logic control unit or microprocessor that is connected to one or more of the amplifiers 250 and the generator and router 220 for the clock signal 260. In various embodiments, the manufacturer encodes control logic into a memory (e.g., electrically erasable programmable read-only memory (EEPROM)) of the gain configuration controller 230 to control what gain each amplifier 250 is set to under what conditions (e.g., based on the time-sharing scheme and the training of the SNN).

[0076] The manufacturer may perform blocks 810-840 on a single chip or other very large scale integrated (VLSI) circuit, or may perform one or more of blocks 810-840 on separate chips and connect the separate chips together to form a circuit. For example, the manufacturer may manufacture the gain configuration controller 230 independently of the other components (or use a second manufacturer) and perform block 840 by integrating the gain configuration controller 230 with the other components.

[0077] The descriptions of various embodiments of the present invention have been presented for illustrative purposes, but are not intended to be exhaustive or to limit them to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0078] In the following, reference is made to the embodiments presented in the present disclosure. However, the scope of the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the following features and elements (whether or not involving different embodiments) may be used to implement and practice the conceived embodiments. In addition, although the embodiments disclosed herein may achieve advantages over other possible solutions or prior art, whether a particular advantage is achieved by a given embodiment is not a limitation on the scope of the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims. Likewise, reference to "the present invention" should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered to be elements or limitations of the appended claims unless expressly stated in the claims.

[0079] Various aspects of the present invention may be implemented as a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or a combination of hardware and software embodiments, which may be collectively referred to herein as "circuits," "modules," or "systems."

[0080] The present invention may be a system, method, and / or computer program product.The computer program product may include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to perform various aspects of the present invention.

[0081] Computer readable storage medium can be a tangible device that can keep and store the instruction used by the instruction execution device.Computer readable storage medium can be, for example but not limited to, electronic storage device, magnetic storage device, optical storage device, electromagnetic storage device, semiconductor storage device or any suitable combination of the above.The non-exhaustive list of more specific examples of computer readable storage medium includes following: portable computer disk, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanical encoding device such as punch card or the convex structure in the groove with the instruction recorded thereon and any suitable combination of the above.Computer readable storage medium as used herein should not be interpreted as temporary signal itself, such as radio wave or other free propagation electromagnetic wave, electromagnetic wave propagated by waveguide or other transmission medium (for example, light pulse passing through fiber optic cable) or electric signal emitted by line.

[0082] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0083] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data or source code or object code written in any combination of one or more programming languages, these programming languages include object-oriented programming languages (such as Smalltalk, C++ etc.) and conventional procedural programming languages (such as " C " programming languages or similar programming languages). The computer-readable program instructions can be performed completely on the user's computer, partly on the user's computer, performed as an independent software package, partly on the user's computer, partly on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer by any type of network (including local area network (LAN) or wide area network (WAN)), or can be connected to an external computer (for example, using an internet service provider through the internet). In certain embodiments, the electronic circuit comprising for example programmable logic circuit, field programmable gate array (FPGA) or programmable logic array (PLA) can make the electronic circuit personalized to perform computer-readable program instructions by utilizing the state information of computer-readable program instructions, so as to perform various aspects of the present invention.

[0084] Various aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0085] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine that causes the instructions, executed by the processor of the computer or other programmable data processing device, to create a device for implementing the functions / actions specified in the block or blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions can cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, a computer-readable storage medium having instructions stored therein includes an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in the block or blocks of the flowchart and / or block diagram.

[0086] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in the box or multiple boxes in the flowchart and / or block diagram.

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functions and operations of possible implementations of the systems, methods and computer program products according to different embodiments of the present invention. To this end, each box in the flowchart or block diagram may represent a module, segment or portion of an instruction, which includes one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions annotated in the box may not occur in the order annotated in the figure. For example, depending on the functions involved, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the opposite order. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs a specified function or action or performs a combination of dedicated hardware and computer instructions.

[0088] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope of the invention is determined by the claims that follow.

Claims

1. A circuit for a neural network, comprising: Multiple artificial neurons; a plurality of artificial synapses, wherein each of the plurality of artificial neurons is associated with a corresponding one of the plurality of artificial synapses; a plurality of variable gain amplifiers, wherein each of the plurality of variable gain amplifiers is associated with a corresponding one of the plurality of artificial neurons; a router configured to connect a plurality of input sources to at least a first artificial neuron of the plurality of artificial neurons via a first variable gain amplifier and a first artificial synapse; as well as a gain configuration controller configured to set a gain on at least the first variable gain amplifier based on a time division scheme, a clock signal, and an identification of an input source from which a given spike is received, comprising: causing a first spike and a first gain determined at least in part based on an identification of a first input source of the first spike to be synchronously received by the first variable gain amplifier to amplify the first spike, wherein the amplified first spike is received by the first artificial neuron via the first artificial synapse, causing a second spike and a second gain determined at least in part based on an identification of a second input source of the second spike to be synchronously received by the first variable gain amplifier to amplify the second spike, wherein the amplified second spike is received by the first artificial neuron via the first artificial synapse, The first gain and the second gain are determined at least in part based on trained weight values learned during a training phase for the first artificial neuron with respect to identities of the first input source and the second input source.

2. The circuit according to claim 1, wherein The number of input sources connected to a given artificial neuron of the plurality of artificial neurons is based on the time division scheme and spike transmission rates from the plurality of input sources.

3. The circuit according to claim 1, wherein The router and the gain configuration controller allow a first artificial neuron of the plurality of artificial neurons to receive a first spike from a first input source of the plurality of input sources at a first gain, and allow a second artificial neuron of the plurality of artificial neurons to receive the first spike from the first input source of the plurality of input sources at a third gain, wherein the third gain is set independently of the first gain.

4. The circuit according to claim 1, wherein The router and the gain configuration controller allow a first artificial neuron of the plurality of artificial neurons to receive a first spike from a first input source of the plurality of input sources during a first time, and allow a second artificial neuron of the plurality of artificial neurons to receive a third spike from a third input source of the plurality of input sources at the first time.

5. The circuit according to claim 1, wherein A first input source of the plurality of input sources transmits spikes at a first transmission rate, and a second input source of the plurality of input sources transmits spikes at a second transmission rate different from the first transmission rate.

6. The circuit according to claim 1, wherein The router includes a register configured to receive and store input spikes from the plurality of input sources and retransmit the input spikes from the register based on the time division scheme.

7. The circuit according to claim 1, wherein The router and the gain configuration controller are controlled via a shared clock signal.

8. The circuit according to claim 1, wherein Each of the plurality of variable gain amplifiers is positioned upstream of a corresponding one of the artificial synapses relative to the corresponding artificial neuron.

9. The circuit according to claim 1, wherein The plurality of artificial neurons, the plurality of artificial synapses, the plurality of variable gain amplifiers, the router, and the gain configuration controller are confined on a single integrated circuit.

10. A method for a neural network, comprising: Training neurons in spiking neural networks (SNNs); assigning a time-sharing scheme for input sources to the neurons based on the training; allocating gains for the neurons in the time-division scheme based on the training; receiving input from the input source; generating a clock signal based on an identity of a given input source; as well as Setting a gain of a first neuron based on the assigned gain, the clock signal, and the given input source from which the given input is received comprises: causing a first spike and a first gain determined at least in part based on an identification of a first input source of the first spike to be received synchronously to amplify the first spike, wherein the amplified first spike is received by the first neuron via a first synapse, causing a second spike and a second gain determined at least in part based on an identification of a second input source of the second spike to be synchronously received to amplify the second spike, wherein the amplified second spike is received by the first neuron via the first synapse, The first gain and the second gain are determined at least in part based on trained weight values learned for the first neuron relative to the identification of the first input source and the second input source during training of the neuron in the SNN.

11. The method according to claim 10, wherein: Setting the gain further includes: The gain is set based on an identification of the input source.

12. The method according to claim 10, wherein: A first one of the neurons receives a first spike from a first one of the input sources at a first gain, and a second one of the neurons receives the first spike at a third gain different from the first gain.

13. The method according to claim 10, wherein: A first one of the neurons receives a first spike from a first one of the input sources at a first time, and a second one of the neurons receives a third spike from a third one of the input sources at the first time.

14. The method according to claim 10, further comprising: The received input is stored in a register until a corresponding time in the time-sharing scheme.

15. The method according to claim 14, wherein Setting the gain further comprises: The gain is set based on the corresponding time associated with a given input source from which the given input is received.

16. The method according to claim 14, further comprising: In response to receiving two input spikes from one of the input sources, an earlier received input spike of the two input spikes from the one input source is discarded.

17. The method according to claim 14, further comprising: In response to receiving at least two input spikes during a time share for transmission to one of the neurons, the at least two input spikes are collided.

18. A system for a neural network, comprising: a signal path comprising a variable gain amplifier; an artificial neuron connected to a plurality of input sources via the signal path; as well as a gain configuration controller configured to set a gain in a variable gain amplifier based on an identification of one of the plurality of input sources from which the artificial neuron receives a given input spike at a given time and a clock signal generated by a router, comprising: causing a first spike and a first gain determined at least in part based on an identification of a first input source of the first spike to be synchronously received to amplify the first spike, wherein the amplified first spike is received by the artificial neuron via the signal path, causing a second spike and a second gain determined at least in part based on an identification of a second input source of the second spike to be synchronously received to amplify the second spike, wherein the amplified second spike is received by the artificial neuron via the signal path, The first gain and the second gain are determined at least in part based on trained weight values learned during a training phase for the artificial neuron with respect to identities of the first input source and the second input source.

19. The system of claim 18, further comprising: A router is connected to the plurality of input sources and configured to connect one of the plurality of input sources at a time to the artificial neuron via the signal path and to generate the clock signal based on an identity of the input source.

20. The system of claim 18, further comprising: A router connects the gain configuration controller and the plurality of input sources, wherein the router is configured to identify to the gain configuration controller which of the plurality of input sources is transmitting the input spike.

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