Semiconductor device structure and method of fabricating the same

Abstract

The application discloses a semiconductor device structure and a preparation method thereof. The semiconductor device structure comprises a semiconductor substrate, a plurality of active regions and isolation structures in the semiconductor substrate, the active regions and the isolation structures are alternately and spacedly arranged along a first direction, the active regions extend along a second direction, and the first direction is perpendicular to the second direction; a gate structure at least on the active regions; and a dummy structure at least on the isolation structures, and there is a spacing between the gate structure and the dummy structure in the second direction; the active regions are further formed with source and drain doped regions on both sides of the gate structure, and a projection of the dummy structure on the isolation structures is between the source doped regions and / or a projection of the dummy structure on the isolation structures is between the drain doped regions.

Description

[0001] Cross Reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202011101325.0, filed on October 15, 2020, entitled “Semiconductor Device Structure and Method of Manufacturing the Same”, the entire contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure belongs to the technical field of integrated circuit manufacturing, and particularly relates to a semiconductor device structure and a method of manufacturing the same. BACKGROUND

[0004] With the development of memory technology, the storage density of planar storage cells approaches the upper limit, and three-dimensional flash memory (3D NAND) technology emerges as the times require. The 3D NAND memory architecture can solve the density limitation in the planar storage cell. At present, a general 3D NAND structure includes a memory array and a peripheral device for controlling the signals of the memory array, and the peripheral device includes a bit line driver, a page buffer, etc. However, with the increase of the storage cell density in the 3D NAND architecture, the size of the peripheral device components needs to be relatively small, for example, the distance between the bit line driver transistors gradually decreases, resulting in a high punch-through risk (NUH / NUH punch-through risk), which is difficult to meet the required performance of the device.

[0005] Therefore, it is necessary to provide a semiconductor device structure and a method of manufacturing the same to solve the above problems in the prior art. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the present disclosure provides a semiconductor device structure, which comprises:

[0007] a semiconductor substrate;

[0008] a plurality of active regions and isolation structures located in the semiconductor substrate, the active regions and the isolation structures are alternately and spacedly arranged along a first direction, the active regions extend along a second direction, and the first direction is perpendicular to the second direction;

[0009] a gate structure located at least on the active regions; and

[0010] a dummy structure located at least on the isolation structure between adjacent active regions, and the gate structure and the dummy structure have a spacing in the second direction;

[0011] A source doped region and a drain doped region are formed in the active region on both sides of the gate structure, and a projection of the dummy structure on the isolation structure is between the source doped regions and / or a projection of the dummy structure on the isolation structure is between the drain doped regions.

[0012] In some embodiments, the gate structure and the dummy structure are made of the same material, and the gate structure and the dummy structure have the same height.

[0013] In some embodiments, the gate structure includes a plurality of gate units corresponding to the active regions, the gate units span the corresponding active regions along the first direction, and each gate unit is electrically connected based on the same metal layer.

[0014] In some embodiments, there is a spacing between adjacent gate units, and a projection of the dummy structure corresponding to the active regions between the two adjacent gate units and the active regions in the first direction overlaps.

[0015] In some embodiments, the gate structure includes a strip gate, and the strip gate spans each active region along the first direction.

[0016] In some embodiments, a lightly doped drain region is formed in the active region on both sides of the gate structure.

[0017] In some embodiments, the semiconductor device structure is a bit line driver.

[0018] In some embodiments, in the first direction, the dummy structure extends above the source doped region to form an overlapping region, or the dummy structure extends above the drain doped region to form the overlapping region.

[0019] In some embodiments, in the first direction, the size of the overlapping region is between 1 / 5 and 1 / 3 of the size of the corresponding source doped region or drain doped region.

[0020] The present application also provides a preparation method of a semiconductor device structure, the preparation method including the following steps:

[0021] providing a semiconductor substrate;

[0022] forming a plurality of active regions and isolation structures in the semiconductor substrate, the active regions and the isolation structures are alternately and spacedly arranged along a first direction, the active regions extend along a second direction, and the first direction is perpendicular to the second direction;

[0023] forming a gate structure and dummy structures on the semiconductor substrate, wherein the gate structure is formed on at least the active regions, the dummy structures are formed on at least the isolation structures between adjacent active regions, and there is a spacing between the gate structure and the dummy structures in the second direction;

[0024] performing ion implantation on the active regions to form source and drain doped regions on both sides of the gate structure, a projection of the dummy structures on the isolation structures is between the source doped regions, and / or a projection of the dummy structures on the isolation structures is between the drain doped regions.

[0025] In some embodiments, the gate structure and the dummy structures are formed simultaneously based on a same process.

[0026] In some embodiments, the gate structure comprises a plurality of gate units corresponding to the active regions one by one, the gate units span the corresponding active regions in the first direction, and each of the gate units is electrically connected based on a same metal layer; or, the gate structure comprises a strip gate spanning each of the active regions in the first direction.

[0027] In some embodiments, there is a spacing between adjacent gate units, and a projection of the gate units corresponding to adjacent active regions and the dummy structures between the active regions in the first direction has an overlap.

[0028] In some embodiments, after forming the source and drain doped regions, the method further comprises the step of: performing ion implantation on the active regions on both sides of the gate structure to form a lightly doped drain region.

[0029] In some embodiments, in the first direction, the dummy structures extend above the source doped regions to form an overlap region, or the dummy structures extend above the drain doped regions to form the overlap region.

[0030] In some embodiments, in the first direction, a size of the overlap region is between 1 / 5 and 1 / 3 of a size of the corresponding source or drain doped region. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A top view showing an example of a semiconductor device structure according to the present application.

[0032] Figure 2 A top view showing another example of a semiconductor device structure according to the present application.

[0033] Figure 3 A top view showing yet another example of a semiconductor device structure according to the present application.

[0034] Figure 4 The diagram shows a top view of yet another example of the semiconductor device structure of the present invention.

[0035] Figure 5 The diagram shows the process flow for fabricating the semiconductor device structure of this invention.

[0036] Figure 6 The diagram shows a schematic of a semiconductor substrate provided in an example of the fabrication of a semiconductor device structure according to the present invention.

[0037] Figure 7 The diagram shown is a schematic representation of the formation of an active region and an isolation structure in an example of the fabrication of a semiconductor device structure according to the present invention.

[0038] Figure 8 The image shown is a top view illustrating the formation of a gate structure and a virtual structure in an example of semiconductor device structure fabrication according to the present invention.

[0039] Figure 9 Displayed as Figure 8 The cross-sectional view of the structure shown in the AA' direction.

[0040] Figure 10 Displayed as Figure 8 The cross-sectional view of the structure shown in the BB' direction.

[0041] Figure 11 The diagram shows an example of the formation of source and drain doped regions in the fabrication of a semiconductor device structure according to the present invention.

[0042] Figure 12 The graph shows the impact of the virtual structure formed by the present invention on the breakdown voltage of the bit line driver compared to the scheme without forming a virtual structure.

[0043] Component designation explanation

[0044] 100 Semiconductor Substrate

[0045] 100a Tunnel

[0046] 101 Active Zone

[0047] 102 Isolation Structure

[0048] 103 gate structure

[0049] 104 Virtual Structure

[0050] 105 source doped region

[0051] 106 Drain doped region

[0052] 107 gate units

[0053] 108 metal layer

[0054] S1-S3 steps DETAILED DESCRIPTION

[0055] Following are examples of the embodiments of the present application. Other advantages and effects of the present application will be more clearly understood from the following description taken in conjunction with the accompanying drawings. The present application can also be embodied in different embodiments or applied to different applications, and the details of the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0056] In describing the embodiments of the present application, the cross-sectional view of the device structure is partially enlarged without the general scale for the convenience of explanation, and the schematic view is only an example which should not limit the scope of protection of the present application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual fabrication.

[0057] For the convenience of description, spatial relationship words such as "under", "below", "lower", "underneath", "above", "upper" and the like can be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatial relationship words are intended to include other orientations of the device in use or operation in addition to the orientations depicted in the drawings. In addition, when a layer is referred to as "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present. In addition, "between" is used in the present application to include both end point values.

[0058] In the context of the present application, the structure in which the first feature is "on" the second feature can include the embodiment in which the first and second features are formed in direct contact, and can also include the embodiment in which another feature is formed between the first and second features, so that the first and second features can not be in direct contact.

[0059] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component can be a random change, and the component layout pattern can be more complex.

[0060] As shown in FIG. 1, the present application provides a semiconductor device structure, which comprises a semiconductor substrate 100, a plurality of active regions 101 and isolation structures 102 located in the semiconductor substrate 100, a gate structure 103 located at least on the active regions 101, and a dummy structure 104 located at least on the isolation structures 102 between adjacent active regions. Figures 1 to 4 As shown in FIG. 1, the present application provides a semiconductor device structure, which comprises a semiconductor substrate 100, a plurality of active regions 101 and isolation structures 102 located in the semiconductor substrate 100, a gate structure 103 located at least on the active regions 101, and a dummy structure 104 located at least on the isolation structures 102 between adjacent active regions.

[0061] The semiconductor substrate 100 can be used to fabricate a substrate of a 3D NAND memory peripheral device, such as a CMOS wafer substrate. The semiconductor substrate 100 can be a single layer of material or a stack of layers of material. The material of the semiconductor substrate can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, glass, a III-V compound, any other suitable material, or any combination thereof. In some embodiments, the semiconductor substrate 100 can be double polished prior to fabrication of the peripheral device. Both are polished and processed to provide a smooth surface for high quality semiconductor devices. The peripheral device can include any suitable semiconductor device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a diode, a resistor, a capacitor, an inductor, etc. In semiconductor devices, p-type MOSFETs and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs. Additionally, the peripheral device can be a p-channel MOSFET or an n-channel MOSFET. In an example, ion implantation can also be performed in the semiconductor substrate 100 to form a well region 100a, which is formed by n-type or p-type doping in an active device region.

[0062] The semiconductor device further includes a plurality of active regions 101 and isolation structures 102. A first direction and a second direction perpendicular to each other are defined in a plane of the semiconductor substrate 100, corresponding to the y direction and the x direction in the figure, respectively. The active regions 101 and the isolation structures 102 are alternately and spacedly arranged along the first direction, and the active regions 101 extend along the second direction. The number of the active regions 101 and the isolation structures 102 can be set according to actual requirements.

[0063] With the continuous reduction of device size, the distance between adjacent active regions is gradually reduced. For example, in the first direction, for the bit line driver of the present application, i.e. the semiconductor device structure as a bit line driver, wherein the 3D NAND structure includes a memory array and peripheral devices for controlling memory array signals, the peripheral devices include a bit line driver. In the current 3D-NAND device design, the bit line driver (BL driver device) is a high-voltage hybrid NMOS (UHVN hybrid NMOS) array structure. During the Cell Erase and Program processes, the adjacent tubes of the bit line driver need to withstand a pressure difference of ~2.4V, while the spacing of the adjacent tubes (as shown by the dashed line in the figure) is only 0.386um, so the bit line memory two-tube punch-through risk (NUH / NUH punch-through risk) is high.

[0064] Further, a gate structure 103 and a dummy structure 104 are also prepared on the semiconductor device structure of the present application. The gate structure 103 is arranged on the active region 101 as the gate of the device.

[0065] The semiconductor device structure includes a dummy structure 104, and the gate structure 103 and the dummy structure 104 have a spacing therebetween, i.e. they are not in contact. In the present application, the dummy structure 104 is arranged on the isolation structure 102. The dummy structure 104 arranged on the isolation structure 102 can block part of the LDD ion implantation and the source-drain implantation (NP implantation), reduce the implantation of the underlying implantation ions, thereby enhancing the isolation ability of the isolation structure, improving the breakdown voltage between adjacent tubes, and effectively suppressing the breakdown of adjacent tubes. In addition, in the present application, the dummy structure 104 is arranged on the isolation structure 102, which has a spacing with the gate structure 103 in the plane of the semiconductor substrate 100, without the need to increase the device area.

[0066] As an example, the gate structure 103 and the virtual structure 104 are made of the same material, specifically polysilicon. The gate structure 103 and the virtual structure 104 have the same height. That is, in this example, the virtual structure 104 is configured to have the same structure as the gate structure 103, with a distance s between them between 0.5 μm and 1 μm, such as 0.6 μm or 0.8 μm. For example, in one example, the virtual structure 104 is located between the drain doped regions of adjacent active regions, and the distance between the virtual structure 104 and the gate structure 103 is 0.7 μm. In another example, the virtual structure has the same length as the adjacent heavily doped region (the drain doped region), meaning that the virtual structure has the same length as the adjacent heavily doped region along the second direction. This allows the virtual structure 104 and the gate structure 103 to be fabricated simultaneously using the same process, and the introduction of the virtual structure 104 does not require any changes to the process conditions or steps, making it simple and feasible.

[0067] As an example, such as Figure 4 As shown, the gate structure includes a plurality of gate units 107 corresponding one-to-one with the active region 101. Each gate unit 107 spans the corresponding active region 101 along the first direction, and all gate units 107 are electrically connected based on the same metal layer 108. In this example, designing multiple open gate units 107 reduces the area between the active regions covered by the gate structure, thereby increasing the threshold voltage of the field-effect transistor and improving the breakdown voltage, thus enhancing the performance of the memory cell even with smaller transistor spacing. Furthermore, the open gate units 107 further reduce the risk of punch-through between adjacent devices. Thus, the punch-through problem between adjacent transistors in the bit line driver proposed in this invention can be solved by the combined action of the gate units 107 and the virtual structure 104. Additionally, in this example, the electrical connection between the gate units 107 via the metal layer reduces series resistance and increases the transmission current of the bit line driver.

[0068] As an example, there is a gap between adjacent gate units 107, and the projections of the two gate units 107 corresponding to two adjacent active regions 101 and the virtual structure 104 corresponding to the active regions 101 overlap in the first direction. That is, the two adjacent gate units 107 and the virtual structure 104 between them are all projected on the y-axis, and there is no gap between the projections of the three components, forming a continuous line.

[0069] As an example, see Figures 1 to 3As shown, the gate structure includes a strip gate which extends across each of the active regions in the first direction. In this example, a single strip gate is used to provide a common gate connection for each of the active regions.

[0070] As an example, source and drain doped regions 105 and 106 are also formed in the active regions 101 on both sides of the gate structure 103, and the dummy structure 104 is formed between the source doped regions 105 or between the drain doped regions 106 of adjacent active regions 101. The source and drain doped regions 105 and 106 are arranged in a second direction and act as the source and drain of the device. The dummy structure 104 can be provided only at a position corresponding to the drain doped region 106 of an adjacent active region 101, as shown in Figure 1 As shown, the dummy structure 104 can also be provided between the source doped regions 105 and between the drain doped regions 106 of adjacent active regions 101, as shown in Figure 2 As shown, the dummy structure 104 can also be provided between the source doped regions 105 and between the drain doped regions 106 of adjacent active regions 101, as shown in The spacing between the dummy structure and the gate structure in the drain doped region 106 is s, and the spacing between the dummy structure and the gate structure in the source doped region 105 is t. In one example, because the drain is to be applied with a voltage, the punchthrough problem needs to be considered, and because the source is not to be applied with a voltage, the punchthrough problem does not need to be considered. The length of s is set to 0.5-1 μm, and can be 0.6 μm or 0.8 μm. The length of t can be designed flexibly according to actual requirements.

[0071] In a further example, the dummy structure 104 also extends over the source doped region 105 or the drain doped region 106 of adjacent active regions in the first direction to form an overlapping region. As shown in Figure 3As shown, the dummy structure 104 is located between the drain doped regions 106 of adjacent active regions, the dummy structure 104 crosses the isolation structure 102 below and further extends to both sides, in an example, the width of the overlap region of the drain doped region 106 in the first direction is d, in an example, the distance of the extension to both sides of the drain doped region is equal, the length d is 0.05-0.2 μm, for example, it can be 0.08 μm, 0.1 μm, 0.12 μm, 0.15 μm, 0.18 μm. The dummy structure is equivalent to blocking the ion implantation of LDD, equivalent to reducing the LDD concentration, reducing the risk of punch-through. In an example, the dose of LDD doping is between 5e10 n / cm2-5e13 n / cm2, for example, it can be selected as 5e12 n / cm2; the dose of NP doping is between 1e11 n / cm2-5e15 n / cm2, for example, it can be selected as 1e13 n / cm2, 5e11 n / cm2, 5e15 n / cm2. Optionally, in the first direction, the size of the overlap region is between 1 / 5 and 1 / 3 of the size of the source doped region or the drain doped region. Wherein, the isolation structure on which the dummy structure 104 is located between the drain doped regions is beneficial to the blocking of subsequent ion implantation (such as LDD doping ion or source-drain NP doping ion), and is beneficial to the blocking of part of the doping ions into the structures such as isolation structure, source doped region and drain doped region, so as to effectively realize the isolation between adjacent transistors, improve the punch BV, and reduce the punch-through risk. Further, forming the overlap region can be beneficial to improving the ion blocking effect, widening the width of the isolation structure in the direction, and being beneficial to improving the isolation between transistors, without affecting the channel of the device and without affecting the performance of the source-drain region of the device. And the above scheme of the present application does not need to increase the size of the isolation structure (STI space), so as not to increase the chip size, and does not increase the unit cost of the device. Without reducing the dose of LDD doping region (LDD dose), the BVDs of the device will not be affected by reducing the LDD doping, and the risk of device break down will not be increased. Without increasing the FLD dose, the ion implantation under the isolation region is used to increase the substrate concentration, reduce the depletion, and reduce the punch-through risk of the device. The body effect of the device will not be affected, and the voltage transmission efficiency will not be reduced. Without the above-mentioned sacrifice, the punch-through risk of the device can be reduced. In addition, as Figure 12 As shown, the voltage-current curve diagram of an example of forming a dummy structure and not forming a dummy structure is shown, and the TCAD simulation data can be seen that the punch BV is improved by 0.8 V.

[0072] As an example, the active region also contains LDD-doped regions located on both sides of the gate structure. In this case, the peripheral device (e.g., HVNMOS) can have an LDD-doped region between the source / drain and the gate structure to reduce the electric field when a high voltage is applied to the drain. It should be noted that the LDD-doped region is the lightly doped drain region well-known in the art.

[0073] In addition, such as Figures 5 to 11 As shown, and see also Figures 1 to 4 The present invention also provides a method for fabricating a semiconductor device structure. Preferably, the semiconductor device structure in the above-described embodiment of the present invention is fabricated using the method described herein. Of course, other methods can also be used. The fabrication method includes the following steps:

[0074] First, such as Figure 5 S1 and Figure 6 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be any semiconductor substrate described in the semiconductor device structure of this embodiment, and will not be described in detail here.

[0075] Next, as Figure 5 S2 and Figure 7 As shown, a plurality of active regions 101 and isolation structures 102 are formed in the semiconductor substrate 100. The active regions 101 and the isolation structures 102 are arranged alternately along a first direction, and the active regions 101 extend along a second direction, wherein the first direction is perpendicular to the second direction. The active regions and the isolation structures can refer to any semiconductor substrate described in the semiconductor device structure in this embodiment, and will not be described again here.

[0076] Additionally, in an example, ion implantation is performed in the semiconductor substrate 100 prior to forming the active region 101 and the isolation structure 102, forming a well region 100a. The active region 101 and the isolation structure 102 are formed in the well region 100a. The well region 100a of a peripheral device (e.g., a bit line driver transistor) can include a p-type doped well for n-channel MOSFETs and an n-type doped well for p-channel MOSFETs, and are referred to as a p-well and an n-well, respectively. The dopant profile and concentration of the well affect the device characteristics of the peripheral device. For MOSFET devices with low threshold voltage (Vt), the well can be doped at a lower concentration, and a low voltage p-well or a low voltage n-well can be formed. For MOSFETs with high Vt, the well can be doped at a higher concentration, and a high voltage p-well or a high voltage n-well can be formed. In some embodiments, to provide electrical isolation from the p-type substrate, a deep n-well can be formed under the high voltage p-well for n-channel MOSFETs with high Vt (also referred to as high voltage nMOSFETs or HV NMOS). The formation of the n-well can include any suitable n-type dopant, such as phosphorus, arsenic, antimony, etc., and / or any combination thereof. The formation of the p-well can include any suitable p-type dopant, such as boron. The incorporation of the dopant can be achieved by ion implantation followed by an activation anneal, or by in-situ doping during epitaxy for the active device region.

[0077] As an example, a method of forming an isolation structure 102 is provided, around which a well region or substrate material forms an active region. The isolation structure 102, which can be an STI, can be formed by patterning the substrate using lithography and etching, filling an insulating material, and polishing the insulating material to form a planar surface on the semiconductor substrate 100. The insulating material for the STI can include silicon oxide, silicon oxynitride, TEOS, low temperature oxide (LTO), high temperature oxide (HTO), silicon nitride, etc. The insulating material of the STI can be deposited using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) chemical vapor deposition, rapid thermal chemical vapor deposition (RTCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), sputtering, thermal oxidation or nitridation, or combinations thereof. The formation of the STI can also include a high temperature anneal step to densify the deposited insulating material to improve electrical isolation. Of course, other STI structures can be employed.

[0078] Next, as shown in FIG. 1C, the isolation structure 102 is formed in the semiconductor substrate 100. The isolation structure 102 can be formed by any suitable technique, such as lithography and etching, or by any other suitable technique. The isolation structure 102 can be formed by any suitable material, such as silicon oxide, silicon oxynitride, TEOS, LTO, HTO, silicon nitride, etc. The isolation structure 102 can be formed by any suitable technique, such as CVD, PVD, PECVD, LPCVD, HDP, RTCVD, MOCVD, ALD, sputtering, thermal oxidation or nitridation, or combinations thereof. The isolation structure 102 can be formed by any suitable thickness, such as 1000 A to 5000 A, or any other suitable thickness. The isolation structure 102 can be formed by any suitable shape, such as a rectangular shape, a square shape, a circular shape, an oval shape, a polygonal shape, or any other suitable shape. The isolation structure 102 can be formed by any suitable depth, such as 1000 A to 5000 A, or any other suitable depth. The isolation structure 102 can be formed by any suitable material and any suitable technique, such as a trench isolation structure, a local oxidation of silicon (LOCOS) structure, or any other suitable isolation structure. Figure 5 Figures 8 to 10 ​As shown, a gate structure 103 and a dummy structure 104 are prepared on the semiconductor substrate 100, wherein the gate structure 103 is formed at least on the active region 101, the dummy structure 104 is formed at least on the isolation structure 102 between adjacent active regions 101, and the gate structure 103 and the dummy structure 104 have a spacing in the second direction. The structural features of the gate structure 103 and the dummy structure 104 can refer to the description of the semiconductor device structure part in the present embodiment, which will not be repeated here.

[0079] As an example, the gate structure 103 and the dummy structure 104 are prepared simultaneously based on the same process. The dummy structure 104 and the gate structure 103 are prepared simultaneously based on the same process, and the introduction of the dummy structure 104 does not need to change any process conditions and steps, and the process is simple and feasible.

[0080] As an example, the gate structure 103 includes a plurality of gate units 107 corresponding to the active regions 101 one by one, the gate units 107 cross the corresponding active regions 101 in the first direction, and each gate unit 107 is electrically connected based on the same metal layer 108.

[0081] As an example, the gate structure 103 includes a strip-shaped gate, which crosses each active region 101 in the first direction.

[0082] As an example, in the first direction, there is a spacing between adjacent gate units 107, and the projection of the dummy structure 104 between the gate units 107 corresponding to adjacent active regions 101 and the active regions 101 in the first direction has an overlap.

[0083] In an example, a way of forming the gate structure 103 and the dummy structure 104 is provided, and the gate structure 103 and the dummy structure 104 can be formed simultaneously without increasing additional process steps. A mask material layer can be first formed on the semiconductor substrate 100, and then patterned to obtain a pattern window corresponding to the gate structure and the dummy structure, and then a gate material is formed in the window to obtain the gate structure and the dummy structure. For example, the gate material layer formed in the window can include a gate dielectric and a gate conductor layer formed on the gate dielectric.

[0084] In one example, the gate dielectric can be made of silicon oxide, silicon nitride, silicon oxynitride, and / or a high-k dielectric film (e.g., hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, magnesium oxide, or lanthanum oxide film and / or combinations thereof). The gate dielectric can be provided by any suitable method, such as CVD, PVD, PECVD, LPCVD, RTCVD, sputtering, MOCVD, ALD, thermal oxidation or nitridation, or combinations thereof. In another example, the gate conductor can be made of a metal or a metal alloy, such as tungsten, cobalt, nickel, copper, or aluminum and / or combinations thereof. In some embodiments, the gate conductor can also include a conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), or the like. The gate conductor can be formed by any suitable deposition method, such as sputtering, thermal evaporation, e-beam evaporation, ALD, PVD, and / or combinations thereof. In other examples, the gate conductor can also include a polycrystalline semiconductor, such as polysilicon, polygermanium, polygermanium-silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material can be combined with any suitable type of dopant, such as boron, phosphorus, or arsenic, or the like. In some embodiments, the gate conductor can also be an amorphous semiconductor with the above-mentioned materials.

[0085] As an example, after forming the gate structure 103 and the dummy structure 104, the method further includes the step of ion implantation to the active region 101 to form source and drain doped regions 105 and 106 on both sides of the gate structure 103 to make the source and drain of the device, respectively.

[0086] As an example, after forming the source and drain doped regions 105 and 106, the method further includes the step of ion implantation to the active region 101 on both sides of the gate structure 103 to form LDD doped regions (not shown in the figure).

[0087] The structural features and descriptions of the source and drain doped regions 105 and 106 and the LDD doped regions formed based on the above two examples can be referred to the descriptions of the semiconductor device structure in the present embodiment, which will not be repeated here.

[0088] In one example, the source / drain is combined with a high concentration dopant. For example, for an n-type MOSFET, the dopant for the source / drain can include any suitable n-type dopant, such as phosphorous, arsenic, antimony, etc., and / or any combination thereof. For a p-type MOSFET, the dopant for the source / drain can include any suitable p-type dopant, such as boron. The dopant incorporation can be achieved by ion implantation, followed by a dopant activation anneal. The source / drain can be made of the same material as the semiconductor substrate, e.g., silicon. In some embodiments, the source / drain can be made of a different material than the semiconductor substrate 100 to achieve high performance. For example, on a silicon substrate, the source / drain for a p-type MOSFET can include SiGe, and the source / drain for an n-type MOSFET can incorporate carbon. Forming the source / drain with a different material can include etching back the substrate material in the source / drain region, and using a technique such as epitaxy to set the new source / drain material. The doping of the source / drain can also be achieved by in-situ doping during epitaxy.

[0089] Additionally, optional source / drain extensions (LDD doping regions) and / or halo regions (not shown) can also be prepared along each side of the gate structure. The source / drain extensions and / or halo regions are located within the active device region below the gate stack, and can be implemented for improved short channel control of peripheral devices with channel lengths less than about 0.5 μm. The source / drain extensions and / or halo regions can be formed similarly to the source / drain, but different implant conditions (e.g., dose, angle, energy, species, etc.) can be used to achieve an optimized doping profile, depth, or concentration.

[0090] As an example, the dummy structure 104 corresponds to being located between adjacent source doping regions 105 or between adjacent drain doping regions 106 of the active regions 101. Furthermore, according to the above description of the semiconductor device structure, the dummy structure 104 can also be provided between both adjacent source doping regions 105 and adjacent drain doping regions 106, i.e. a projection of the dummy structure 104 on the isolation structure 102 is located between the source doping regions 105 and / or a projection of the dummy structure 104 on the isolation structure 102 is located between the drain doping regions 106. In a further example, the dummy structure 104 also extends in the first direction over the source doping region 105 or the drain doping region 106 of two adjacent active regions 101 to form an overlap region, wherein the size d of the overlap region in the first direction is between 1 / 5 and 1 / 3 of the size of the source doping region or the drain doping region.

[0091] In summary, the semiconductor device structure and the preparation method thereof, a dummy structure is prepared on the isolation structure between adjacent active regions, the projection of the dummy structure on the isolation structure is between the source doped regions or the drain doped regions, and can further extend to the adjacent source doped region or drain doped region to form an overlapping area, which can block part of ion implantation, effectively improve the breakdown voltage of the bit line memory, reduce the risk of breakdown, the dummy structure and the gate structure can be prepared at the same time, without changing any process conditions and steps, the process is simple and feasible, and the dummy structure of the application can not increase the device area. Therefore, the application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0092] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.

Claims

1. A semiconductor device structure, the semiconductor device structure comprising: Semiconductor substrate; Multiple active regions and multiple isolation structures are located within the semiconductor substrate, the active regions and the isolation structures are arranged alternately along a first direction, and the active regions extend along a second direction; wherein the first direction is perpendicular to the second direction; A gate structure, at least located on the active region; and A virtual structure, at least located on the isolation structure, and having a spacing between the gate structure and the virtual structure in the second direction; The active region further includes a source doped region and a drain doped region, wherein the source doped region is located on one side of the gate structure and the drain doped region is located on the other side of the gate structure; wherein, one side of the gate structure and the other side of the gate structure are oppositely arranged sides; Wherein, the projection of the virtual structure onto the isolation structure is located between the two source doped regions arranged along the first direction; and / or, the projection of the virtual structure onto the isolation structure is located between the two drain doped regions arranged along the first direction.

2. The semiconductor device structure according to claim 1, wherein, The gate structure and the virtual structure are made of the same material and have the same height.

3. The semiconductor device structure according to claim 1, wherein, The gate structure includes a plurality of gate units that correspond one-to-one with the active region. The gate units span the corresponding active region along the first direction, and each gate unit is electrically connected based on the same metal layer.

4. The semiconductor device structure according to claim 3, wherein, There is a gap between adjacent gate units, and the projections of the two gate units corresponding to two adjacent active regions and the virtual structure corresponding to the active regions in the first direction overlap.

5. The semiconductor device structure according to claim 1, wherein, The gate structure includes a strip gate that spans each of the active regions along the first direction.

6. The semiconductor device structure according to claim 1, wherein, The active region also includes a lightly doped drain region located on both sides of the gate structure.

7. The semiconductor device structure according to claim 1, wherein, The semiconductor device structure is a bit line driver.

8. The semiconductor device structure according to any one of claims 1 to 7, wherein, In the first direction, the virtual structure extends above the source doped region and has an overlapping region with the source doped region; or, in the first direction, the virtual structure extends above the drain doped region and has the overlapping region with the drain doped region.

9. The semiconductor device structure according to claim 8, wherein, When there is an overlapping region between the virtual structure and the source doped region, the size of the overlapping region along the first direction is between 1 / 5 and 1 / 3 of the size of the corresponding source doped region; When there is an overlapping region between the virtual structure and the drain doped region, the size of the overlapping region along the first direction is between 1 / 5 and 1 / 3 of the size of the corresponding drain doped region.

10. A method for fabricating a semiconductor device structure, the method comprising the following steps: Provide semiconductor substrates; Multiple active regions and isolation structures are formed in the semiconductor substrate. The active regions and isolation structures are arranged alternately along a first direction, and the active regions extend along a second direction. The first direction is perpendicular to the second direction. A gate structure and a dummy structure are fabricated on the semiconductor substrate, wherein, The gate structure is formed at least on the active region, the virtual structure is formed at least on the isolation structure, and there is a gap between the gate structure and the virtual structure in the second direction; A source doped region is formed on one side of the gate structure, and a drain doped region is formed on the other side of the gate structure; wherein, one side and the other side of the gate structure are oppositely arranged. Wherein, the projection of the virtual structure onto the isolation structure is located between the two source doped regions arranged along the first direction; and / or, the projection of the virtual structure onto the isolation structure is located between the two drain doped regions arranged along the first direction.

11. The method for fabricating a semiconductor device structure according to claim 10, wherein, The gate structure and the virtual structure are fabricated simultaneously using the same process.

12. The method for fabricating a semiconductor device structure according to claim 10, wherein, The gate structure includes a plurality of gate units corresponding one-to-one with the active regions, the gate units spanning the corresponding active regions along the first direction, and each gate unit being electrically connected based on the same metal layer; or, the gate structure includes a strip gate, the strip gate spanning each of the active regions along the first direction.

13. The method for fabricating a semiconductor device structure according to claim 12, wherein, There is a gap between adjacent gate units, and the projection of the virtual structure between the gate units corresponding to two adjacent active regions and the active regions in the first direction overlaps.

14. The method for fabricating a semiconductor device structure according to claim 10, wherein, After forming the source doped region and the drain doped region, the method further includes the step of: performing ion doping on the active regions on both sides of the gate structure to form a lightly doped drain region.

15. The method for fabricating a semiconductor device structure according to claim 10, wherein, In the first direction, the virtual structure extends over the source doped region to form an overlapping region; or, in the first direction, the virtual structure extends over the drain doped region to form the overlapping region.

16. The method for fabricating a semiconductor device structure according to claim 15, wherein, When there is an overlapping region between the virtual structure and the source doped region, the size of the overlapping region along the first direction is between 1 / 5 and 1 / 3 of the size of the corresponding source doped region; When there is an overlapping region between the virtual structure and the drain doped region, the size of the overlapping region along the first direction is between 1 / 5 and 1 / 3 of the size of the corresponding drain doped region.

Images