Silicon carbide semiconductor device

Abstract

A silicon carbide semiconductor device has a silicon carbide substrate having a first main face and a second main face opposite to the first main face. A gate trench is provided on the first main face, the gate trench being defined by a side face reaching a drift region from a through source region and a body region and a bottom face connected to the side face, and extending in a first direction parallel to the first main face. The silicon carbide substrate further has an electric field relaxation region provided between the bottom face and the second main face, extending in the first direction, and having the second conductivity type, and a connection region electrically connecting a contact region and the electric field relaxation region, and having the second conductivity type, when viewed from a direction perpendicular to the first main face, the gate trench and the electric field relaxation region are located on an imaginary straight line extending in the first direction, and the connection region is in contact with the electric field relaxation region on the imaginary straight line.

Description

Technical Field

[0001] This disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2019-230976, filed on December 20, 2019, and incorporates all the contents set forth in said Japanese application. Background Technology

[0003] As one of the silicon carbide semiconductor devices, a trench MOSFET (metal oxide semiconductor field effect transistor) with an electric field shielding region provided below the gate trench formed on the main surface has been disclosed (for example, Patent Documents 1 and 2).

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-41990

[0007] Patent Document 2: Japanese Patent Application Publication No. 2012-169385 Summary of the Invention

[0008] The silicon carbide semiconductor device disclosed herein includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes: a drift region having a first conductivity type; a body region disposed on the drift region and having a second conductivity type different from the first conductivity type; a source region disposed on the body region such that it is spaced from the drift region and has the first conductivity type; and a contact region disposed on the body region and having the second conductivity type. A gate trench is provided on the first main surface, the gate trench being defined by a side surface extending through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extending in a first direction parallel to the first main surface. The silicon carbide semiconductor device further includes a source electrode connected to the source region and the contact region. The silicon carbide substrate further comprises: an electric field relaxation region disposed between the bottom surface and the second main surface, extending in the first direction, and having a second conductivity type; and a connection region electrically connecting the contact region to the electric field relaxation region, and having the second conductivity type. When viewed from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are located on an imaginary straight line extending in the first direction, and the connection region contacts the electric field relaxation region on the imaginary straight line. Attached Figure Description

[0009] [ Figure 1 ] Figure 1 A three-dimensional cross-sectional view (1) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0010] [ Figure 2 ] Figure 2 A three-dimensional cross-sectional view (2) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0011] [ Figure 3 ] Figure 3 This diagram illustrates the structure of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the embodiment.

[0012] [ Figure 4 ] Figure 4 A cross-sectional view (1) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0013] [ Figure 5 ] Figure 5 A cross-sectional view (2) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0014] [ Figure 6 ] Figure 6 A cross-sectional view (3) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0015] [ Figure 7 ] Figure 7 A cross-sectional view (4) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0016] [ Figure 8 ] Figure 8 A cross-sectional view (5) showing the configuration of the silicon carbide semiconductor device according to the embodiment.

[0017] [ Figure 9A ] Figure 9A This is a cross-sectional view (1) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0018] [ Figure 9B ] Figure 9B This is a cross-sectional view (2) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0019] [ Figure 9C ] Figure 9C This is a cross-sectional view (3) illustrating the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0020] [ Figure 9D ] Figure 9D This is a cross-sectional view (4) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0021] [ Figure 9E ] Figure 9E This is a cross-sectional view (5) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0022] [ Figure 10A ] Figure 10A A cross-sectional view (6) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0023] [ Figure 10B ] Figure 10B A cross-sectional view (7) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0024] [ Figure 10C ] Figure 10C A cross-sectional view (8) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0025] [ Figure 10D ] Figure 10D A cross-sectional view (9) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0026] [ Figure 10E ] Figure 10E This is a cross-sectional view (10) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0027] [ Figure 10F ] Figure 10F This is a cross-sectional view (11) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0028] [ Figure 10G ] Figure 10G A cross-sectional view (12) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0029] [ Figure 11A ] Figure 11A This is a cross-sectional view (13) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0030] [ Figure 11B ] Figure 11B This is a cross-sectional view (14) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0031] [ Figure 11C ] Figure 11C This is a cross-sectional view (15) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0032] [ Figure 11D ] Figure 11D This is a cross-sectional view (16) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0033] [ Figure 11E ] Figure 11E A cross-sectional view (17) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0034] [ Figure 11F ] Figure 11F A cross-sectional view (18) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0035] [ Figure 11G ] Figure 11G A cross-sectional view (19) showing the manufacturing method of the silicon carbide semiconductor device according to the embodiment.

[0036] [ Figure 11H ] Figure 11H This is a cross-sectional view (20) illustrating a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0037] [ Figure 12 ] Figure 12 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a first variation of the embodiment.

[0038] [ Figure 13 ] Figure 13 This diagram illustrates the configuration of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to a second variation of the embodiment.

[0039] [ Figure 14 ] Figure 14 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a second variation of the embodiment.

[0040] [ Figure 15 ] Figure 15 This diagram illustrates the structure of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to a third variation of the embodiment.

[0041] [ Figure 16 ] Figure 16 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a third variation of the embodiment.

[0042] [ Figure 17 ] Figure 17 This diagram illustrates the structure of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to the fourth variation of the embodiment.

[0043] [ Figure 18 ] Figure 18 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the fourth variation of the embodiment. Detailed Implementation

[0044] [The problem this disclosure aims to solve]

[0045] In conventional silicon carbide semiconductor devices with electric field shielding, the reverse transfer capacitance is large and the conduction between the source electrode and the electric field shielding is blocked, resulting in high switching losses.

[0046] Therefore, the purpose of this disclosure is to provide a silicon carbide semiconductor device that can reduce reverse transfer capacitance and switching losses.

[0047] [The effect of this disclosure]

[0048] According to this disclosure, it is possible to reduce reverse transfer capacitance and switching losses.

[0049] The following describes the implementation method.

[0050] [Description of the implementation of this disclosure]

[0051] First, embodiments of the present disclosure are listed and described. In the following description, the same or corresponding elements are labeled with the same symbols, and the same descriptions are not repeated. In the crystallographic descriptions in this specification, individual orientations are represented by [], aggregate orientations by <>, individual planes by (), and aggregate planes by {}. Furthermore, while negative indices in crystallography are usually indicated by adding a "-" (bar) above the number, in this specification, a negative sign is added before the number.

[0052] [1] One aspect of this disclosure relates to a silicon carbide semiconductor device having a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having: a drift region having a first conductivity type; a body region disposed on the drift region and having a second conductivity type different from the first conductivity type; a source region disposed on the body region such that it is spaced apart from the drift region and having the first conductivity type; and a contact region disposed on the body region and having the second conductivity type, a gate trench being provided on the first main surface, the gate trench being a side surface extending through the source region and the body region to the drift region and an side surface opposite to the side surface. The silicon carbide semiconductor device further comprises a source electrode connected to the source region and the contact region, the bottom surface of the substrate being defined and extending in a first direction parallel to the first main surface, the silicon carbide substrate further comprising: an electric field relaxation region disposed between the bottom surface and the second main surface, extending in the first direction and having a second conductivity type; and a connection region electrically connecting the contact region to the electric field relaxation region and having the second conductivity type, wherein, when viewed from a direction perpendicular to the first main surface, the gate trench and the electric field relaxation region are located on an imaginary straight line extending in the first direction, and the connection region contacts the electric field relaxation region on the imaginary straight line.

[0053] The contact region and the electric field relaxation region are electrically connected by a connection region. The contact region is electrically connected to the source electrode. Therefore, the electric field relaxation region is electrically connected to the source electrode. This reduces the reverse transfer capacitance and effectively supplies carriers from the source electrode to the electric field relaxation region. During switching, by accelerating the movement of the depletion layer extending from the electric field relaxation region to the drift region side, switching losses are reduced. Furthermore, the gate trench and the electric field relaxation region are located on an imaginary straight line, and the connection region contacts the electric field relaxation region on this imaginary straight line. Therefore, the connection region does not easily impede the current flowing along the portion of the sidewall of the gate trench parallel to the first direction. Thus, sufficient current is ensured during conduction.

[0054] [2] In [1], the plurality of gate trenches can be arranged at certain intervals overlapping the imaginary straight line, and when viewed from a direction perpendicular to the first main surface, the connection area can be arranged between adjacent gate trenches in the first direction. By arranging the connection area between adjacent gate trenches in the first direction when viewed from a direction perpendicular to the first main surface, it is easy to ensure that the connection area is large and that the resistance in the connection area is easily reduced.

[0055] [3] In [2], the silicon carbide semiconductor device may further include: a gate insulating film that contacts the side surface and the bottom surface; a gate electrode disposed on the gate insulating film such that the gate insulating film is sandwiched between the gate electrode and the silicon carbide substrate; and an interlayer insulating film that covers the gate electrode. When viewed from a direction perpendicular to the first main surface, the contact area may have: a first region that is spaced apart from the interlayer insulating film in a second direction perpendicular to the first direction; and a second region disposed between adjacent gate trenches in the first direction, wherein the source electrode can be connected to the first region, and a first dimension of the first region in the first direction can be larger than a second dimension of the second region in the first direction. By having the first dimension larger than the second dimension, it is possible to reduce the contact resistance between the first region and the source electrode while ensuring a large current flow range when conducting.

[0056] [4] In [3], the first size can be greater than 1 and less than 6 times the second size. By making the first size greater than 1 and less than 6 times the second size, it is possible to reduce the contact resistance between the first region and the source electrode while ensuring a large current flow range when conducting, thereby suppressing the contact resistance between the source region and the source electrode to a low level.

[0057] [5] In [3] or [4], the source region and the first region may be alternately arranged in the first direction, and the first size may be larger than the third size of the source region in the first direction. By making the first size larger than the third size, the contact resistance between the first region and the source electrode and the contact resistance between the source region and the source electrode can be suppressed to a low level, respectively.

[0058] [6] In [3] or [4], the source region and the first region may be alternately arranged in the first direction, and the first size may be more than 0.2 times and less than 0.6 times the sum of the first size and the third size of the source region in the first direction. By making the first size more than 0.2 times and less than 0.6 times the sum of the first size and the third size, the contact resistance between the first region and the source electrode and the contact resistance between the source region and the source electrode can be suppressed to a low level.

[0059] [7] In [3] to [6], the second region may be exposed from the interlayer insulating film, and the source electrode may also be connected to the second region. By connecting the source electrode to the second region, the contact resistance between the contact area and the source electrode can be further reduced.

[0060] [8] In [3] to [7], the contact region may have the first region on both sides of the gate trench in the second direction. By having the contact region have the first region on both sides of the gate trench in the second direction, it is easy to suppress the resistance between the source electrode and the electric field relaxation region.

[0061] [9] In [3] to [7], the contact area may have the first area on only one side of the gate trench in the second direction. By having the first area on only one side of the gate trench in the second direction, the contact hole on the side where the first area is not provided can be narrower than the contact hole on the side where the first area is provided, and it is easy to make the cell pitch in the second direction narrower.

[0062]

[10] In [1] to [9], the first effective concentration of the second conductivity type of impurity in the contact region can be higher than the second effective concentration of the second conductivity type of impurity in the connection region. By having the first effective concentration higher than the second effective concentration, leakage current can be suppressed while suppressing the contact resistance between the contact region and the source electrode.

[0063]

[11] In [1] to

[10] , the sidewalls of the gate trench may include {0-33-8} surfaces. By including {0-33-8} surfaces on the sidewalls, good mobility can be obtained on the sidewalls of the gate trench, and the channel resistance can be reduced.

[0064] [Implementation of this disclosure]

[0065] Embodiments of this disclosure relate to so-called vertical MOSFETs (silicon carbide semiconductor devices). Figure 1 and Figure 2 This is a three-dimensional cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. Figure 2 A portion of the internal structure of a silicon carbide semiconductor device is shown in perspective. Figure 3 This diagram illustrates the structure of the interlayer insulating film and the first main surface in the silicon carbide semiconductor device according to the embodiment. Figures 4-8 This is a cross-sectional view showing the configuration of the silicon carbide semiconductor device according to the embodiment. Figure 4 For equivalent to along Figure 3 , Figure 7 and Figure 8 The cross-sectional view obtained from line IV-IV in the diagram. Figure 5 For equivalent to along Figure 3 , Figure 7 and Figure 8 The cross-sectional view obtained from the VV line. Figure 6 For equivalent to along Figure 3 , Figure 7 and Figure 8 The cross-sectional view obtained from the VI-VI line. Figure 7 For equivalent to along Figure 3 , Figure 4 , Figure 5 and Figure 6 The cross-sectional view obtained from line VII-VII in the diagram. Figure 8 For equivalent to along Figure 3 , Figure 4 , Figure 5 and Figure 6 The cross-sectional view obtained from line VIII-VIII in the diagram.

[0066] like Figures 1 to 8 As shown, the MOSFET 100 according to this embodiment mainly includes: a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, a barrier metal film 84, and a passivation film 85. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 located on the silicon carbide single crystal substrate 50. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are, for example, made of polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains, for example, n-type impurities such as nitrogen (N) and has an n-type (first conductivity type). The maximum diameter of the first main surface 1 of the silicon carbide substrate 10 is, for example, 100 mm or more, preferably 150 mm or more.

[0067] The first principal surface 1 is a surface obtained by tilting the {0001} surface or the {0001} surface at an angle of less than 8° in the deviation direction. Preferably, the first principal surface 1 is a surface obtained by tilting the (000-1) surface or the (000-1) surface at an angle of less than 8° in the deviation direction. The deviation direction can be, for example, a <11-20> direction or a <1-100> direction. The deviation angle can be, for example, more than 1° or more than 2°. The deviation angle can be less than 6° or less than 4°.

[0068] The silicon carbide epitaxial layer 40 mainly has: a drift region 11, a bulk region 12, a source region 13, an electric field relaxation region 16, a connection region 17, and a contact region 18.

[0069] Drift region 11 may contain, for example, n-type impurities such as nitrogen or phosphorus (P) and has an n-type conductivity. Drift region 11 may primarily have a third region 11C, a fourth region 11D, and a fifth region 11E.

[0070] Body region 12 is disposed on drift region 11. Body region 12 contains, for example, p-type impurities such as aluminum (Al) and has p-type (second conductivity type) conductivity. The effective concentration of p-type impurities in body region 12 is 5 × 10⁻⁶. 17 cm -3The above describes the short-channel effect (punch-through). This effect occurs because the depletion layer can extend from the pn junction region into the channel region, causing the entire channel region to become a depletion layer. Increasing the effective concentration of p-type impurities in the body region 12 can reduce the extension of the depletion layer formed in the channel region. The thickness of the body region 12 can, for example, be less than 0.7 μm. The effective concentration of p-type impurities in the body region 12 is, for example, approximately 1 × 10⁻⁶. 18 cm -3 .

[0071] Source region 13 is disposed on body region 12, thereby separating it from drift region 11. Source region 13 contains, for example, n-type impurities such as nitrogen or phosphorus, and has n-type conductivity. Source region 13 constitutes the first principal surface 1. The effective concentration of n-type impurities in source region 13 can be higher than the effective concentration of p-type impurities in body region 12. The effective concentration of n-type impurities in source region 13 is, for example, about 1 × 10⁻⁶. 19 cm -3 .

[0072] Contact region 18 contains, for example, p-type impurities such as aluminum and has p-type conductivity. Contact region 18 constitutes the first main surface 1. Contact region 18 mainly has, for example, a first region 18A and a second region 18B. The effective concentration of p-type impurities in contact region 18 is, for example, higher than the effective concentration of p-type impurities in body region 12 and the effective concentration of p-type impurities in connection region 17. Contact region 18 penetrates source region 13 and contacts body region 12. The effective concentration of p-type impurities in contact region 18 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 20 cm -3 the following.

[0073] A gate trench 5, defined by a side surface 3 and a bottom surface 4, is provided on the first main surface 1. The side surface 3 penetrates the source region 13, the body region 12, and the drift region 11 to reach the electric field relaxation region 16. The bottom surface 4 is connected to the side surface 3. The bottom surface 4 is located in the electric field relaxation region 16. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 relative to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 can be, for example, 50° or more. The angle θ1 can be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that can obtain excellent mobility.

[0074] In particular, such as Figure 3As shown, when viewed from a direction perpendicular to the first main surface 1, the gate trench 5 overlaps with an imaginary straight line L1 extending in a first direction parallel to the first main surface 1. When viewed from a direction perpendicular to the first main surface 1, the gate trench 5 is located on the imaginary straight line L1. A plurality of gate trenches 5 are provided at certain intervals along the imaginary straight line L1. Furthermore, when viewed from a direction perpendicular to the first main surface 1, a plurality of gate trenches 5 are also provided at certain intervals in a second direction perpendicular to the first direction. The plurality of gate trenches 5 can, for example, be arranged in an array.

[0075] The electric field relaxation region 16 contains, for example, p-type impurities such as Al and has p-type conductivity. The electric field relaxation region 16 is located between the bottom surface 4 of the gate trench 5 and the second main surface 2. The upper end surface of the electric field relaxation region 16 includes, for example, the bottom surface 4 of the gate trench 5. A portion of the upper end surface of the electric field relaxation region 16 is opposite to a portion of the lower end surface of the body region 12. The electric field relaxation region 16, like the gate trench 5, overlaps with an imaginary straight line L1 when viewed from a direction perpendicular to the first main surface 1. When viewed from a direction perpendicular to the first main surface 1, the electric field relaxation region 16 is located on the imaginary straight line L1. The electric field relaxation region 16 can be commonly provided on multiple gate trenches 5 along the imaginary straight line L1. Furthermore, when viewed from a direction perpendicular to the first main surface 1, multiple electric field relaxation regions 16 are provided at certain intervals in a second direction perpendicular to the first direction. The multiple electric field relaxation regions 16 can be provided in a strip shape. The effective concentration of p-type impurities in the electric field relaxation region 16 is, for example, 5 × 10⁻⁶. 17 cm -3 Above and 5×10 18 cm -3 the following.

[0076] The third region 11C of drift region 11 is sandwiched between body region 12 and electric field relaxation region 16. The third region 11C is in contact with both body region 12 and electric field relaxation region 16. The third region 11C is located closer to the second principal surface 2 than body region 12. The third region 11C is located closer to the first principal surface 1 than electric field relaxation region 16. The effective concentration of n-type impurities in the third region 11C is, for example, 5 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0077] Region 11D is located closer to the second principal surface 2 than Region 11C. Region 11D is connected to Region 11C. Region 11D is in contact with the electric field relaxation region 16 in a direction parallel to the second principal surface 2. Region 11D and the electric field relaxation region 16 can be located on the same plane parallel to the second principal surface 2. The effective concentration of n-type impurities in Region 11D can be higher than the effective concentration of n-type impurities in Region 11C. For example, the effective concentration of n-type impurities in Region 11D is 5 × 10⁻⁶.16 cm -3 Above and 5×10 17 cm -3 the following.

[0078] The fifth region 11E is located closer to the second main surface 2 than the fourth region 11D. The fifth region 11E is connected to the fourth region 11D. The fifth region 11E is in contact with the electric field relaxation region 16. The fifth region 11E is located closer to the second main surface 2 than the electric field relaxation region 16. The fifth region 11E can be sandwiched between the fourth region 11D and the silicon carbide single crystal substrate 50. The fifth region 11E can be connected to the silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in the fifth region 11E can be lower than the effective concentration of n-type impurities in the fourth region 11D. For example, the effective concentration of n-type impurities in the fifth region 11E is 5 × 10⁻⁶. 15 cm -3 Above and 5×10 16 cm -3 the following.

[0079] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is, for example, made of a material containing silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the electric field relaxation region 16 on the bottom surface 4. The gate insulating film 81 is in contact with the source region 13, the body region 12, and the drift region 11 on the side surface 3, respectively. The gate insulating film 81 may be in contact with the source region 13 on the first main surface 1.

[0080] The gate electrode 82 is disposed on the gate insulating film 81. The gate electrode 82 is, for example, made of polycrystalline silicon (polycrystalline Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. A portion of the gate electrode 82 may be disposed on the first main surface 1.

[0081] The interlayer insulating film 83 is configured to contact the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 is electrically insulated from the gate electrode 82 and the source electrode 60. A portion of the interlayer insulating film 83 may be disposed inside the gate trench 5.

[0082] The interlayer insulating film 83, like the gate trench 5 and the electric field relaxation region 16, overlaps with the imaginary straight line L1 when viewed from a direction perpendicular to the first main surface 1. The interlayer insulating film 83 can be commonly disposed on multiple gate trenches 5 along the imaginary straight line L1. When viewed from a direction perpendicular to the first main surface 1, contact holes 90 are formed at intervals in a second direction on both the interlayer insulating film 83 and the gate insulating film 81. The contact holes 90 are arranged such that, when viewed from a direction perpendicular to the first main surface 1, the gate trenches 5 are located between adjacent contact holes 90 in the second direction. The contact holes 90 extend in the first direction. The source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 through the contact holes 90. The size of the contact holes 90 in the second direction can, for example, be less than 1 μm.

[0083] Especially as Figure 3 As shown, the first region 18A of the contact region 18 is exposed from the interlayer insulating film 83 through the contact hole 90. The first region 18A can be disposed between adjacent gate trenches 5 in the second direction. Between two adjacent gate trenches 5 in the second direction, the first region 18A and the source region 13 can be alternately disposed in the first direction. For example, the first region 18A can be disposed near the end of the gate trench 5 in the first direction, and the source region 13 can be disposed near the center of the gate trench 5 in the first direction. The first region 18A is disposed on both sides of the gate trench 5 in the second direction. The first region 18A and the source region 13 can be exposed from all the contact holes 90.

[0084] The second region 18B is disposed between adjacent gate trenches 5 in the first direction. The second region 18B is covered by an interlayer insulating film 83 and a barrier metal film 84. The second region 18B is connected to the first region 18A in the second direction. The first region 18A and the second region 18B are disposed alternately in the second direction. For example, the first dimension Wp1 of the first region 18A in the first direction is larger than the second dimension Wp2 of the second region 18B in the first direction.

[0085] The connection region 17 contains, for example, p-type impurities such as Al and has p-type conductivity. The connection region 17 is electrically connected to the contact region 18 and the electric field relaxation region 16. The connection region 17 contacts the electric field relaxation region 16 on an imaginary straight line L1. The connection region 17 contacts either the body region 12 or the contact region 18. The connection region 17 can contact both the body region 12 and the contact region 18. The connection region 17 is located between the electric field relaxation region 16 and the contact region 18. The connection region 17 is located on the side closer to the second main surface 2 than the contact region 18. The connection region 17 is located on the side closer to the first main surface 1 than the electric field relaxation region 16. For example, in a direction perpendicular to the second main surface 2, the connection region 17 is located between the second region 18B and the electric field relaxation region 16, and can contact both the second region 18B and the electric field relaxation region 16 respectively. In the direction perpendicular to the second principal surface 2, the connection region 17 is located between the second region 18B and the electric field relaxation region 16. When in contact with both the second region 18B and the electric field relaxation region 16, the series resistance between them decreases. The effective concentration of p-type impurities in the connection region 17 can be approximately the same as the effective concentration of p-type impurities in the electric field relaxation region 16. For example, the effective concentration of p-type impurities in the connection region 17 is 5 × 10⁻⁶. 17 cm -3 Above and 5×10 18 cm -3 the following.

[0086] If the multiple gate trenches 5 arranged in the first direction are assumed to be a gate trench assembly, then the gate trench assembly can be considered to be divided into multiple gate trenches 5 by the second region 18B and the connection region 17.

[0087] A barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81, respectively. The barrier metal film 84 is, for example, made of a material containing titanium nitride (TiN).

[0088] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 has a contact electrode 61 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the first region 18A of the contact region 18 on the first main surface 1. The contact electrode 61 is made of, for example, a material containing nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is ohmically bonded to the source region 13 and the first region 18A of the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61, respectively. The source wiring 62 is made of, for example, a material containing Al.

[0089] A passivation film 85 covers the upper surface of the source wiring 62. The passivation film 85 is in contact with the source wiring 62. The passivation film 85 is, for example, made of a material containing polyimide.

[0090] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single-crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is, for example, made of a material containing NiSi. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is ohmically bonded to the silicon carbide single-crystal substrate 50.

[0091] In a direction perpendicular to the second main surface 2, the upper end surface of the electric field relaxation region 16 can be spaced apart from the bottom surface 4. In this case, for example, the bottom surface 4 can be located in the drift region 11, and the side surface 3 can penetrate the source region 13 and the volume region 12 to reach the drift region 11. For example, a third region 11C can be present between the upper end surface and the bottom surface 4 of the electric field relaxation region 16.

[0092] A buffer layer containing, for example, n-type impurities such as nitrogen and having n-type conductivity can be provided between the silicon carbide single crystal substrate 50 and the fifth region 11E. The effective concentration of n-type impurities in the buffer layer can be higher than the effective concentration of n-type impurities in the fifth region 11E.

[0093] Next, the manufacturing method of the MOSFET 100 according to the embodiment will be described. Figures 9A to 9E , Figures 10A to 10G and Figures 11A to 11H This is a cross-sectional view illustrating the manufacturing method of the MOSFET 100 according to the embodiment. Figures 9A to 9E Indicates in Figure 4 The cross section shown and in Figure 6 The common changes of the cross sections shown. Figures 10A to 10G Indicates in Figure 4 The changes in the cross section are shown. Figures 11A to 11H Indicates in Figure 6 The changes in the cross section are shown.

[0094] First, such as Figure 9A As shown, the process of preparing a silicon carbide single crystal substrate 50 is performed. For example, the silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured using the sublimation method. A buffer layer (not shown) can be formed on the silicon carbide single crystal substrate 50. The buffer layer can be formed, for example, using a mixture of silane (SiH4) and propane (C3H8) as the feed gas and a chemical vapor deposition (CVD) method using, for example, hydrogen (H2) as the carrier gas. During the epitaxial growth of the buffer layer, for example, n-type impurities such as nitrogen can be introduced into the buffer layer.

[0095] Then, similarly Figure 9A As shown, the process of forming the first epitaxial layer 21 is performed. For example, a mixture of silane and propane is used as the raw material gas, and the first epitaxial layer 21 is formed on a silicon carbide single crystal substrate 50 by a CVD method using, for example, hydrogen as the carrier gas. During epitaxial growth, for example, n-type impurities such as nitrogen are introduced into the first epitaxial layer 21. The first epitaxial layer 21 has an n-type conductivity. The effective concentration of the n-type impurities in the first epitaxial layer 21 can be lower than the effective concentration of the n-type impurities in the buffer layer.

[0096] Next, as Figure 9B As shown, the process of forming the electric field relaxation region 16 is performed. For example, a mask layer (not shown) with an opening is formed in the region where the electric field relaxation region 16 is formed. Next, for example, p-type impurity ions capable of imparting p-type properties, such as aluminum ions, are implanted into the first epitaxial layer 21. Thus, the electric field relaxation region 16 is formed.

[0097] Next, as Figure 9C As shown, the process of forming the fourth region 11D is performed. For example, a mask layer (not shown) with an opening is formed in the region where the fourth region 11D is formed, that is, in the region on the side of the electric field relaxation region 16 in the direction parallel to the second main surface 2. Next, n-type impurity ions capable of imparting n-type are implanted into the first epitaxial layer 21, such as nitrogen. Thus, the fourth region 11D is formed. In the first epitaxial layer 21, the portion closer to the silicon carbide single crystal substrate 50 than the electric field relaxation region 16 and the portion closer to the silicon carbide single crystal substrate 50 than the fourth region 11D are formed as the fifth region 11E. The effective concentration of n-type impurities in the fourth region 11D is higher than the effective concentration of n-type impurities in the fifth region 11E.

[0098] Next, as Figure 9D As shown, the process of forming the second epitaxial layer 22 is performed. For example, a mixture of silane and propane is used as the feed gas, and the second epitaxial layer 22 is formed on the first epitaxial layer 21 by a CVD method using, for example, hydrogen as the carrier gas. During epitaxial growth, for example, n-type impurities such as nitrogen are introduced into the second epitaxial layer 22. The second epitaxial layer 22 has an n-type conductivity. The thickness of the second epitaxial layer 22 is, for example, 0.8 μm or more and 1.2 μm or less. For example, the effective concentration of n-type impurities in the second epitaxial layer 22 is lower than the effective concentration of n-type impurities in the fourth region 11D.

[0099] Next, as Figure 9E As shown, the process of forming body region 12 is performed. P-type impurity ions, such as aluminum ions, capable of imparting a p-type structure are implanted onto the entire surface of the second epitaxial layer 22. Thus, body region 12 is formed.

[0100] Then, similarly Figure 9EAs shown, the process of forming source region 13 is performed. For example, phosphorus or other n-type impurity ions capable of imparting an n-type form are implanted onto the entire surface of the second epitaxial layer 22. Thus, source region 13 is formed.

[0101] Next, as Figure 11A As shown, the process of forming the connection region 17 is performed. For example, a mask layer (not shown) with an opening is formed on the region where the connection region 17 is formed. Next, p-type impurity ions, such as aluminum ions, which can impart p-type characteristics, are implanted into the source region 13, the body region 12, and the third region 11C. As a result, the connection region 17 is formed in contact with the body region 12 and the electric field relaxation region 16.

[0102] Next, as Figure 11B As shown, the process of forming contact region 18 is performed. For example, a mask layer (not shown) with an opening is formed on the area where contact region 18 is formed. Next, p-type impurity ions, such as aluminum ions, which can impart p-type properties, are implanted into the connection region 17. Thus, contact region 18 is formed that contacts body region 12 and connection region 17.

[0103] Next, in order to activate the impurity ions implanted into the silicon carbide substrate 10, activation annealing is performed. The activation annealing temperature is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The activation annealing time is, for example, about 30 minutes. The activation annealing atmosphere is preferably an inert gas atmosphere, for example, an Ar atmosphere.

[0104] Next, as Figure 10A As shown, the process of forming the gate trench 5 is performed. For example, a mask layer (not shown) is formed on a first main surface 1 consisting of a source region 13 and a contact region 18, the mask layer having an opening at the location where the gate trench 5 is formed. Using the mask layer, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. As an etching method, reactive ion etching, particularly inductively coupled plasma reactive ion etching, can be used, for example. Specifically, inductively coupled plasma reactive ion etching, for example, can be used using sulfur hexafluoride (SF6) or a mixture of SF6 and oxygen (O2) as the reactive gas. By etching, a recess (not shown) is formed in the area where the gate trench 5 is to be formed, the recess having a side portion that is substantially perpendicular to the first main surface 1 and a bottom portion that is continuous with the side portion and substantially parallel to the first main surface 1.

[0105] Next, thermal etching is performed on the recess. Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one halogen atom, while a mask layer is formed on the first main surface 1. The at least one halogen atom includes at least any one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere may contain, for example, chlorine (Cl2), boron trichloride (BCl3), SF6, or carbon tetrafluoride (CF4). For example, a mixture of chlorine and oxygen is used as the reactive gas, and the heat treatment temperature is set, for example, to 800°C or higher and 900°C or lower, for thermal etching. It should be noted that the reactive gas may contain a carrier gas in addition to the chlorine and oxygen. For example, nitrogen, argon, or helium may be used as the carrier gas.

[0106] By means of thermal etching, a gate trench 5 is formed on the first main surface 1 of the silicon carbide substrate 10. The gate trench 5 is defined by a side surface 3 and a bottom surface 4. The side surface 3 is composed of a source region 13, a body region 12, and a drift region 11. The bottom surface 4 is composed of an electric field relaxation region 16. The angle θ1 between the side surface 3 and the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. Then, the mask layer is removed from the first main surface 1.

[0107] Next, as Figure 10B and Figure 11C As shown, the process of forming a gate insulating film 81 is performed. For example, a gate insulating film 81 is formed by thermally oxidizing a silicon carbide substrate 10, which contacts the source region 13, the body region 12, the drift region 11, the electric field relaxation region 16, and the contact region 18. Specifically, the silicon carbide substrate 10 is heated in an atmosphere containing oxygen, for example, at a temperature of 1300°C or higher and 1400°C or lower. As a result, a gate insulating film 81 is formed that contacts the first main surface 1, the side surface 3, and the bottom surface 4.

[0108] Next, the silicon carbide substrate 10 can be heat-treated (NO annealing) in a nitric oxide (NO) atmosphere. In NO annealing, the silicon carbide substrate 10 is held, for example, at a temperature above 1100°C and below 1400°C for about 1 hour. This introduces nitrogen atoms into the interface region between the gate insulating film 81 and the body region 12. As a result, the channel mobility can be improved by suppressing the formation of interface energy levels in the interface region.

[0109] Next, as Figure 10C and Figure 11D As shown, the process of forming the gate electrode 82 is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed, for example, by low-pressure CVD (low-pressure chemical vapor deposition: LP-CVD). The gate electrode 82 is formed opposite to the source region 13, the body region 12, and the drift region 11, respectively.

[0110] Next, as Figure 10D and Figure 11E As shown, the process of forming an interlayer insulating film 83 is performed. Specifically, the interlayer insulating film 83 is formed in a manner that covers the gate electrode 82 and contacts the gate insulating film 81. The interlayer insulating film 83 is formed, for example, by a CVD method. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. A portion of the interlayer insulating film 83 may be formed inside the gate trench 5.

[0111] Next, as Figure 10E and Figure 11F As shown, the process of forming a barrier metal film 84, a contact electrode 61, and a drain electrode 70 is performed. For example, by etching in the form of forming contact holes 90 on the interlayer insulating film 83 and the gate insulating film 81, the source region 13 and the first region 18A are exposed from the interlayer insulating film 83 and the gate insulating film 81 at the contact holes 90. Next, a barrier metal film 84 is formed covering the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is, for example, made of a material containing TiN. The barrier metal film 84 is formed, for example, by film formation using sputtering and reactive ion etching (RIE). Next, a metal film (not shown) for contact electrode 61 that contacts the source region 13 and the first region 18A is formed on the first main surface 1. The metal film for contact electrode 61 is formed, for example, by sputtering. The metal film for contact electrode 61 is, for example, made of a material containing Ni. Next, a metal film (not shown) for a drain electrode 70, which contacts the silicon carbide single-crystal substrate 50, is formed on the second main surface 2. The metal film for the drain electrode 70 is formed, for example, by sputtering. The metal film for the drain electrode 70 is made of, for example, a material containing Ni.

[0112] Next, alloying annealing is performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature, for example, above 900°C and below 1100°C, for about 5 minutes. As a result, at least a portion of the metal film for the contact electrode 61 and at least a portion of the metal film for the drain electrode 70 reacts with the silicon contained in the silicon carbide substrate 10 to form a silicide. This forms a contact electrode 61 with an ohmic bond to the source region 13 and the first region 18A, and a drain electrode 70 with an ohmic bond to the silicon carbide single-crystal substrate 50. The contact electrode 61 may be made of a material containing Ti, Al, and Si. The drain electrode 70 may be made of a material containing Ti, Al, and Si.

[0113] Next, as Figure 10F and Figure 11GAs shown, the process of forming source wiring 62 is performed. Specifically, source wiring 62 covering contact electrode 61 and barrier metal film 84 is formed. Source wiring 62 is formed, for example, by film deposition and RIE using sputtering. Source wiring 62 is made of, for example, a material containing aluminum. In this way, source electrode 60 having contact electrode 61 and source wiring 62 is formed.

[0114] Next, as Figure 10G and Figure 11H As shown, the process of forming a passivation film 85 is performed. Specifically, a passivation film 85 covering the source wiring 62 is formed. The passivation film 85 is, for example, made of a material containing polyimide. The passivation film 85 is formed, for example, by a coating method. The passivation film 85 can also be formed by plasma CVD.

[0115] In this way, the MOSFET 100 involved in the implementation method is completed.

[0116] Next, the effects of the MOSFET involved in this embodiment will be explained.

[0117] In the MOSFET 100 of this embodiment, the contact region 18 and the electric field relaxation region 16 are electrically connected via a connection region 17. The contact region 18 is electrically connected to the source electrode 60. Therefore, the electric field relaxation region 16 is electrically connected to the source electrode 60. Thus, carriers can be supplied from the source electrode 60 to the electric field relaxation region 16, and the reverse transfer capacitance can be reduced. By reducing the reverse transfer capacitance, switching losses can be reduced, and switching speed can be increased.

[0118] Furthermore, the gate trench 5 and the electric field relaxation region 16 are located on the imaginary straight line L1. That is, the gate trench 5 and the electric field relaxation region 16 overlap with the imaginary straight line L1. Moreover, the connection region 17 contacts the electric field relaxation region 16 on the imaginary straight line L1. Therefore, the connection region 17 does not easily obstruct the drain current flowing along the portion of the side surface 3 parallel to the first direction, that is, the portion of the side surface 3 spaced apart from the end of the gate trench 5 in the first direction. Therefore, sufficient drain current can be ensured when the circuit is turned on.

[0119] When viewed from a direction perpendicular to the first main surface 1, a connection region 17 is provided between adjacent gate trenches 5 in the first direction. When viewed from a direction perpendicular to the first main surface 1, the connection region 17 can overlap with the gate trenches 5, but when provided between the gate trenches 5, the volume of the connection region 17 can be increased, and the resistance in the connection region 17 can be reduced. Furthermore, if a source region 13, a body region 12, and a drift region 11 exist between the end of the gate trench 5 in the first direction and the second region 18B, drain current can also flow in the region between the gate trench 5 and the second region 18B in the first direction.

[0120] In this embodiment, the semiconductor region near the upper end of the gate trench 5 is an n-type source region 13. A p-type contact region 18 may also be present near the upper end of the gate trench 5, but the gate insulating film 81 tends to be thinner in the p-type contact region 18 compared to the n-type source region 13. Furthermore, the electric field tends to concentrate near the upper end of the gate trench 5. By using an n-type source region 13 as the semiconductor region near the upper end of the gate trench 5, a thick gate insulating film 81 can be easily formed, thus suppressing the insulation breakdown of the gate insulating film 81 that accompanies the electric field concentration near the upper end of the gate trench 5.

[0121] The first region 18A is provided on both sides of the gate trench 5 in the second direction. Therefore, compared with the case where the first region 18A is provided on only one side of the gate trench 5 in the second direction, the resistance between the source electrode 60 and the electric field relaxation region 16 can be suppressed.

[0122] In the direction perpendicular to the second main surface 2, the connection region 17 is located between the second region 18B and the electric field relaxation region 16, and by contacting the second region 18B and the electric field relaxation region 16 respectively, the series resistance between the second region 18B and the electric field relaxation region 16 can be reduced.

[0123] The first effective concentration of p-type impurities in contact region 18 is preferably higher than the second effective concentration of p-type impurities in connection region 17. Because of the high first effective concentration, the contact resistance between contact region 18 and contact electrode 61 can be suppressed. When the second effective concentration is higher than the first effective concentration, leakage current may easily flow due to the introduction of crystal defects.

[0124] The first dimension Wp1 of the first region 18A in the first direction is preferably larger than the second dimension Wp2 of the second region 18B in the first direction. Since the contact electrode 61 is ohmically connected to the first region 18A, the larger the first dimension Wp1 is, the lower the contact resistance between the first region 18A and the contact electrode 61 can be. On the other hand, since the second region 18B is disposed between adjacent gate trenches 5 in the first direction, when the second dimension Wp2 is as large as the first dimension Wp1, the range through which the drain current flows becomes narrower, and it may be difficult to obtain sufficient drain current. By making the first dimension Wp1 larger than the second dimension Wp2, it is possible to reduce the contact resistance between the first region 18A and the source electrode 60 while ensuring a large range through which the drain current flows when the circuit is turned on. Therefore, the first dimension Wp1 is preferably larger than the second dimension Wp2.

[0125] For example, the first size Wp1 is preferably greater than 1 and less than 6 times the second size Wp2. When the first size Wp1 is greater than 6 times the second size Wp2, the area where the contact electrode 61 may form an ohmic connection with the source region 13 inside the contact hole 90 becomes smaller, and the contact resistance between the source region 13 and the contact electrode 61 becomes higher. By making the first size Wp1 greater than 1 and less than 6 times the second size Wp2, it is possible to reduce the contact resistance between the first region 18A and the source electrode 60 while ensuring a large range of drain current flow during conduction, thereby suppressing the contact resistance between the source region 13 and the source electrode 60 to a low level. Therefore, the first size Wp1 is more preferably more than 2 and less than 5 times the second size Wp2.

[0126] For example, the first dimension Wp1 is preferably larger than the third dimension Wn in the first direction of the source region 13. Generally, p-type impurities are more difficult to activate than n-type impurities. By making the first dimension Wp1 larger than the third dimension Wn, the contact resistance between the first region 18A and the contact electrode 61 and the contact resistance between the source region 13 and the contact electrode 61 can be suppressed to a low level.

[0127] For example, the first dimension Wp1 is preferably 0.2 times or more and 0.6 times or less than the sum of the first dimension Wp1 and the third dimension Wn, Wch. When the first dimension Wp1 is less than 0.2 times Wch, the contact resistance between the first region 18A and the contact electrode 61 may become too high. When the first dimension Wp1 is greater than 0.6 times Wch, the contact resistance between the source region 13 and the contact electrode 61 may become too high. By making the first dimension Wp1 more than 0.2 times and 0.6 times Wch, the contact resistance between the first region 18A and the contact electrode 61, and the contact resistance between the source region 13 and the contact electrode 61, can be suppressed to a low level. The first dimension Wp1 is more preferably 0.3 times and 0.6 times Wch.

[0128] By including the {0-33-8} surface on the side 3 of the gate trench 5, excellent mobility can be obtained in the channel, and the channel resistance can be reduced.

[0129] [First Variation]

[0130] Next, a first variation of the embodiment will be described. The first variation differs from the embodiment mainly in the shape of the gate trench. Figure 12 This is a cross-sectional view showing the configuration of the MOSFET (silicon carbide semiconductor device) according to the first variation of the embodiment. Figure 12 Indicates and along Figure 3 The cross section obtained by the IV-IV line is the same as the cross section.

[0131] like Figure 12As shown, in the MOSFET 110 of the first modified example, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 relative to the plane including the bottom surface 4 can be 90°. Other configurations are the same as in the embodiment.

[0132] The same effect as the implementation method can be obtained through such a first variation.

[0133] [Second variation]

[0134] Next, a second variation of the embodiment will be described. The second variation differs from the embodiment mainly in the position of the first region 18A. Figure 13 This diagram illustrates the configuration of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to a second variation of the embodiment. Figure 14 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a second variation of the embodiment. Figure 14 Equivalent to along Figure 13 The cross-sectional view is obtained by the XIV-XIV line in the diagram.

[0135] In the MOSFET 120 involved in the second variation, such as Figure 13 and Figure 14 As shown, the first region 18A is disposed on only one side of the gate trench 5 in the second direction. Contact holes 91 and 92 are formed on the interlayer insulating film 83. Contact holes 91 and 92 are alternately arranged in the second direction. The first region 18A may be disposed on the portion of the first main surface 1 exposed by contact hole 91, but not on the portion of the first main surface 1 exposed by contact hole 92. The first region 18A and the source region 13 may be exposed from contact hole 91. Alternatively, only the source region 13 may be exposed from contact hole 92. Inside contact hole 91, contact electrode 61 is ohmically engaged with both source region 13 and first region 18A. Inside contact hole 92, contact electrode 61 is ohmically engaged with source region 13. Other structures are the same as in the embodiment.

[0136] According to the second modification, the reverse transfer capacitance can also be reduced, thereby reducing switching losses and increasing switching speed. According to the second modification, sufficient drain current can also be ensured. According to the second modification, insulation breakdown of the gate insulating film 81 associated with electric field concentration near the upper end of the gate trench 5 can also be suppressed. According to the second modification, the series resistance between the second region 18B and the electric field relaxation region 16 can also be reduced.

[0137] [Third variation]

[0138] Next, a third variation of the embodiment will be described. The third variation differs from the embodiment mainly in the configuration of the contact area 18. Figure 15This diagram illustrates the structure of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to a third variation of the embodiment. Figure 16 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a third variation of the embodiment. Figure 16 For equivalent to along Figure 15 Cross-sectional view obtained from the XVI-XVI line.

[0139] In the MOSFET 140 involved in the third variation, such as Figure 15 and Figure 16 As shown, the contact region 18 is composed of a first region 18A, and does not include a second region 18B. Between adjacent gate trenches 5 in the first direction, below the interlayer insulating film 83 and the barrier metal film 84, a connection region 17 can form a first main surface 1. The connection region 17 can contact the gate insulating film 81 and the barrier metal film 84. Other configurations are the same as in the embodiment.

[0140] According to the third modification, the reverse transfer capacitance can also be reduced, thereby reducing switching losses and increasing switching speed. The third modification also ensures sufficient drain current. According to the third modification, insulation breakdown of the gate insulating film 81, which is associated with electric field concentration near the upper end of the gate trench 5, can also be suppressed. According to the third modification, compared to the case where the first region 18A is provided on only one side of the gate trench 5 in the second direction, the resistance between the source electrode 60 and the electric field relaxation region 16 can also be reduced.

[0141] [Fourth variation]

[0142] Next, a fourth variation of the embodiment will be described. The fourth variation differs from the embodiment mainly in the configuration of the gate trench 5. Figure 17 This diagram illustrates the structure of the interlayer insulating film and the first main surface in a silicon carbide semiconductor device according to the fourth variation of the embodiment. Figure 18 This is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to the fourth variation of the embodiment. Figure 18 For equivalent to along Figure 17 The cross-sectional view obtained from the XVIII-XVIII line.

[0143] In the MOSFET 150 involved in the fourth variation, such as Figure 17 and Figure 18 As shown, in this embodiment, a plurality of gate trenches 5 arranged on an imaginary straight line L1 are interconnected to form a gate trench 5A. A second region 18B and a connecting region 17 are disposed on both sides of the gate trench 5A in a second direction. The second region 18B and the connecting region 17 can contact the side surface 3. Other configurations are the same as in this embodiment.

[0144] According to the fourth modification, the reverse transfer capacitance can also be reduced, thereby reducing switching losses and increasing switching speed. The fourth modification also ensures sufficient drain current. According to the fourth modification, compared to the case where the first region 18A is provided on only one side of the gate trench 5 in the second direction, the resistance between the source electrode 60 and the electric field relaxation region 16 can also be reduced. According to the fourth modification, the series resistance between the second region 18B and the electric field relaxation region 16 can also be reduced.

[0145] In the embodiments and reference examples described above, n-type is described as the first conductivity type and p-type as the second conductivity type, but p-type can also be described as the first conductivity type and n-type as the second conductivity type. In the embodiments and reference examples described above, a MOSFET is used as an example of a silicon carbide semiconductor device, but silicon carbide semiconductor devices can also be, for example, insulated gate bipolar transistors (IGBTs). The effective concentrations of p-type and n-type impurities in each impurity region can be measured, for example, by scanning capacitance microscopy (SCM) or secondary ion mass spectrometry (SIMS). The position of the boundary between the p-type and n-type regions (i.e., the pn junction interface) can be determined, for example, by SCM or SIMS. The distribution of the effective concentration of mass carriers in the current diffusion region can be determined, for example, by the distribution of the thickness of the depletion layer formed by the pn junction of the current diffusion region and the bulk region, even without measuring the effective concentration. The thickness of the depletion layer can be determined, for example, by SCM or SIMS.

[0146] The embodiments have been described in detail above, but are not limited to specific embodiments. Various modifications and alterations can be made within the scope of the claims.

[0147] Symbol Explanation

[0148] 1 First Main Face

[0149] 2 Second Main Face

[0150] 3. Side view

[0151] 4 bottom

[0152] 5. 5A Gate Trench

[0153] 10 Silicon carbide substrate

[0154] 11 Drift Zone

[0155] 11C Third District

[0156] 11D Fourth District

[0157] 11E Fifth District

[0158] 12 body areas

[0159] 13 source regions

[0160] 16 Electric field relaxation region

[0161] 17 Connection Area

[0162] 18 Contact Area

[0163] 18A First District

[0164] 18B Second District

[0165] 21 First epitaxial layer

[0166] 22 Second epitaxial layer

[0167] 40 Silicon carbide epitaxial layer

[0168] 50 Silicon carbide single crystal substrate

[0169] 60 source electrodes

[0170] 61 Contact Electrode

[0171] 62 Source wiring

[0172] 70 Drain electrode

[0173] 81 Gate insulating film

[0174] 82 gate electrode

[0175] 83 interlayer insulating film

[0176] 84 Barrier Metal Film

[0177] 85 Passivation film

[0178] Contact holes 90, 91, and 92

[0179] 100, 110, 120, 140, 150 Silicon carbide semiconductor devices (MOSFETs)

[0180] Wp1 First Size

[0181] Wp2 Second Size

[0182] Wn Third Size

[0183] Wch and

[0184] θ1 Angle

Claims

1. A silicon carbide semiconductor device, wherein, The silicon carbide semiconductor device has a silicon carbide substrate, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: A drift region having a first conductivity type; A body region, wherein the body region is disposed on the drift region and has a second conductivity type different from the first conductivity type; A source region is disposed on the body region such that it is separated from the drift region, and has the first conductivity type; and A contact area is disposed on the body region and has the second conductivity type. A gate trench is provided on the first main surface. The gate trench is defined by a side surface that extends through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extends in a first direction parallel to the first main surface. The silicon carbide semiconductor device further includes a source electrode connected to the source region and the contact region. The silicon carbide substrate also has: An electric field relaxation region is disposed between the bottom surface and the second main surface, extends in the first direction, and has the second conductivity type; and A connection region electrically connects the contact region to the electric field relaxation region, and has the second conductivity type. When viewed from a direction perpendicular to the first main surface The gate trench and the electric field relaxation region are located on an imaginary straight line extending in the first direction, and The connection region contacts the electric field relaxation region along the imaginary straight line. The connection area does not contact the side of the end of the gate trench in the first direction.

2. The silicon carbide semiconductor device as claimed in claim 1, wherein, The plurality of gate trenches are arranged at certain intervals, overlapping the imaginary straight line. When viewed from a direction perpendicular to the first main surface, the connection area is disposed between adjacent gate trenches in the first direction.

3. A silicon carbide semiconductor device, wherein, The silicon carbide semiconductor device has a silicon carbide substrate, the silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has: A drift region having a first conductivity type; A body region, wherein the body region is disposed on the drift region and has a second conductivity type different from the first conductivity type; A source region is disposed on the body region such that it is separated from the drift region, and has the first conductivity type; and A contact area is disposed on the body region and has the second conductivity type. A gate trench is provided on the first main surface. The gate trench is defined by a side surface that extends through the source region and the body region to the drift region and a bottom surface connected to the side surface, and extends in a first direction parallel to the first main surface. The silicon carbide semiconductor device further includes a source electrode connected to the source region and the contact region. The silicon carbide substrate also has: An electric field relaxation region is disposed between the bottom surface and the second main surface, extends in the first direction, and has the second conductivity type; and A connection region electrically connects the contact region to the electric field relaxation region, and has the second conductivity type. When viewed from a direction perpendicular to the first main surface The gate trench and the electric field relaxation region are located on an imaginary straight line extending in the first direction, and The connection region contacts the electric field relaxation region along the imaginary straight line. Multiple gate trenches are arranged at certain intervals, overlapping the imaginary straight line. When viewed from a direction perpendicular to the first main surface, the connection region is positioned between adjacent gate trenches in the first direction. A gate insulating film, wherein the gate insulating film is in contact with the side surface and the bottom surface; A gate electrode, wherein the gate electrode is disposed on the gate insulating film such that the gate insulating film is sandwiched between the gate electrode and the silicon carbide substrate; and An interlayer insulating film, wherein the interlayer insulating film is configured to cover the gate electrode. When viewed from a direction perpendicular to the first main surface The contact area has: A first region is configured to be spaced apart from the interlayer insulating film in a second direction perpendicular to the first direction; and The second region is disposed between adjacent gate trenches in the first direction. The source electrode is connected to the first region, and The first dimension of the first region in the first direction is greater than the second dimension of the second region in the first direction.

4. The silicon carbide semiconductor device as claimed in claim 3, wherein, The first dimension is greater than 1 and less than 6 times the second dimension.

5. The silicon carbide semiconductor device as claimed in claim 3 or claim 4, wherein, The source region and the first region are alternately arranged in the first direction, and The first dimension is larger than the third dimension of the source region in the first direction.

6. The silicon carbide semiconductor device as claimed in claim 3 or claim 4, wherein, The source region and the first region are alternately arranged in the first direction, and The first dimension is more than 0.2 times and less than 0.6 times the sum of the first dimension and the third dimension of the source region in the first direction.

7. The silicon carbide semiconductor device as claimed in claim 3 or claim 4, wherein, The second region is exposed from the interlayer insulating film, and The source electrode is also connected to the second region.

8. The silicon carbide semiconductor device as claimed in claim 3 or claim 4, wherein, The contact area has the first region on both sides of the gate trench in the second direction.

9. The silicon carbide semiconductor device as claimed in claim 3 or claim 4, wherein, The contact area has the first region on only one side of the gate trench in the second direction.

10. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The first effective concentration of impurities of the second conductivity type in the contact area is higher than the second effective concentration of impurities of the second conductivity type in the connection area.

11. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein, The sidewalls of the gate trench include {0-33-8} surfaces.

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