A chip operating current measurement system

Abstract

The present invention provides a chip operating current measurement system, comprising: a sampling resistor circuit including multiple sampling resistor branches; a voltage and current sampling module pre-configured with a sampling current threshold and having multiple amplifier gears; a current measurement module comprising: a storage unit for storing multiple sampling gears and a derivation array associated with each sampling gear; a gear optimization unit for selecting a sampling gear as an initial gear, controlling the voltage and current sampling module to collect an initial current at the initial gear, and selecting a sampling gear as an adaptive sampling gear; and a first control unit for controlling the voltage and current sampling module to collect an operating current at the adaptive sampling gear as an operating current measurement result. The beneficial effect is that the system selects an adaptive sampling gear based on the initial current collected at the sampling gear corresponding to the maximum current range and the derivation array, and calibrates the system through a calibration current coefficient, thereby making the operating current measurement result more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of chip operating current measurement, and in particular to a chip operating current measurement system. Background Art

[0002] Electrical performance testing is required during chip proofing, small batch or batch sampling, such as the operating current in different operating modes, the operating current at different voltages, the operating current at different temperatures, etc. In all of the above cases, the chip operating current range varies widely, from tens of nA to hundreds of mA.

[0003] The current chip current testing method requires manual adjustment of the current gear and cannot communicate with the control module, so it cannot automatically record current data. Although the use of precise current measuring instruments can meet the test requirements, current measuring instruments are bulky and expensive, and the test environment is relatively complicated to set up. It is also difficult to measure the working current of multiple chips simultaneously. Summary of the Invention

[0004] In view of the problems existing in the prior art, the present invention provides a chip operating current measurement system, comprising:

[0005] a sampling resistor circuit connected to a chip under test, wherein the sampling resistor circuit comprises a plurality of sampling resistor branches arranged in parallel;

[0006] a voltage and current sampling module connected to the sampling resistor circuit, wherein the voltage and current sampling module is pre-configured with a sampling current threshold and has a plurality of amplifier gears;

[0007] A current measurement module, connected to the sampling resistor circuit and the voltage and current sampling module, comprising:

[0008] a storage unit, configured to store a plurality of pre-configured sampling gears obtained according to combinations of the sampling resistor branches and the amplifier gears, and a derivation array associated with each sampling gear;

[0009] a gear optimization unit connected to the storage unit, configured to select one of the sampling gears as an initial gear, control the voltage and current sampling module and the sampling resistor circuit to collect an initial current of the chip under test at the initial gear, and perform gear optimization based on the initial current and the derivation array to select one of the sampling gears as an adapted sampling gear;

[0010] A first control unit is connected to the gear optimization unit and is used to control the voltage and current sampling module and the sampling resistor circuit to collect a working current of the chip under test at the adapted sampling gear as the working current measurement result of the chip under test.

[0011] Preferably, the gear optimization unit includes:

[0012] a storage subunit, configured to store a sampling current range corresponding to each sampling gear;

[0013] a first control subunit, connected to the storage subunit, configured to select the sampling gear corresponding to the sampling current range having the maximum upper limit value among the sampling current ranges as the initial gear, control the conduction of the sampling resistor branch corresponding to the initial gear, and switch the voltage and current sampling module to the corresponding amplifier gear, so as to collect the initial current of the chip under test in the initial gear and the amplifier gear;

[0014] a first processing subunit, connected to the first control subunit, configured to use the initial gear as an adaptive sampling gear when the initial current is less than the sampling current threshold; and

[0015] When the initial current is not less than the sampling current threshold, an analog current corresponding to each of the remaining sampling gears is inferred according to the initial current and the derivation array;

[0016] A second processing subunit, connected to the first processing subunit, is used to obtain multiple differences based on each of the analog currents and the sampling current threshold value and eliminate the differences that are not less than 0 to obtain multiple valid differences, and use the sampling gear corresponding to the maximum valid difference among the valid differences as the adaptive sampling gear.

[0017] Preferably, the plurality of sampling resistor branches arranged in parallel include a first sampling resistor branch, a second sampling resistor branch and a third sampling resistor branch;

[0018] The first sampling resistor branch includes:

[0019] a first sampling resistor, one end of which is connected to the drain of a first field effect transistor;

[0020] The gate of the first field effect transistor is connected to the current measurement module;

[0021] The second sampling resistor branch includes:

[0022] a second sampling resistor, one end of the second sampling resistor being connected to the drain of a second field effect transistor, and the other end of the second sampling resistor being connected to the other end of the first sampling resistor;

[0023] The source of the second field effect transistor is connected to the source of the first field effect transistor, and the gate of the second field effect transistor is connected to the current measurement module;

[0024] The third sampling resistor branch includes:

[0025] a third sampling resistor, one end of the third sampling resistor being connected to the drain of a third field effect transistor, and the other end of the third sampling resistor being connected to the other end of the third sampling resistor;

[0026] The source of the third field effect transistor is connected to the source of the second field effect transistor, and the gate of the third field effect transistor is connected to the current measurement module.

[0027] Preferably, the storage unit is further used to store a current calibration parameter corresponding to each sampling resistor branch obtained by pre-measurement;

[0028] The current measurement module also includes a second control unit, which is respectively connected to the storage unit and the first control unit, and is used to obtain the corresponding current calibration parameter according to the sampling resistor branch matching corresponding to the adaptive sampling gear, and calibrate the working current according to the current calibration parameter to obtain the actual current, and use the actual current as the working current measurement result of the chip under test.

[0029] Preferably, it further comprises a calibration resistance circuit, connected to the current measurement module and the sampling resistance circuit respectively, and the calibration resistance circuit comprises a plurality of calibration resistance branches;

[0030] The current measurement module includes a third control unit, which is used to control the disconnection of the chip under test, and for each sampling resistor branch, control the corresponding calibration resistor branch to be turned on, and then control the voltage and current sampling module to collect a test voltage and a test current of the sampling resistor branch, and obtain the current calibration parameter corresponding to the sampling resistor branch based on the test voltage and the test current.

[0031] Preferably, the plurality of calibration resistor branches include a first calibration resistor branch, a second calibration resistor branch and a third calibration resistor branch;

[0032] The first calibration resistance branch comprises:

[0033] a first calibration resistor, one end of the first calibration resistor being connected to the source of a fourth field effect transistor, and the other end of the first calibration resistor being grounded;

[0034] The gate of the fourth field effect transistor is connected to the current measurement module;

[0035] The second calibration resistance branch includes:

[0036] a second calibration resistor, one end of the second calibration resistor being connected to the source of a fifth field effect transistor, and the other end of the second calibration resistor being grounded;

[0037] The drain of the fifth field effect transistor is connected to the drain of the fourth field effect transistor, and the gate of the fifth field effect transistor is connected to the current measurement module;

[0038] The third calibration resistance branch comprises:

[0039] a third calibration resistor, one end of which is connected to the source of a sixth field effect transistor, and the other end of which is grounded;

[0040] The drain of the sixth field effect transistor is connected to the drain of the fifth field effect transistor, and the gate of the sixth field effect transistor is connected to the current measurement module.

[0041] Preferably, the current calibration coefficient is calculated by the following calculation formula:

[0042]

[0043] in,

[0044] CalFactor represents the current calibration factor;

[0045] Vbus represents the test voltage;

[0046] R represents the resistance value of the calibration resistor;

[0047] Ishunt represents the test current.

[0048] Preferably, the sampling resistor circuit further includes a seventh field effect transistor, the drain of the seventh field effect transistor is connected to the other end of the first sampling resistor, the source of the seventh field effect transistor is connected to the source of the first field effect transistor, and the gate of the seventh field effect transistor is connected to the current measurement module.

[0049] Preferably, the voltage and current sampling module includes:

[0050] a programmable gain amplifier, wherein the programmable gain amplifier is configured with each of the amplifier gears;

[0051] An analog-to-digital converter is configured with the sampling current threshold.

[0052] The above technical solution has the following advantages or beneficial effects:

[0053] (1) This system includes multiple sampling resistor branches and a programmable gain amplifier with multiple amplifier gears, which can be combined to obtain multiple sampling gears, making the measured working current of the chip under test more accurate;

[0054] (2) The system obtains the analog current of each sampling gear according to the initial current collected at the sampling gear corresponding to the maximum current range and the derivation array, and selects the adaptive sampling gear according to the analog current and the sampling current threshold;

[0055] (3) This system flexibly conducts the sampling resistor branch and the calibration resistor branch through the current measurement module, and uploads the measurement results to the host computer in real time for summary, making the data traceable.

[0056] (4) The calibration resistor circuit in this system can be calibrated in real time under different temperatures, different operating voltages and currents. The measured operating current is calibrated to obtain the actual current through the current calibration parameters, reducing the interference of other currents and making the measurement results more accurate.

[0057] (5) This system is not limited to measuring chip operating current, but can also be used in similar application scenarios;

[0058] (6) The working current measurement scheme adopted by this system is simple, reliable and low-cost, saving the involvement of expensive instruments and is easy to implement and expand. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 The structural principle diagram of the system in the preferred embodiment of the present invention is as follows;

[0060] Figure 2 The electrical schematic diagram of the sampling resistor circuit in a preferred embodiment of the present invention;

[0061] Figure 3 This is an electrical schematic diagram of a calibration resistor circuit in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0062] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The present invention is not limited to this embodiment, and other embodiments may also fall within the scope of the present invention as long as they conform to the gist of the present invention.

[0063] In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a chip operating current measurement system is provided. Figure 1 As shown, including:

[0064] A sampling resistor circuit 1 is connected to a chip under test 2, and the sampling resistor circuit 1 includes a plurality of sampling resistor branches arranged in parallel;

[0065] A voltage and current sampling module 3 is connected to the sampling resistor circuit 1. The voltage and current sampling module 3 is pre-configured with a sampling current threshold and has multiple amplifier gears;

[0066] A current measurement module 4, connected to the sampling resistor circuit 1 and the voltage and current sampling module 3, includes:

[0067] A storage unit 41, for storing a plurality of pre-configured sampling gears obtained according to the combination of each sampling resistor branch and each amplifier gear, and a derivation array associated with each sampling gear;

[0068] a gear optimization unit 42 connected to the storage unit 41, configured to select a sampling gear as an initial gear, control the voltage and current sampling module 3 and the sampling resistor circuit 1 to collect an initial current of the chip under test 2 at the initial gear, and perform gear optimization based on the initial current and the derivation array to select a sampling gear as an adapted sampling gear;

[0069] A first control unit 43 is connected to the gear optimization unit 42 and is used to control the voltage and current sampling module 3 and the sampling resistor circuit 1 to collect an operating current of the chip under test 2 at the adapted sampling gear as the operating current measurement result of the chip under test 2 .

[0070] In a preferred embodiment of the present invention, the gear optimization unit 42 includes:

[0071] A storage subunit 421, for storing a sampling current range corresponding to each sampling gear;

[0072] a first control subunit 422, connected to the storage subunit 421, configured to select a sampling gear corresponding to a sampling current range having a maximum upper limit value among the sampling current ranges as an initial gear, control the conduction of the sampling resistor branch corresponding to the initial gear, and switch the voltage and current sampling module 3 to the corresponding amplifier gear, thereby collecting the initial current of the chip under test 2 in the initial gear and the amplifier gear;

[0073] a first processing subunit 423 connected to the first control subunit 422, configured to use the initial gear as the adaptive sampling gear when the initial current is less than the sampling current threshold; and

[0074] When the initial current is not less than the sampling current threshold, an analog current corresponding to each of the remaining sampling gears is inferred based on the initial current and the derivation array;

[0075] A second processing sub-unit 424 is connected to the first processing sub-unit 423, and is used to obtain multiple differences based on each analog current and the sampling current threshold and eliminate the differences that are not less than 0 to obtain multiple valid differences, and use the sampling gear corresponding to the maximum valid difference among the valid differences as the adaptive sampling gear.

[0076] Specifically, in this embodiment, the sampling current threshold is subtracted from each analog current to obtain the corresponding difference. Since some analog currents are greater than the sampling current threshold and some analog currents are less than the sampling current resistance, the difference has positive and negative numbers. Since the analog current cannot be greater than the sampling current threshold, the positive numbers in the difference are cleared and the negative numbers are used as the valid difference.

[0077] In a preferred embodiment of the present invention, Figure 2 As shown, the plurality of sampling resistor branches arranged in parallel include a first sampling resistor branch 11, a second sampling resistor branch 12 and a third sampling resistor branch 13;

[0078] The first sampling resistor branch 11 includes:

[0079] a first sampling resistor R1, one end of the first sampling resistor R1 is connected to the drain of a first field effect transistor Q1;

[0080] The gate of the first field effect transistor Q1 is connected to the current measurement module 4;

[0081] The second sampling resistor branch 12 includes:

[0082] a second sampling resistor R2, one end of the second sampling resistor R2 is connected to the drain of a second field effect transistor Q2, and the other end of the second sampling resistor R2 is connected to the other end of the first sampling resistor R1;

[0083] The source of the second field effect transistor Q2 is connected to the source of the first field effect transistor Q1 , and the gate of the second field effect transistor Q2 is connected to the current measurement module 4 ;

[0084] The third sampling resistor branch 13 includes:

[0085] a third sampling resistor R3, one end of the third sampling resistor R3 is connected to the drain of a third field effect transistor Q3, and the other end of the third sampling resistor R3 is connected to the other end of the third sampling resistor R3;

[0086] The source of the third field effect transistor Q3 is connected to the source of the second field effect transistor Q2 , and the gate of the third field effect transistor Q3 is connected to the current measurement module 4 .

[0087] Specifically, in this embodiment, the resistance of the first sampling resistor R1 is 1.2 ohms, the resistance of the second sampling resistor R2 is 510 ohms, and the resistance of the third sampling resistor R3 is 5.1K ohms.

[0088] In a preferred embodiment of the present invention, the storage unit 41 is further used to store a current calibration parameter corresponding to each sampling resistor branch obtained in advance;

[0089] The current measurement module 4 also includes a second control unit 44, which is respectively connected to the storage unit 41 and the first control unit 43, and is used to obtain corresponding current calibration parameters according to the sampling resistor branch corresponding to the adaptive sampling gear and calibrate the working current according to the current calibration parameters to obtain the actual current, and use the actual current as the working current measurement result of the chip under test 2.

[0090] In a preferred embodiment of the present invention, a calibration resistor circuit 5 is further included, connected to the current measurement module 4 and the sampling resistor circuit 1 respectively, and the calibration resistor circuit 5 includes multiple calibration resistor branches;

[0091] The current measurement module includes a third control unit 45, which is used to control the chip under test 2 to be disconnected, and for each sampling resistor branch, control the corresponding calibration resistor branch to be turned on, and then control the voltage and current sampling module 3 to collect a test voltage and a test current of the sampling resistor branch, and obtain the current calibration parameters corresponding to the sampling resistor branch based on the test voltage and test current.

[0092] In a preferred embodiment of the present invention, Figure 3 As shown, the multiple calibration resistor branches include a first calibration resistor branch 51, a second calibration resistor branch 52 and a third calibration resistor branch 53;

[0093] The first calibration resistor branch 51 includes:

[0094] a first calibration resistor R4, one end of the first calibration resistor R4 is connected to the source of a fourth field effect transistor Q4, and the other end of the first calibration resistor R4 is grounded;

[0095] The gate of the fourth field effect transistor Q4 is connected to the current measurement module 4;

[0096] The second calibration resistor branch 52 includes:

[0097] a second calibration resistor R5, one end of the second calibration resistor R5 is connected to the source of a fifth field effect transistor Q5, and the other end of the second calibration resistor R5 is grounded;

[0098] The drain of the fifth field effect transistor Q5 is connected to the drain of the fourth field effect transistor Q4, and the gate of the fifth field effect transistor Q5 is connected to the current measurement module 4;

[0099] The third calibration resistor branch 53 includes:

[0100] a third calibration resistor R6, one end of the third calibration resistor R6 is connected to the source of a sixth field effect transistor Q6, and the other end of the third calibration resistor R6 is grounded;

[0101] The drain of the sixth field effect transistor Q6 is connected to the drain of the fifth field effect transistor Q5 , and the gate of the sixth field effect transistor Q6 is connected to the current measurement module 4 .

[0102] Specifically, in this embodiment, the resistance of the first calibration resistor R4 is 200 ohms, the resistance of the second calibration resistor R5 is 18k ohms, and the resistance of the third calibration resistor R6 is 1M ohms.

[0103] Preferably, if the first FET Q1 is to be turned on, the gate of the first FET Q1 is set low, and the second FET Q2, the third FET Q3, the fourth FET Q4, the fifth FET Q5, the sixth FET Q6 and the seventh FET Q7 are processed in the same manner.

[0104] Preferably, the calibration resistance circuit of the system can be calibrated in real time under different temperatures, different voltages and currents, etc.

[0105] In a preferred embodiment of the present invention, the current calibration coefficient is calculated by the following formula:

[0106]

[0107] in,

[0108] CalFactor represents the current calibration factor;

[0109] Vbus represents the test voltage;

[0110] R represents the resistance value of the calibration resistor;

[0111] Ishunt test current.

[0112] Specifically, in this embodiment, the second control unit 44 selects the first current calibration coefficient, the second current calibration coefficient, or the third current calibration coefficient according to the adaptive sampling gear to calibrate the working current to obtain the actual current.

[0113] Specifically, in this embodiment, the voltage and current sampling module 3 collects the test voltage and test current, and the test current includes the load current and the offset current. The load current is calculated by the following calculation formula:

[0114]

[0115] in,

[0116] Iload represents the load current;

[0117] Vbus represents the test voltage;

[0118] R is the resistance of the calibration resistor.

[0119] Preferably, the offset current is calculated using the following formula:

[0120] Ioffset=Ishunt-Iload

[0121] in,

[0122] Ioffset represents the offset current;

[0123] Ishunt represents the test current;

[0124] Iload represents the load current.

[0125] Preferably, when calibrating using the current calibration coefficient, the actual current is obtained by the following calculation formula:

[0126] Iload′=Ishunt*CalFactor-Ioffset

[0127] in,

[0128] Iload′ represents the actual current;

[0129] Ishunt represents the test current;

[0130] CalFactor represents the current calibration factor;

[0131] Ioffset represents the offset current.

[0132] Specifically, in this embodiment, the third control unit 45 controls the conduction of the first sampling resistor branch 11 and the first calibration resistor branch 51, and then controls the voltage and current sampling module 3 to collect the first test voltage and the first test current of the first sampling resistor branch 11, and obtains the first current calibration parameter corresponding to the first sampling resistor branch 11 based on the first test voltage and the first test current.

[0133] Preferably, at this time, the third control unit 45 only needs to control the first FET Q1 and the fourth FET Q4 to be turned on, and control the second FET Q2, the third FET Q3, the fifth FET Q5 and the sixth FET Q6 to be turned off.

[0134] Specifically, in this embodiment, the third control unit 45 controls the conduction of the second sampling resistor branch 12 and the second calibration resistor branch 52, and then controls the voltage and current sampling module 3 to collect the second test voltage and the second test current of the second sampling resistor branch 12, and obtains the second current calibration parameter corresponding to the second sampling resistor branch 12 according to the second test voltage and the second test current.

[0135] Preferably, at this time, the third control unit 45 only needs to control the second FET Q2 and the fifth FET Q5 to be turned on, and control the first FET Q1, the third FET Q3, the fourth FET Q4 and the sixth FET Q6 to be turned off.

[0136] Specifically, in this embodiment, the third control unit 45 controls the conduction of the third sampling resistor branch 13 and the third calibration resistor branch 53, and then controls the voltage and current sampling module 3 to collect the third test voltage and the third test current of the third sampling resistor branch 13, and obtains the third current calibration parameter corresponding to the third sampling resistor branch 13 based on the third test voltage and the third test current.

[0137] Preferably, at this time, the third control unit 45 only needs to control the third FET Q3 and the sixth FET Q6 to be turned on, and control the first FET Q1 , the second FET Q2 , the fourth FET Q4 and the fifth FET Q5 to be turned off.

[0138] Preferably, the second control unit 44 obtains the first current calibration parameter, the second current calibration parameter, or the third current calibration parameter according to the sampling resistor branch matching corresponding to the adaptive sampling gear to calibrate the working current to obtain the actual current.

[0139] In a preferred embodiment of the present invention, the sampling resistor circuit 1 further includes a seventh field-effect transistor Q7 , wherein the drain of the seventh field-effect transistor Q7 is connected to the other end of the first sampling resistor R1 , the source of the seventh field-effect transistor Q7 is connected to the source of the first field-effect transistor Q1 , and the gate of the seventh field-effect transistor Q7 is connected to the current measurement module 4 .

[0140] Specifically, in this embodiment, the first FET Q1 , the second FET Q2 , the third FET Q3 , the fourth FET Q4 , the fifth FET Q5 , the sixth FET Q6 and the seventh FET Q7 are individually controlled on and off by the current measurement module 4 .

[0141] Preferably, the seventh field effect transistor Q7 can be used to protect the circuit.

[0142] Specifically, in this embodiment, the sampling resistor circuit 1 further includes a seventh resistor R7 , but the resistance of the seventh resistor R7 is 0.

[0143] In a preferred embodiment of the present invention, the voltage and current sampling module 3 includes:

[0144] A programmable gain amplifier 31, wherein the programmable gain amplifier 31 is configured with various amplifier gears;

[0145] An analog-to-digital converter 32 is configured with a sampling threshold.

[0146] Specifically, in this embodiment, the programmable gain amplifier 31 is provided with four amplifier gears, and the storage unit 41 stores twelve sampling gears obtained by combining the four amplifier gears of the programmable gain amplifier 31 and the first sampling resistor R1, the second sampling resistor R2, and the third sampling resistor R3. Each sampling gear has a corresponding sampling current range. The sampling gears are arranged in descending order according to the size of the sampling current range corresponding to each sampling gear and are numbered from 0 to 11, and the sampling gear numbered 0 is used as the initial gear.

[0147] Specifically, in this embodiment, the analog currents of the remaining sampling gears are estimated by the derivation array and the initial current. The expression of the derivation array is as follows:

[0148] float InferRatio[CURRENT_STALL_NUM]={1,2,2,2,53.125,2,2,2,1.25,2,2,2}

[0149] Among them, each parameter in the derivation array corresponds to the analog current multiple between each sampling gear. In actual operation, it is necessary to measure the current corresponding ADC (analog to digital converter) value of the initial current at the initial gear and deduce it according to the derivation array. For example, when the current corresponding ADC value measured at the sampling gear numbered 0 is 1200, the current corresponding ADC value of the sampling gear numbered 1 can be deduced to be 2400 according to the derivation array, and the current corresponding ADC value of the sampling gear numbered 2 is 4800 (the current corresponding ADC value >4000 is over-range), and so on until the current corresponding ADC value of the sampling gear numbered 11 is deduced. However, since the current corresponding ADC value of the sampling gear numbered 2 has exceeded the range, the sampling gears numbered 2-11 cannot be switched.

[0150] Preferably, the ADC value corresponding to the current measured at each sampling gear for the same current is different, and therefore needs to be deduced based on the deduction array.

[0151] Preferably, in theory, only the current value of the initial gear needs to be collected to deduce the analog current corresponding to each other sampling gear. However, in actual operation, the analog current needs to be derived when switching to each sampling gear to ensure that the analog current of the next sampling gear does not exceed the sampling current threshold, thereby ensuring that the sampling gear will not be over-adjusted.

[0152] Specifically, in this embodiment, the voltage and current sampling module 3 uses the INA219 chip, which has a programmable gain amplifier 31 and an analog-to-digital converter 32. The amplifier gears of the programmable gain amplifier 31 are 1, 2, 4, and 8, respectively, and a 12-bit analog-to-digital converter 32 is used. The sampling current threshold corresponding to the INA219 chip is approximately 4000.

[0153] Preferably, if the chip used by the voltage and current sampling module 3 is changed, the value of the sampling current threshold will also change accordingly.

[0154] Preferably, the sizes of the three sampling resistors are 1.2 ohms, 510 ohms, and 5.1K ohms, respectively, wherein the 1.2 ohm sampling resistor corresponds to sampling gears numbered 0, 1, 2, and 3, the 510 ohm sampling resistor corresponds to sampling gears numbered 4, 5, 6, and 7, and the 5.1K ohm corresponds to sampling gears numbered 8, 9, 10, and 11. After the initial current is collected at sampling gear numbered 0, it is first determined whether the initial current is greater than 4000. If it is not greater than 4000, the initial gear is used as the adaptive sampling gear. If it is greater than 4000, the analog currents of sampling gears numbered 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 are calculated based on the initial current and the derivation array, and the sampling gear corresponding to the analog current closest to the sampling current threshold is used as the adaptive sampling gear, wherein the analog current corresponding to the adaptive sampling gear must be less than the sampling current threshold.

[0155] Preferably, when actually switching the sampling gear, first switch the resistance gear corresponding to the sampling resistor for coarse adjustment, and then switch the amplifier gear for fine adjustment. However, there are only three resistance gears. Therefore, before switching the resistance gear, it is necessary to determine whether the number of the sampling gear to be switched is less than 8. If the number is less than 8, fine adjustment is performed in the first two resistance gears. If the number is not less than 8, fine adjustment is performed in the third resistance gear. Number 8 represents the last resistance gear, and the resistance gear cannot be switched backward.

[0156] Preferably, if there are four sampling resistors, it is necessary to determine whether the number of the sampling gear to be switched is less than 12 before switching the resistance gear, and so on.

[0157] In a preferred embodiment of the present invention, a voltage follower circuit 6 is further included, which is connected to the sampling resistor circuit 1 and the voltage and current acquisition module 3 respectively, and is used to cooperate with the voltage and current acquisition module 3 to collect the initial current or working current of the chip under test 2.

[0158] The above description is only a preferred embodiment of the present invention and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A chip operating current measurement system, characterized in that: include: a sampling resistor circuit connected to a chip under test, wherein the sampling resistor circuit comprises a plurality of sampling resistor branches arranged in parallel; a voltage and current sampling module connected to the sampling resistor circuit, wherein the voltage and current sampling module is pre-configured with a sampling current threshold and has a plurality of amplifier gears; A current measurement module, connected to the sampling resistor circuit and the voltage and current sampling module, comprising: a storage unit, configured to store a plurality of pre-configured sampling gears obtained according to combinations of the sampling resistor branches and the amplifier gears, and a derivation array associated with each sampling gear; a gear optimization unit connected to the storage unit, configured to select one of the sampling gears as an initial gear, control the voltage and current sampling module and the sampling resistor circuit to collect an initial current of the chip under test at the initial gear, and perform gear optimization based on the initial current and the derivation array to select one of the sampling gears as an adapted sampling gear; a first control unit, connected to the gear optimization unit, configured to control the voltage and current sampling module and the sampling resistor circuit to collect an operating current of the chip under test at the adapted sampling gear as a working current measurement result of the chip under test; The gear optimization unit includes: a storage subunit, configured to store a sampling current range corresponding to each sampling gear; a first control subunit, connected to the storage subunit, configured to select the sampling gear corresponding to the sampling current range having the maximum upper limit value among the sampling current ranges as the initial gear, control the conduction of the sampling resistor branch corresponding to the initial gear, and switch the voltage and current sampling module to the corresponding amplifier gear, so as to collect the initial current of the chip under test in the initial gear and the amplifier gear; a first processing subunit, connected to the first control subunit, configured to use the initial gear as an adaptive sampling gear when the initial current is less than the sampling current threshold; and When the initial current is not less than the sampling current threshold, an analog current corresponding to each of the remaining sampling gears is inferred according to the initial current and the derivation array; a second processing subunit, connected to the first processing subunit, configured to obtain a plurality of differences according to the analog currents and the sampled current thresholds, eliminate the differences that are not less than 0, obtain a plurality of valid differences, and use the sampling gear corresponding to the maximum valid difference among the valid differences as the adapted sampling gear; Each parameter in the derivation array corresponds to a multiple of the analog current between each of the sampling gears.

2. The chip operating current measurement system according to claim 1, characterized in that: The plurality of sampling resistor branches arranged in parallel include a first sampling resistor branch, a second sampling resistor branch and a third sampling resistor branch; The first sampling resistor branch includes: a first sampling resistor, one end of which is connected to the drain of a first field effect transistor; The gate of the first field effect transistor is connected to the current measurement module; The second sampling resistor branch includes: a second sampling resistor, one end of the second sampling resistor being connected to the drain of a second field effect transistor, and the other end of the second sampling resistor being connected to the other end of the first sampling resistor; The source of the second field effect transistor is connected to the source of the first field effect transistor, and the gate of the second field effect transistor is connected to the current measurement module; The third sampling resistor branch includes: a third sampling resistor, one end of the third sampling resistor being connected to the drain of a third field effect transistor, and the other end of the third sampling resistor being connected to the other end of the third sampling resistor; The source of the third field effect transistor is connected to the source of the second field effect transistor, and the gate of the third field effect transistor is connected to the current measurement module.

3. The chip operating current measurement system according to claim 1, characterized in that: The storage unit is further used to store a current calibration parameter corresponding to each sampling resistor branch obtained by pre-measurement; The current measurement module also includes a second control unit, which is respectively connected to the storage unit and the first control unit, and is used to obtain the corresponding current calibration parameter according to the sampling resistor branch matching corresponding to the adaptive sampling gear, and calibrate the working current according to the current calibration parameter to obtain the actual current, and use the actual current as the working current measurement result of the chip under test.

4. The chip operating current measurement system according to claim 3, characterized in that: It also includes a calibration resistance circuit, connected to the current measurement module and the sampling resistance circuit respectively, and the calibration resistance circuit includes multiple calibration resistance branches; The current measurement module includes a third control unit, which is used to control the disconnection of the chip under test, and for each sampling resistor branch, control the corresponding calibration resistor branch to be turned on, and then control the voltage and current sampling module to collect a test voltage and a test current of the sampling resistor branch, and obtain the current calibration parameter corresponding to the sampling resistor branch based on the test voltage and the test current.

5. The chip operating current measurement system according to claim 4, characterized in that: The plurality of calibration resistance branches include a first calibration resistance branch, a second calibration resistance branch and a third calibration resistance branch; The first calibration resistance branch comprises: a first calibration resistor, one end of the first calibration resistor being connected to the source of a fourth field effect transistor, and the other end of the first calibration resistor being grounded; The gate of the fourth field effect transistor is connected to the current measurement module; The second calibration resistance branch includes: a second calibration resistor, one end of the second calibration resistor being connected to the source of a fifth field effect transistor, and the other end of the second calibration resistor being grounded; The drain of the fifth field effect transistor is connected to the drain of the fourth field effect transistor, and the gate of the fifth field effect transistor is connected to the current measurement module; The third calibration resistance branch comprises: a third calibration resistor, one end of the third calibration resistor being connected to the source of a sixth field effect transistor, and the other end of the third calibration resistor being grounded; The drain of the sixth field effect transistor is connected to the drain of the fifth field effect transistor, and the gate of the sixth field effect transistor is connected to the current measurement module.

6. The chip operating current measurement system according to claim 5, characterized in that: The current calibration coefficients corresponding to the first calibration resistor branch, the second calibration resistor branch, and the third calibration resistor branch are calculated using the following formula: ； in, CalFactor represents the current calibration factor; Vbus represents the test voltage; R represents the resistance value of the first calibration resistor, the second calibration resistor, or the third calibration resistor; Ishunt represents the test current.

7. The chip operating current measurement system according to claim 2, characterized in that: The sampling resistor circuit further includes a seventh field effect transistor, wherein a drain of the seventh field effect transistor is connected to the other end of the first sampling resistor, a source of the seventh field effect transistor is connected to the source of the first field effect transistor, and a gate of the seventh field effect transistor is connected to the current measurement module.

8. The chip operating current measurement system according to claim 1, characterized in that: The voltage and current sampling module includes: a programmable gain amplifier, wherein the programmable gain amplifier is configured with each of the amplifier gears; An analog-to-digital converter is configured with the sampling current threshold.

9. The chip operating current measurement system according to claim 1, characterized in that: It also includes a voltage follower circuit, which is connected to the sampling resistor circuit and the voltage and current sampling module respectively, and is used to cooperate with the voltage and current sampling module to collect the initial current or the working current of the chip under test.

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