Voltage-based block family combination for memory devices

Abstract

This application relates to voltage-based block family combinations for memory devices. An example memory subsystem includes a memory device and a processing device operably coupled to the memory device. The processing device is configured to create a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read level offsets, create a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window after the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of read level offsets, and in response to determining that a threshold criterion is satisfied, combine the first block family and the second block family.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems, and more specifically, to voltage-based block family combination for memory devices. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] According to an aspect of the present application, a system is provided. The system includes a memory device; and a processing device operably coupled to the memory device to perform operations comprising: creating a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of voltage level offsets; creating a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window after the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of voltage level offsets; and in response to determining that a threshold criterion is satisfied, combining the first block family and the second block family, wherein determining that the threshold criterion is satisfied comprises determining that a difference in voltage offset values associated with a die of the first block family and the same die of the second block family is below a voltage difference threshold for all dies of the memory device.

[0004] According to another aspect of the present application, a method is provided. The method includes creating a first block family comprising a first set of blocks that have been programmed within a first specified time window, wherein each block associated with the first block family is associated with a first set of read level offsets; creating a second block family comprising a second set of blocks that have been programmed within a second specified time window after the first specified time window, wherein each block associated with the second block family is associated with a second set of read level offsets; and in response to determining that a difference in voltage offset values associated with a die of the first block family and the same die of the second block family is below a voltage difference threshold for all dies of the memory device, combining the first block family and the second block family.

[0005] According to yet another aspect of the present application, a non-transitory computer- readable storage medium is provided. The non-transitory computer-readable storage medium comprises instructions that, when executed by a processing device operably coupled to a memory device, perform operations comprising: creating a first family of blocks comprising a first set of blocks that have been programmed within at least one of a first specified window of time or a first specified window of temperature, wherein each block associated with the first family of blocks is associated with a first set of voltage level offsets; creating a second family of blocks comprising a second set of blocks that have been programmed within at least one of a second specified window of time or a second specified window of temperature after the first specified window of time, wherein each block associated with the second family of blocks is associated with a second set of voltage level offsets; and in response to determining that a threshold criterion is satisfied, combining the first family of blocks and the second family of blocks, wherein determining that the threshold criterion is satisfied comprises determining that a difference in voltage offset values associated with a die of the first family of blocks and the same die of the second family of blocks is below a voltage difference threshold for all dies of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, of some embodiments of the present disclosure.

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the present disclosure is described.

[0008] Figure 2 A time voltage shift caused by slow charge loss exhibited by a three-tier memory cell according to some embodiments of the present disclosure is schematically illustrated.

[0009] Figure 3 An example voltage boundary table and an example voltage offset table are depicted.

[0010] Figure 4A An example plot illustrating a dependence of threshold voltage offset on post-program time (i.e., a period of time elapsed since a block has been programmed) according to some embodiments of the present disclosure is depicted.

[0011] Figure 4B A set of predefined voltage block groups according to embodiments of the present disclosure is schematically illustrated.

[0012] Figure 5 Block family management operations implemented by a block family manager component of a memory sub-system controller operated according to embodiments of the present disclosure are schematically illustrated.

[0013] Figure 6 Selecting a block family for calibration according to embodiments of the present disclosure is schematically illustrated.

[0014] Figure 7An instance of metadata maintained by a memory sub-system controller for associating blocks and / or partitions with block families according to embodiments of the present disclosure is illustratively shown.

[0015] Figure 8 A graph of time voltage shift for dies of multiple block families converging to similar values is illustratively shown.

[0016] Figure 9 A graph of time voltage shift for dies of multiple block families converging to similar values is illustratively shown.

[0017] Figure 10 An instance of combining block families based on voltage metrics for each die in the block family is illustratively shown.

[0018] Figure 11 An instance of metadata maintained by a memory sub-system controller for associating block families with die temperature is illustratively shown.

[0019] Figure 12 A flowchart of an example method 1200 of block family management implemented by a memory sub-system controller operating according to some embodiments of the present disclosure.

[0020] Figure 13 A flowchart of an example method 1300 of performing a read operation by a memory sub-system controller operating according to some embodiments of the present disclosure.

[0021] Figure 14 A flowchart of an example method 1400 of block family combining implemented by a memory sub-system controller operating according to some embodiments of the present disclosure.

[0022] Figure 15 A block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0023] Embodiments of the present disclosure relate to voltage-based block family combining for memory devices. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Embodiments of the present disclosure are described below in the context of a storage device and a memory module. Generally, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. Figure 1 Embodiments of the present disclosure relate to voltage-based block family combining for memory devices. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Embodiments of the present disclosure are described below in the context of a storage device and a memory module. Generally, a host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0024] Memory sub-systems can utilize one or more memory devices, including any combination of different types of non-volatile memory devices and / or volatile memory devices, to store data provided by a host system. In some embodiments, the non-volatile memory devices can be provided by a NAND-type flash memory device. The following description is provided below in connection with Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a group of physical blocks. Each block is composed of a group of pages. Each page is composed of a group of memory cells ("cells"). A cell is an electronic circuit that stores information.

[0025] Data operations can be performed by a memory sub-system. A data operation can be a host initiated operation. For example, a host system can initiate a data operation (e.g., a write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write commands, read commands) to the memory sub-system in order to store data on a memory device at the memory sub-system and read data from a memory device on the memory sub-system. The data to be read or written as specified by the host request is hereinafter referred to as "host data." The host request can include logical address information (e.g., logical block address (LBA), namespace) of the host data, which is a location associated with the host data by the host system. The logical address information (e.g., LBA, namespace) can be part of metadata of the host data. Metadata can also include error handling data (e.g., ECC codewords, parity codes), data version (e.g., to distinguish a lifetime of written data), valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0026] A memory device includes a plurality of memory cells, each of which can store one or more bits of information depending on the type of memory cell. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which causes the memory cell to retain a charge, allowing the voltage distribution produced by the memory cell to be modulated. Furthermore, precisely controlling the amount of charge stored by a memory cell allows a plurality of threshold voltage levels corresponding to different logical levels to be established, effectively allowing a single memory cell to store multiple bits of information: a memory cell operating with 2 n "threshold voltage" will refer herein to a voltage level that defines a boundary between two adjacent voltage distributions corresponding to two logical levels. Thus, a read operation can be performed by comparing a measured voltage exhibited by a memory cell to one or more reference voltage levels in order to distinguish between two logical levels for single-level cells and multiple logical levels for multi-level cells.

[0027] Due to a phenomenon known as slow charge loss, the threshold voltage of a memory cell changes over time as the cell's charge degrades, which is referred to as "temporal voltage shift" (as the degraded charge causes the voltage distribution to shift along the voltage axis toward lower voltage levels). The threshold voltage changes rapidly at first (immediately after the memory cell is programmed), and then slows in a generally logarithmic-linear manner relative to the time elapsed since the cell programming event. Thus, failing to mitigate temporal voltage shift caused by slow charge loss can increase the bit error rate in read operations.

[0028] However, various common implementations fail to adequately address temporal voltage shift, or employ inefficient strategies that cause high bit error rates and / or exhibit other shortcomings. Embodiments of the present disclosure address the above and other deficiencies by implementing a memory subsystem that employs a block family-based error avoidance strategy, thereby significantly improving the bit error rate exhibited by the memory subsystem.

[0029] According to embodiments of the present disclosure, temporal voltage shift is selectively tracked for programmed blocks grouped by block family, and an appropriate voltage offset based on the block's membership in a certain block family is applied to a base read level in order to perform a read operation. A "block family" will refer herein to a group of blocks that have been programmed within a specified time window and a specified temperature window. Since the time elapsed after programming and temperature are the primary factors affecting temporal voltage shift, it is presumed that all blocks and / or partitions within a single block family exhibit similar threshold voltage distributions in the memory cells, and thus the same voltage offset will need to be applied to the base read level for read operations. A "base read level" will refer herein to the initial threshold voltage level exhibited by a memory cell immediately after programming. In some implementations, the base read level can be stored in metadata of the memory device.

[0030] Block families can be created asynchronously with respect to block programming events. In an illustrative example, a new block family can be created whenever a specified period of time (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family or a change in the reference temperature of the memory cells has been greater than a specified threshold. The memory subsystem controller can maintain identifiers of active block families that are associated with one or more blocks as the blocks are programmed.

[0031] The memory subsystem controller can periodically perform a calibration process to associate each die of each block family with one of a predefined set of threshold voltage offset blocks, which in turn are associated with voltage offsets to be applied for read operations. The associations of blocks to block families and block families to dies to threshold voltage offset blocks can be stored in respective metadata tables maintained by the memory subsystem controller.

[0032] Upon receiving a read command, the memory sub-system controller can identify a block family associated with a block identified by a logical block address (LBA) specified by the read command, identify a threshold voltage offset block group associated with the block family and a die on which the block resides, calculate a new threshold voltage by superimposing a threshold voltage offset associated with the threshold voltage offset block group to a base read level, and perform the read operation using the new threshold voltage, as described in more detail herein below.

[0033] As block families age, the temporal voltage shifts of temporally adjacent block families (e.g., block families that are adjacent in block family creation order) can converge. Since the amount of space available for the metadata table maintained by the memory sub-system controller to store records associated with different block families can be limited, it can be desirable to combine multiple active block families into a single block family. In some embodiments, the memory sub-system controller can perform the combining operation by updating the block family metadata table. For example, a metadata table entry related to block family metadata associated with a first block family can be updated to additionally include records for blocks associated with a second block family. Records associated with the second block family in the block family metadata table can then be cleared and the second block family can be reused during future write operations. To determine whether to combine two block families, the memory sub-system controller can determine whether a difference in voltage offset values (measured by the voltage metric) associated with the two block families satisfies a threshold condition. For example, the threshold condition can be satisfied when the difference in voltage offset values for the two block families is less than a predetermined threshold. By combining the two block families, space in the block family metadata table is freed and the number of block families that need to be tracked and periodically calibrated is reduced.

[0034] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the disclosure include, but are not limited to, improved performance and energy consumption with less metadata, and reduced resources allocated to periodic calibration.

[0035] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such media.

[0036] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a Secure Digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0037] The computing system 100 can be a computing device, such as a desktop computer, a notebook computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked consumer device), or such computing device that includes a memory and a processing device (e.g., a processor).

[0038] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0039] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory sub-system 110, such as to write data to and read data from the memory sub-system 110.

[0040] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0041] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0042] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-gridded data access arrays. Further, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0043] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit of data per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), and a quad-level cell (QLC), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used to store data. In the case of some types of memory, such as NAND, pages can be grouped to form blocks.

[0044] Although non-volatile memory devices such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non- (NOR) flash memory, as well as electrically erasable programmable read-only memory (EEPROM).

[0045] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0046] The memory sub-system controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0047] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. Although the local memory 119 is illustrated as being included in the memory sub-system controller 115, in another embodiment of the present disclosure, the memory sub-system 110 does not include a controller 115 and can instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system). Figure 1

[0048] Generally, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., a logical block address (LBA), a name space) and a physical address (e.g., a physical block address) associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access the memory devices 130, as well as convert responses associated with the memory devices 130 into information for the host system 120.

[0049] In some implementations, the memory sub-system 110 can use a striping scheme, according to which each data payload (e.g., user data) is spread across multiple dies of the memory devices 130 (e.g., NAND-type flash memory devices) such that the payload is distributed across the subset of dies, while the remaining die(s) are used to store error correction information (e.g., parity bits). Accordingly, a set of blocks distributed across a set of dies of a memory device using a striping scheme will be referred to herein as a “superblock.”

[0050] ​The memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory devices 130.

[0051] In some embodiments, the memory devices 130 include a local media controller 135 that operates in conjunction with the memory sub-system controller 115 to perform operations on one or more memory cells of the memory devices 130. An external controller (e.g., the memory sub-system controller 115) can externally manage the memory devices 130 (e.g., perform media management operations on the memory devices 130). In some embodiments, the memory devices 130 are managed memory devices, which are raw memory devices combined with a local controller (e.g., the local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0052] The memory sub-system 110 includes a block family manager component 113 that can be used to implement a block family based error avoidance policy in accordance with embodiments of the disclosure. In some embodiments, the controller 115 includes at least a portion of the block family manager component 113. For example, the controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the block family manager component 113 is part of the host system 120, an application, or an operating system. The block family manager component 113 can manage block families associated with the memory devices 130, as described in greater detail herein below.

[0053] Figure 2 An illustration of time voltage shift caused by slow charge loss exhibited by a three-level memory cell is described in accordance with embodiments of the disclosure. While Figure 2 The illustrative example of is with a three-level cell, the same observations can be made, and thus, the same remedies can be applied to single-level cells and any memory cell having multiple levels.

[0054] A memory cell can be programmed (written to) by applying a voltage (e.g., a program voltage) to the memory cell, resulting in a charge stored by the memory cell. Precise control of the amount of charge stored by the memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. In 2 nA memory cell capable of operating at n different threshold voltage levels can store n bits of information.

[0055] Each of charts 210 and 230 illustrates a program voltage distribution 220A-N (also referred to herein as a "program distribution" or "voltage distribution" or "distribution") of memory cells programmed to encode a corresponding logic level by a respective write level (which can be assumed to be at the midpoint of the program distribution). The program distributions 220A-N can illustrate a range of threshold voltages (e.g., a normal distribution of threshold voltages) for memory cells programmed at a respective write level (e.g., program voltage). To distinguish between adjacent program distributions (corresponding to two different logic levels), a read threshold voltage level is defined (shown by the vertical dashed line) such that any measured voltage below the read threshold level is associated with one of a pair of adjacent program distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other program distribution of the pair of adjacent distributions.

[0056] In chart 210, eight states of a memory cell are shown below the corresponding program distributions (the distribution of states is not shown except for the state labeled ER, which is the erased state). Each state corresponds to a logic level. Threshold voltage levels are labeled Va to Vh. As shown, any measured voltage below Va is associated with the ER state. States labeled PI, P2, P3, P4, P5, P6, and P7 correspond to distributions 220A-N, respectively.

[0057] Time after program (TAP) will refer herein to the time elapsed since a cell has been written and is the main driver of temporal voltage shift (TVS). TAP can be estimated (e.g., inferred from data state metrics) or directly measured (e.g., from a controller clock). A cell, block, page, block family, etc. is new (or relatively new) if it has a (relatively) small TAP and old (or relatively old) if it has a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be made (e.g., reference calibration is performed 8-12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes).

[0058] As seen from example graphs 210 and 230, which reflect, respectively, a programmed time (TAP) immediately after programming and a T hour TAP (where T is the number of hours) as 0, the program distribution changes over time primarily due to slow charge loss. To reduce the read bit error rate, the corresponding read threshold voltage is adjusted to compensate for the shift in the program distribution, which is shown by the vertical dashed lines. In various embodiments of the present disclosure, the time voltage shift is tracked selectively for a die population based on measurements performed at one or more representative dies in the die population. Based on measurements of the time voltage shift and operating temperature of the dies in the die population made on representative dies in the die population, the read threshold voltage offset for reading memory cells for the dies in the die population is updated and applied to the base read threshold level to perform read operations.

[0059] Figure 3 Example voltage boundary table and example voltage offset table are depicted. Voltage boundary table 310 and voltage offset table 320 can be used to determine read level offsets that are added to base read level voltages to read data from memory cells. As the programmed time increases, the threshold voltage of the distribution of memory cells can change due to storage charge loss, as shown by the example of Figure 2 To determine the appropriate read level offset for reading a cell, a measurement of the cell can be performed to estimate the programmed time of the cell based on, for example, data state metrics such as voltage. For example, a level 7 distribution of the cell can be measured, and the difference between the measured read level (e.g., 100 millivolts) and a reference read level (e.g., 0 volts) can be determined. The difference corresponds to the programmed time of the memory cell, and can be used to identify a read level offset to be added to a base read threshold level to perform a read operation.

[0060] Voltage boundary table 310 can be used to identify a bin group that contains a read offset to be used to read data from a memory cell. The bin group to be used is the value of the bin group column for which the voltage difference (between the measured read level and the reference read level) corresponds to the voltage range shown in the boundary column. For example, if the difference is less than VI, bin group 0 will be used. If the difference is between VI and V2, bin group 1 will be used, and so on. The voltage offset table can be used to identify a read level offset to be used for the identified bin group. For example, if the bin group to be used is bin group 0, one of the offsets shown in the column labeled "bin group 0" 322 (e.g., V10, V20...V60) will be added to the base read offset level for levels 1 through 7 (and any other offsets) when reading the memory cell. "Bin group 0" 322 corresponds to a programmed time of 0 hours, as shown in Figure 2 "bin group 5" 324 corresponds to a programmed time of 24 hours, as shown in Figure 2The T hours of post-program time shown, and have a larger amount of values offset. Block group numbers less than a threshold age value can be referred to as "newer block groups," and block group numbers greater than or equal to the threshold age value can be referred to as "older block groups." For example, if the threshold age value is block group number 5, then block groups 0 through 4 can be referred to as newer block groups, and block groups 5 through 7 can be referred to as older block groups. As another example, if the threshold age value is block group number 4, then block groups 0 through 3 can be referred to as newer block groups, and block groups 4 through 7 can be referred to as older block groups.

[0061] As described above, "read level" will refer herein to a voltage position. Read levels are numbered with increasing voltage from LI to 2^(number of bits). As an example, for TLC, the read levels will be LI, L2...L7. "Read level value" will refer herein to the voltage or DAC value representing the voltage applied to the read element (typically the control gate of a NAND cell) for the purpose of reading the cell. "Read level offset" will refer herein to a component of the equation that determines the read level value. Offsets can be summed (i.e., read level value = offset_a + offset_b +...). By convention, one of the read level offsets can be referred to as the read level base. "Calibration" will refer herein to altering the read level value (possibly by adjusting the read level offsets or the read level base) to better match the ideal read level for a die or a set of reads.

[0062] As described above, "block group" (or "voltage block group" or "voltage offset block group") will refer herein to a set of read level offsets applied to a set of data. Block group offsets are read level offsets that affect the read level of a block family within a block group. In this context, block groups are generally targeted primarily for addressing TVS, but can also be targeted for other mechanisms (e.g., tempco mis-calibration). An old or older block group is a block group for which read level offsets are targeted for data written at a relatively early time. A new or newer block group is a block group for which read level offsets are targeted for data written relatively recently. Read level adjustment can be implemented through offsets or read retries or even as an adjustment to the base. Block group selection will refer herein to the process by which a memory device selects which block group to use for a given read.

[0063] Figure 4A An example plot 400 illustrating the dependence of threshold voltage offset on post-program time (i.e., the period of time elapsed since a block has been programmed) is depicted in accordance with some embodiments of the present disclosure. As Figure 4ATo illustrate, the memory device is divided into block families 430A to 430N, such that each block family contains one or more blocks that have been programmed within a specified time window and a specified temperature window. As mentioned above, since the elapsed time and temperature after programming are the main factors affecting the time voltage shift, it is presumed that all blocks and / or partitions within a single block family will exhibit similar threshold voltage distributions in the memory cells, and therefore will require the same voltage offset for read operations.

[0064] Block families can be created asynchronously relative to block programming events. In an illustrative example, whenever a specified time period (e.g., a predetermined number of minutes) has elapsed since the creation of the last block family, or whenever the change in the reference temperature of a memory cell, updated at specified time intervals, has exceeded a specified threshold since the creation of the current block family, Figure 1 The memory subsystem controller 115 can then create new block families. The memory subsystem controller can maintain identifiers for active block families, which are associated with the blocks when one or more blocks are programmed.

[0065] The newly created block family can be associated with block group 0. Then, the memory subsystem controller can periodically perform a calibration process to ensure that each die in each block family is associated with a predefined voltage block group (…). Figure 4A In the illustrative example, a block group (0 to 7) is associated with one of the block groups, which in turn is associated with a voltage offset to be applied for a read operation. The associations between blocks and block families, as well as between block families and dies and voltage block groups, can be stored in corresponding metadata tables maintained by the memory subsystem controller, such as those relating to the following... Figure 7 The metadata table described.

[0066] Figure 4B A set of predefined threshold voltage blocks is illustrated schematically according to embodiments of the present disclosure. For example... Figure 4B To illustrate, the threshold voltage offset curve 450 can be subdivided into multiple voltage block groups, such that each voltage block group corresponds to a predetermined range of threshold voltage offset. Although Figure 4B The illustrative example defines ten voltage block groups, but in other implementations, various other numbers of voltage block groups may be used (e.g., 64 block groups). The memory subsystem controller may associate each die of each block family with a voltage block group based on a periodically performed calibration process, as described in further detail below.

[0067] Figure 5 This illustration schematically depicts block family management operations performed by a block family manager component of a memory subsystem controller operating according to embodiments of the present disclosure. For example... Figure 5Illustratively, the block family manager 510 can maintain, in memory variables, an identifier 520 of the active block family, which is associated with one or more blocks of the cursor 530A-530K as they are programmed. A "cursor" will be used broadly herein to refer to a location on a memory device to which data is written.

[0068] The memory sub-system controller can track the creation time of a block family with a power-on minute (POM) clock. In some implementations, in addition to the POM clock, a less accurate clock that continues to run when the controller is in various low power states can also be utilized, such that upon the controller waking up from a low power state, the POM clock is updated based on the less accurate clock.

[0069] Accordingly, upon initialization of each block family, the current time 540 is stored in a memory variable as the block family start time 550. As the blocks are programmed, the current time 540 is compared to the block family start time 550. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next sequential integer), and the memory variable storing the block family start time 550 is updated to store the current time 540.

[0070] The block family manager 510 can also maintain two memory variables for storing high and low reference temperatures of the selected die of each memory device. Upon initialization of each block family, the high temperature 560 and low temperature 570 variables store values of the current temperature of the selected die of the memory device. In operation, while the active block family identifier 520 remains the same, temperature measurements are periodically obtained and compared to the stored high temperature 560 and low temperature 570 values, which are updated accordingly: if a temperature measurement is found to be greater than or equal to the value stored by the high temperature variable 560, the value stored by the high temperature variable 560 is updated to store the temperature measurement; conversely, if a temperature measurement is found to fall below the value stored by the low temperature variable 570, the value stored by the low temperature variable 570 is updated to store the temperature measurement.

[0071] The block family manager 510 can further periodically compute the difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is greater than or equal to a specified temperature threshold, the block family manager 510 can create a new active block family: update the memory variable storing the active block family identifier 520 to store the next block family number (e.g., the next sequential integer), update the memory variable storing the block family start time 550 to store the current time 540, and update the high temperature 560 and low temperature 570 variables to store values of the current temperature of the selected die of the memory device.

[0072] When programming a block, the memory sub-system controller associates the block with a currently active block family. The association of each block with a corresponding block family is reflected by block family metadata 580, as described below with reference to Figure 7 In more detail.

[0073] As mentioned above, based on a periodically performed calibration process, the memory sub-system controller associates each die of each block family with a set of threshold voltage offset blocks that define a set of threshold voltage offsets to be applied to a base voltage read level in order to perform read operations. The calibration process involves performing read operations with different threshold voltage offsets with respect to a specified number of randomly selected blocks within the block family being calibrated, and picking the threshold voltage offset that minimizes the error rate of the read operations.

[0074] Figure 6 Illustratively, a block family is selected for calibration in accordance with embodiments of the present disclosure. As Figure 6 Illustratively, the memory sub-system controller can limit the calibration operation to the oldest block family in each block group (e.g., block family 610 in block group 0 and block family 620 in block group 1), as it is the oldest block family to migrate to the next block group before any other block family of the current block group due to slow charge loss.

[0075] Figure 7 Illustratively, example metadata maintained by the memory sub-system controller for associating blocks and / or partitions with block families in accordance with embodiments of the present disclosure. As Figure 7 Illustratively, the memory sub-system controller can maintain a superblock table 710, a family table 720, and an offset table 730.

[0076] Each record of the superblock table 710 specifies a block family associated with a specified superblock and partition combination. In some embodiments, the superblock table record can further include a time and temperature value associated with the specified superblock and partition combination.

[0077] The family table 720 is indexed by block family number, such that each record of the family table 720 specifies, for the block family to which the record of the family table 720 refers, a set of threshold voltage offset blocks associated with the respective dies of the block family. In other words, each record of the family table 720 includes a vector, each element of which specifies a set of threshold voltage offset blocks associated with the die to which the vector element’s index refers. The sets of threshold voltage offset blocks to be associated with the block family dies can be determined by a calibration process, as described in more detail above.

[0078] Finally, the offset table 730 is indexed by block group number. Each record of the offset table 730 specifies a set of threshold voltage offsets (e.g., for TLC, MLC, and / or SLC) associated with a threshold voltage offset block.

[0079] Metadata tables 710-730 can be stored on one or more memory devices 130 Figure 1 In some implementations, at least a portion of the metadata tables can be cached in a local memory 119 of the memory sub-system controller 115 Figure 1

[0080] In operation, upon receiving a read command, the memory sub-system controller determines a physical address corresponding to a logical block address (LBA) specified by the read command. Physical address components such as a physical block number and a die identifier are used to perform a metadata table walk: first, the super-block table 710 is used to identify a block family identifier corresponding to the physical block number; next, the block family identifier is used as an index to the family table 720 in order to determine a threshold voltage offset block group associated with the block family and die; finally, the identified threshold voltage offset block group is used as an index to the offset table 730 in order to determine a threshold voltage offset corresponding to the block group. The memory sub-system controller can then superimpose the identified threshold voltage offset to a base voltage read level in order to perform the requested read operation.

[0081] In the illustrative example of Figure 7 The super-block table 710 maps partition 0 of super-block 0 to block family 4, which is used as an index to the family table 720 in order to determine that die 0 is mapped to block group 3. The latter value is used as an index to the offset table in order to determine the threshold voltage offset value for block group 3.

[0082] Figure 8 A graph illustrating the temporal voltage shifting of dies of multiple block families converging to similar values according to embodiments of the disclosure. As Figure 8 illustrated, the memory sub-system controller creates multiple block families (block family 810, block family 820, and block family 830) over time (indicated by the bottom x-axis in log scale). Upon creating a block family, each die (indicated by the diagonal line originating from the top x-axis) of each block family 810, 820, 830 is associated with a threshold voltage offset block group 0. The y-axis indicates the voltage offset of each block group. The voltage offset is expressed in DAC (digital-to-analog converter) units (e.g., DAC values), where one DAC value is equivalent to 10 millibel.

[0083] As the data in each block family 810, 820, 830 ages, the voltage offset of each die of each block family 810, 820, 830 increases. A periodic calibration procedure performed by the memory sub-system controller 115 determines whether to associate each die of the block families 810, 820, 830 with a new threshold voltage offset block group. As Figure 8 ​As seen in the middle, the voltage shifts of the dies of the block families 810, 820, 830 can converge (as shown at 840) to similar values over time. To reduce the number of calibration operations that need to be performed, the memory sub-system controller 115 can combine two block families into a single block family by updating the metadata table maintained by the memory sub-system controller 115 based on certain conditions. In the illustrative example, a first block family can include blocks 1-100 (across one or more dies), and a second block family can include blocks 101-200 (across one or more dies). By updating the super-block table 710 and the family table 720 in the illustrative example, the second block family can be combined into the first block family such that the first block family includes blocks 1-200. For example, the second block family can be unmapped from the super-block table 710 and the family table 720, and the first block family can be updated in the metadata table (not shown) to be associated with blocks 1-200. Each die associated with blocks 1-200 can be associated with an appropriate block group (e.g., in the family table 720). Thus, by combining the two block families, space in the block family table is freed, and the second block family record is recycled for future use. Figure 7

[0084] Figure 9 A graph illustrating the temporal voltage shifts of multiple block families converging in accordance with these embodiments of the disclosure is shown. Multiple block families 1-13 (indicated by the diagonal lines originating from the top x-axis and having a sequential order from left to right) are created over time (indicated by the log of the bottom x-axis). Upon creation of the block families, each die (not shown) of each block family is associated with a threshold voltage shift block group 0. The y-axis indicates the voltage shift of each block group. In the example, although a block spans multiple dies, any given block family can be a die assigned to a single block group based on selected criteria (e.g., based on the die in the block family having the largest temporal voltage shift, the die having the smallest temporal voltage shift, an average of the temporal voltage shifts of all dies in the block family, etc.).

[0085] In some embodiments, the memory sub-system controller 115 can combine two block families based on a data state metric. The data state metric is a numerical value inferred from data behavior within the memory sub-system 110 and reflects the temporal voltage shift, the degree of read disturbance, the block group to which data should be assigned, etc. For example, the memory sub-system controller 115 can first select a pair of temporally adjacent block families (e.g., block families that are adjacent in the block family creation order, such that the second block family in the pair is created immediately after the first block family in the pair is closed), such as Figure 9 ​The block family 13 and the block family 12 shown in the middle. The memory sub-system controller 115 can select a first candidate block family as the oldest (e.g., the most recently created) block family in the block family creation order (e.g., the block family 13), the newest (e.g., the most recently created) block family in the block family creation order (e.g., the block family 1), the oldest or newest block family associated with a predetermined block group (e.g., the oldest or newest block family associated with the block group 2), a random block family, etc. In response to selecting the first candidate block family, the memory sub-system controller 115 can then examine its time-adjacent block families to determine whether the difference in data state metrics between the two block families satisfies a threshold criterion.

[0086] In an example, the data state metric can be a voltage metric that indicates a measure of temporal voltage shift (e.g., voltage offset). The voltage metric can be measured in DAC (digital-to-analog converter) units, millibels, or volts. The threshold criterion can be satisfied when, for example, the difference in voltage metrics associated with a selected die of one block family and the same die of another block family is below a predefined voltage threshold for all dies of the memory sub-system 110. In an illustrative example, the memory sub-system controller 115 can select two rows (e.g., indices 1 and 2) in the block family table 720, determine the difference between each block group associated with each die in index 1 and each block group of the same die in index 2 (e.g., for die 0, |5-4| = 1; for die 1, |6-2| = 4; for die n, |4-5| = 1), select the largest difference value (e.g., 4), and compare the largest difference value to a block group threshold. If the largest difference value is less than the block group threshold, the memory sub-system controller 115 can combine the two block families. Figure 10

[0087] In another example, the data state metric can be a block group placement metric that indicates a difference in block group placement of a selected die of one block family and the same die of another block family. The threshold criterion can be satisfied if, for example, the difference in block group placement metric is below a block group threshold for all dies of the memory sub-system 110. In an illustrative example, the memory sub-system controller 115 can select two rows (e.g., indices 1 and 2) in the block family table 720, determine the difference between each block group associated with each die in index 1 and each block group of the same die in index 2 (e.g., for die 0, |5-4| = 1; for die 1, |6-2| = 4; for die n, |4-5| = 1), select the largest difference value (e.g., 4), and compare the largest difference value to a block group threshold. If the largest difference value is less than the block group threshold, the memory sub-system controller 115 can combine the two block families. Figure 7

[0088] ​​In another illustrative example, the DAC value of the time-voltage shift of the first candidate block family can be 16, the DAC value of the time-voltage shift of the second candidate block family can be 17, and the threshold value can be a DAC value of 2. Thus, the memory sub-system controller 115 can combine the first candidate block family and the second candidate block family because the difference 1 in the voltage metric values (2 - 1 = 1) is less than the threshold value of 2.

[0089] Figure 10 An example of combining block families based on per-die voltage metric values according to embodiments of the disclosure is illustratively explained. As Figure 10 Illustratively, the memory sub-system controller 115 can select a first candidate block family (e.g., BFn 1010) and its temporally adjacent block family (e.g., BFm 1020) as a second candidate block family. The memory sub-system controller 115 can select the first candidate block family as the oldest block family in the block family creation order, the newest block family in the block family creation order, the oldest or newest block family in a predetermined block group (e.g., the oldest or newest block family in block group 2), a random block family, etc. In response to selecting the first candidate block family, the memory sub-system controller 115 can then check its temporally adjacent block family, determine whether the difference in voltage metric values between each die associated with the first candidate block family and the same die associated with the second candidate block family (e.g., compare each die to itself) satisfies a threshold criterion. The threshold criterion can be satisfied when, for example, the maximum difference in voltage metrics of each die comparison is less than a predefined voltage threshold. Referring to Figure 10 , with the predefined voltage threshold being 0.5 DAC, the voltage difference for die 0 between the first candidate block family and the second candidate block family is 0.1 DAC, the voltage difference for die 1 between the first candidate block family and the second candidate block family is 0.2 DAC, the voltage difference for die 2 between the first candidate block family and the second candidate block family is 0.1 DAC, and the voltage difference for die 3 between the first candidate block family and the second candidate block family is 0.4 DAC. Thus, the maximum difference in voltage metric values of each die comparison is 0.4 DAC. Accordingly, the memory sub-system controller 115 can combine the first candidate block family and the second candidate block family because the maximum difference in voltage metric values of each die comparison (0.4 DAC) is less than the predefined voltage threshold of 0.5 DAC. The measurements related to the voltage metrics (or any data state metric) of each die comparison are stored in a temporary memory structure and are cleared once the process of determining whether to combine the first candidate block family and the second candidate block family is complete.

[0090] Figure 11 An example of metadata maintained by a memory sub-system controller to associate block families with die temperatures according to embodiments of the disclosure is illustratively explained. As Figure 11 Illustratively, the memory sub-system controller 115 can maintain a family table 1110.

[0091] The memory sub-system controller 115 can combine two block families based on a write temperature and / or a read temperature. The write temperature can be a temperature measured at the memory device during a write operation, such as a maximum temperature across all dies of the memory device, a minimum temperature across all dies of the memory device, a median temperature across all dies of the memory device, and the like. The read temperature can be a temperature measured at the memory device during a read operation, such as a maximum temperature across all dies of the memory device, a minimum temperature across all dies of the memory device, a median temperature across all dies of the memory device. By way of example, a method of combining block families based on a write temperature will be discussed. However, it should be noted that such a method can be applied to combining block families based on a read temperature.

[0092] In some embodiments, the memory sub-system controller 115 can select a pair of temporally adjacent block families. The memory sub-system controller 115 can select a first candidate block family based on an oldest block family in the block family creation order, a newest block family in the block family creation order, an oldest or newest block family in a predetermined block group (e.g., an oldest or newest block family in block group 2), a random block family, and the like. In response to selecting the first candidate block family, the memory sub-system controller 115 can then check its temporally adjacent block family (a second block family candidate) to determine whether a write temperature value difference between each die associated with the first candidate block family and a same die of the second candidate block family (e.g., compare each die to itself) satisfies a temperature threshold criterion. The temperature threshold criterion can be satisfied when, for example, a maximum difference in write temperature values for each die is less than a predefined temperature threshold.

[0093] In the illustrative example, the predefined temperature threshold can be 5°C, a write temperature difference for a first die associated with the first candidate block family and the second candidate block family can be 3°C, and a write temperature difference for a second die associated with the first candidate block family and the second candidate block family can be 4°C. Thus, a maximum difference in write temperatures for each die comparison is 4°C. Accordingly, the memory sub-system controller 115 can combine the first candidate block family and the second candidate block family because the maximum difference in write temperatures for each die comparison (4°C) is less than the predefined temperature threshold of 5°C. A maximum difference in write temperature values is used by way of example, and other criteria can be used, such as an average write temperature value for a die comparison, a median write value for a die comparison, and the like.

[0094] In some embodiments, the memory sub-system controller 115 can combine two block families when the write temperature of each die belongs to a write temperature threshold range. In an example, the write temperature threshold range can be 75°C to 80°C. The memory sub-system controller 115 can determine, via the family table 1110, that the write temperatures of the first, second, and third dies associated with the first candidate block family are 75°C, 77°C, and 78°C, respectively, and the write temperatures of the first, second, and third dies associated with the candidate second block family are 76°C, 79°C, and 79°C, respectively. Accordingly, the memory sub-system controller 115 can combine the first candidate block family and the second candidate block family because the write temperature of each die associated with the two block families belongs to the write temperature threshold range.

[0095] In some embodiments, the memory sub-system controller 115 can initiate combining block families in response to satisfying a combining criteria threshold. In an example, the combining criteria threshold can include an amount of existing (active) block families that exceeds a predefined threshold (e.g., 32). Combining block families can release locations, for example, in a family table metadata structure (e.g., the family table 720). In some embodiments, the memory sub-system controller 115 can stop combining block families in response to satisfying a stop combining criteria threshold. In an example, the stop combining criteria threshold can include an amount of existing (active) block families that is less than or equal to a predefined threshold (e.g., 28).

[0096] In some embodiments, in response to the memory sub-system controller 115 failing to detect combinable block families, the memory sub-system controller 115 modifies the criteria for combining block families. In an example, the memory sub-system controller 115 can modify a predefined voltage threshold criteria by increasing the predefined voltage threshold required to satisfy the voltage threshold criteria (e.g., from 0.5 DAC to 1.0 DAC). In another example, the memory sub-system controller 115 can modify a temperature threshold criteria by increasing the temperature threshold required to satisfy the temperature threshold criteria (e.g., from 5°C to 8°C). In yet another example, the memory sub-system controller 115 can modify a temperature threshold criteria by increasing the write temperature threshold range required to satisfy the temperature threshold criteria (e.g., from 75°C to 80°C to 73°C to 82°C).

[0097] Figure 12 A flowchart of an example method 1200 for block family management implemented by a memory sub-system controller operating in accordance with some embodiments of the present disclosure. The method 1200 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1200 is performed by the memory sub-system controller 115. Figure 1The block family manager component 113 executes. Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is understood that the illustrated embodiments are examples only and that the illustrated operations can be performed in a different order, and some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all of the operations described are required in every implementation, and other process flows are possible.

[0098] At operation 1210, processing logic of the memory sub-system controller initializes a block family and stores an identifier of the block family in a memory variable.

[0099] At operation 1215, the processing device initializes a timer associated with the block family.

[0100] At operation 1220, the processing logic initializes a low temperature and a high temperature associated with the block family to store a current temperature of a selected die (e.g., a randomly selected die) of the memory device.

[0101] In response to determining at operation 1225 that a difference between the high temperature value and the low temperature value is greater than or equal to a specified temperature threshold, the method branches to operation 1235; otherwise, the processing logic continues at operation 1230.

[0102] In response to determining at operation 1230 that a value of the timer associated with the block family is greater than or equal to a specified timeout value, the processing logic can shut down the block family at operation 1235; otherwise, the method loops back to operation 1225.

[0103] In response to performing operation 1235, the method loops back to operation 1210.

[0104] Operations 1250-1270 are performed asynchronously with respect to operations 1210-1260. In the illustrative example, operations 1210-1235 are performed by a first processing thread, and operations 1250-1270 are performed by a second processing thread.

[0105] At operation 1250, the processing logic receives a temperature measurement at the selected die of the memory device.

[0106] In response to determining at operation 1255 that the received temperature measurement is greater than or equal to the stored high temperature value, at operation 860, the processing logic updates the high temperature value to store the received temperature measurement.

[0107] In response to determining at operation 1265 that the received temperature measurement is lower than the stored low temperature value, at operation 1270, the processing logic updates the low temperature value to store the received temperature measurement.

[0108] Figure 13A flowchart of an example method for performing a read operation by a memory sub-system controller operating in accordance with some embodiments of the present disclosure. The method 1300 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1300 is performed by the block family manager component 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated operations can be performed in a different order, and / or concurrently, some operations can be performed in parallel / Thus, not all of the operations illustrated for each embodiment are required, and implementations include other operations not expressly shown. Additionally, storage of data in a memory device can be performed at various stages during the operations.

[0109] At operation 1310, the processing logic of the memory sub-system controller receives a read command specifying an identifier of a logical block.

[0110] At operation 1320, the processing logic converts the identifier of the logical block to a physical address (PA) of a physical block stored on the memory device. In the illustrative example, the conversion is performed by looking up the logical block identifier (also referred to as a logical block address or LBA) in a logical-to-physical (L2P) table associated with the memory device. The L2P table includes a plurality of mapping records such that each mapping record maps an LBA to a corresponding physical address. For a flash memory device, the physical address can include a channel identifier, a die identifier, a page identifier, a plane identifier, and / or a frame identifier.

[0111] At operation 1330, the processing logic identifies a block family associated with the physical address based on block family metadata associated with the memory device. In the illustrative example, the processing device utilizes the superblock table 710 of the Figure 7 to identify the block family associated with the physical address.

[0112] At operation 1340, the processing logic determines a threshold voltage offset associated with the block family and a memory device die. In the illustrative example, the processing device utilizes the block family table 720 of the Figure 7 to determine a block group identifier corresponding to a combination of the block family identifier and the die identifier. The processing device then utilizes the offset table 730 of the Figure 7 to determine the threshold voltage offset of the identified threshold voltage offset block group.

[0113] At operation 1350, the processing logic computes a modified threshold voltage by applying the identified threshold voltage offset to a base read level voltage associated with the memory device. As mentioned above, the base read level voltage can be stored in a metadata region of the memory device.

[0114] At operation 1360, the processing logic performs the requested read operation with the computed modified threshold voltage. In response to completing operation 1360, the method terminates.

[0115] Figure 14 A flowchart of an example method 1400 for block family management by a memory subsystem controller operating in accordance with some embodiments of the present disclosure. The method 1400 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a computing device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1400 is performed by the block family manager component 113 of Figure 1 Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, it is to be understood that the illustrated embodiments are merely examples, and that the illustrated operations can be performed in a different order, and / or concurrently with each other. Additionally, one or more operations can be omitted in some embodiments. As such, not all of the illustrated operations are necessarily required for every implementation, and other implementations are possible.

[0116] At operation 1410, the processing logic of the memory subsystem can create a first block family at a first time. The first block family can include a first set of blocks that have been programmed within a first specified time window and / or a first specified temperature window. Each block associated with the first block family can be associated with a first set of read level offsets.

[0117] At operation 1420, the processing logic can create a second block family at a second time. The second time can be after the first specified time window. The second block family can include a second set of blocks that have been programmed within a second specified time window and / or a second specified temperature window. Each block associated with the second block family can be associated with a second set of read level offsets.

[0118] At operation 1430, in response to determining that the threshold criteria are satisfied, the processing logic can combine the first block family and the second block family. For example, the processing logic can append a record of the blocks associated with the second block family to the first block family metadata of the first block family. The processing logic can further remove the record associated with the second block family from the block family table. In some embodiments, the threshold criteria include determining that a difference in voltage offset values associated with each die of the first block family and a same die of the second block family satisfies a voltage threshold criterion. In some embodiments, the threshold criteria include determining that a difference in write temperature values associated with a die of the first block family and the same die of the second block family satisfies a write temperature threshold criterion for all dies of the memory device. In some embodiments, the threshold criteria include determining that write temperature values for each die associated with the first block family and the second block family are within a predetermined temperature range. In some embodiments, the threshold criteria include determining that a difference in voltage offset values associated with the first block family and the second block family satisfies a voltage threshold criterion. In some embodiments, the threshold criteria include determining that a difference in write temperature values associated with the first block family and the second block family satisfies a write temperature threshold criterion. In some embodiments, the threshold criteria include determining that write temperature values associated with the first block family and the second block family are within a predetermined temperature range.

[0119] In some embodiments, the processing logic can initiate combining block families in response to satisfying a combining criteria threshold. For example, combining the first block family and the second block family can be performed in response to an amount of empty records in the block family table being less than a threshold. The processing logic can then stop combining block families in response to satisfying a stop combining criteria threshold. In an example, the stop combining criteria threshold can include an amount of empty block families being greater than a threshold.

[0120] The processing logic can begin a scan of combinable block families by selecting a newest block family (e.g., a most recently created block family) in a block family creation order as a combining candidate. The processing logic can then select a second block family in response to the second block family being adjacent to the first block family such that there are no other block families between the first block family and the second block family in the block family creation order. In response to failing to detect two block families that satisfy the threshold criteria, the processing logic can scan another pair of block families for combining. For example, the processing logic can select a second newest block family (and so on) in the block family creation order and a block family that is temporally adjacent to the second newest block family as candidates for combining. In some embodiments, in response to failing to detect two block families that satisfy the threshold criteria, the processing logic can modify the threshold criteria. For example, the processing logic can modify a predefined voltage threshold criterion such that there is a greater chance of detecting two combinable block families.

[0121] Figure 15An example machine illustrating computer system 1500 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 1500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the block family manager component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0122] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, it should be understood that the term "machine" also includes any collection of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0123] Example computer system 1500 includes a processing device 1502, a main memory 1504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1510 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1518, which communicate with each other via a bus 1530.

[0124] Processing device 1502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 1502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1502 is configured to execute instructions 1528 for performing the operations and steps discussed herein. Computer system 1500 may further include a network interface device 1512 for communication via network 1520.

[0125] Data storage system 1518 may include machine-readable storage medium 1524 (also referred to as computer-readable medium) on which one or more sets of instructions 1528 or software embodying any one or more of the methods or functions described herein are stored. Instructions 1528 may also reside wholly or at least partially within main memory 1504 and / or processing device 1502 during execution by computer system 1500, which also constitute machine-readable storage medium. Machine-readable storage medium 1524, data storage system 1518, and / or main memory 1504 may correspond to... Figure 1 The memory subsystem 110.

[0126] In one embodiment, instruction 1528 includes instructions for implementing the corresponding Figure 1 The block family manager component 113 contains functional instructions. Although the machine-readable storage medium 1524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. It should also be considered that the term "machine-readable storage medium" includes any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0127] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0128] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0129] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

[0130] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the methods. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0131] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., computing device, electronic device, etc.). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium, etc.

[0132] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: creating a first block family comprising a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read voltage level offsets; creating a second block family comprising a second set of blocks that have been programmed within at least one of a second specified time window after the first specified time window or a second specified temperature window, wherein each block associated with the second block family is associated with a second set of read voltage level offsets; and in response to determining that a threshold criterion is satisfied, combining the first block family and the second block family, wherein determining that the threshold criterion is satisfied comprises determining that a difference in voltage offset values associated with a die of the first block family and the same die of the second block family is below a voltage difference threshold for all dies of the memory device.

2. The memory system of claim 1, wherein determining that the threshold criterion is satisfied further comprises: determining that a difference in write temperature values associated with a die of the first block family and the same die of the second block family satisfies a write temperature threshold criterion for all dies of the memory device.

3. The memory system of claim 1, wherein determining that the threshold criterion is satisfied further comprises: determining that write temperature values associated with the first block family and the second block family are within a predetermined temperature range.

4. The memory system of claim 1, wherein combining the first block family and the second block family is performed in response to determining that a number of empty records in a block family table is below a threshold number.

5. The memory system of claim 1, wherein the second block family is created immediately after closing the first block family.

6. The memory system of claim 1, wherein the processing device is to further perform operations comprising: removing a record associated with the second block family from a block family table.

7. The memory system of claim 1, wherein the processing device is to further perform operations comprising: appending records of the second set of blocks to first block family metadata of the first block family.

8. The memory system of claim 1, wherein the processing device is to further perform operations comprising: selecting a most recently created block family among all block families and a second most recently created block family among all block families as combination candidates.

9. The memory system of claim 1, wherein the processing device is to further perform operations comprising: in response to failing to detect two block families that satisfy the threshold criterion, modifying the threshold criterion.

10. A method for memory comprising: creating a first block family comprising a first set of blocks that have been programmed within a first specified time window, wherein each block associated with the first block family is associated with a first set of read level offsets; creating a second block family including a second set of blocks that have been programmed within a second specified time window after the first specified time window, wherein each block associated with the second block family is associated with a second set of read level offsets; in response to determining that a difference in voltage offset values associated with a die of the first block family and the same die of the second block family is below a voltage difference threshold for all dies of the memory device, combining the first block family and the second block family.

11. The method of claim 10, wherein combining the first block family and the second block family is performed in response to determining that a number of empty records in a block family table is below a threshold number.

12. The method of claim 10, wherein the second block family is created immediately after closing the first block family.

13. The method of claim 10, further comprising: removing a record associated with the second block family from a block family table.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operably coupled to a memory device, perform operations comprising: creating a first block family including a first set of blocks that have been programmed within at least one of a first specified time window or a first specified temperature window, wherein each block associated with the first block family is associated with a first set of read voltage level offsets; creating a second block family including a second set of blocks that have been programmed within at least one of a second specified time window or a second specified temperature window after the first specified time window, wherein each block associated with the second block family is associated with a second set of read voltage level offsets; and in response to determining that a threshold criterion is satisfied, combining the first block family and the second block family, wherein determining that the threshold criterion is satisfied comprises determining that a difference in voltage offset values associated with a die of the first block family and the same die of the second block family is below a voltage difference threshold for all dies of the memory device.

15. The non-transitory computer-readable storage medium of claim 14, wherein determining that the threshold criterion is satisfied further comprises: determining that a difference in write temperature values associated with a die of the first block family and the same die of the second block family satisfies a write temperature threshold criterion for all dies of the memory device.

16. The non-transitory computer-readable storage medium of claim 14, wherein determining that the threshold criterion is satisfied further comprises: determining that write temperature values associated with the first block family and the second block family are within a predetermined temperature range.

17. The non-transitory computer-readable storage medium of claim 14, wherein combining the first block family and the second block family is performed in response to determining that a number of empty records in a block family table is below a threshold number.

18. The non-transitory computer-readable storage medium of claim 14, modifying the threshold criterion in response to failing to detect two block families that satisfy the threshold criterion.

19. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is to further perform operations comprising: selecting, as a combination candidate, a most recently created chunk family among all chunk families and a second most recently created chunk family among all chunk families.

20. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is to further perform operations comprising: appending records of the second set of chunks to first chunk family metadata of the first chunk family.

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