Semiconductor test element and semiconductor test method

Abstract

Embodiments of the present invention relate to semiconductor test devices and semiconductor test methods. A semiconductor test device comprises: a semiconductor substrate, a first internal interconnect structure, a second internal interconnect structure, a connecting metal layer, a redistribution layer structure, a first terminal, and a second terminal. The first internal interconnect structure and the second internal interconnect structure are arranged on the semiconductor substrate and are electrically isolated from the semiconductor substrate. The connecting metal layer electrically connects the first internal interconnect structure and the second internal interconnect structure and is electrically isolated from the semiconductor substrate. The redistribution layer structure is electrically connected to the first internal interconnect structure and the second internal interconnect structure. The first terminal and the second terminal are electrically connected to the first internal interconnect structure and the second internal interconnect structure, respectively, through the redistribution layer structure.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor test device and a semiconductor test method, and more particularly to a semiconductor test device for testing electrical over stress (EOS) and a test method for EOS. Background Art

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Generally speaking, semiconductor devices can form various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) on a wafer through a front-end-of-line (FEOL) process, and form interconnect structures that provide electrical connections between these electronic components through a back-end-of-line (BEOL) process to manufacture a large number of integrated circuits on the wafer. The individual dies on the wafer are singulated by sawing along the cutting lines between each integrated circuit, and the individual dies can be packaged into multi-die modules or other types of packages. The semiconductor industry continues to increase the integration density of various electronic components by continuously reducing the minimum feature size, which enables more components to be integrated into a given area. In some applications, these smaller electronic components also require smaller packages, which utilize a smaller area than previous packages.

[0003] The package structure is equipped with conductive terminals, such as power terminals, ground terminals, and signal terminals, to draw power for operation and exchange signals with other external circuits. However, because these terminals are made of conductive materials, they may accumulate charge during the manufacturing process, eventually causing electrical overload (or excessive electrical stress) (EOS), which can damage the internal structure of the integrated circuit.

[0004] As mentioned previously, electrical overload can occur at any stage in the entire process. However, current semiconductor package structures can only be measured after the entire package is fabricated. This only reveals whether electrical overload has occurred, but does not reveal the specific process stage where the overload occurred.

[0005] Therefore, there is still a need for a semiconductor test device for testing electrical overload and an electrical overload testing method, so as to promptly discover a process site where electrical overload occurs. Summary of the Invention

[0006] According to one embodiment of the present invention, a semiconductor test device is provided, comprising: a semiconductor substrate, a first internal interconnect structure, a second internal interconnect structure, a connection metal layer, a redistribution layer (RDL) structure, a first terminal, and a second terminal. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The connection metal layer electrically connects the first internal interconnect structure and the second internal interconnect structure and is electrically isolated from the semiconductor substrate. The redistribution layer structure is disposed on the first internal interconnect structure and the second internal interconnect structure and is electrically connected to the first internal interconnect structure and the second internal interconnect structure. The first terminal is electrically connected to the first internal interconnect structure through the redistribution layer structure, and the second terminal is electrically connected to the second internal interconnect structure through the redistribution layer structure.

[0007] According to one embodiment of the present invention, a semiconductor test device is further provided, comprising: a semiconductor substrate, a first internal interconnect structure, a second internal interconnect structure, a third internal interconnect structure, a redistribution layer structure, a first terminal, and a second terminal. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate and the first internal interconnect structure. The third internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate, the first internal interconnect structure, and the second internal interconnect structure. The redistribution layer structure is disposed on the first internal interconnect structure, the second internal interconnect structure, and the third internal interconnect structure, and is electrically connected to the first internal interconnect structure and the second internal interconnect structure. The first terminal is electrically connected to the first internal interconnect structure via the redistribution layer structure, and the second terminal is electrically connected to the second internal interconnect structure via the redistribution layer structure.

[0008] According to one embodiment of the present invention, a test method is further provided. The test method includes: receiving a semiconductor structure, the semiconductor structure including a semiconductor substrate, a first semiconductor test element, and a second semiconductor test element. The first semiconductor test element is disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate. The second semiconductor test element is disposed on the semiconductor substrate and electrically isolated from both the semiconductor substrate and the first semiconductor test element. A first continuity / disconnection test is performed on the first semiconductor test element. A second continuity / disconnection test is performed on the second semiconductor test element. When the result of the first continuity / disconnection test is disconnection, it is determined that a metal melting electrical overload has occurred. When the result of the second continuity / disconnection test is continuity, it is determined that a dielectric breakdown electrical overload has occurred. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0010] Figure 1 FIG. 1 is a partial schematic diagram of a semiconductor chip provided according to an embodiment of the present disclosure.

[0011] Figure 2 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0012] Figure 3 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0013] Figure 4 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0014] Figure 5 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0015] Figure 6 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0016] Figure 7is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0017] Figure 8 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0018] Figure 9 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0019] Figure 10 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0020] Figure 11 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0021] Figure 12 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0022] Figure 13 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line.

[0023] Figure 14 It is a flowchart of a testing method provided according to an embodiment of the present disclosure.

[0024] Figure 15A and Figure 15B is a schematic diagram according to one or more embodiments of the present disclosure.

[0025] Figure 16A and Figure 16B is a schematic diagram according to one or more embodiments of the present disclosure.

[0026] Figure 17A and Figure 17B is a schematic diagram according to one or more embodiments of the present disclosure.

[0027] Figure 18A and Figure 18B is a schematic diagram according to one or more embodiments of the present disclosure.

[0028] Figure 19A and Figure 19B is a schematic diagram according to one or more embodiments of the present disclosure.

[0029] Figure 20A and Figure 20B is a schematic diagram according to one or more embodiments of the present disclosure.

[0030] Figure 21A and Figure 21B is a schematic diagram according to one or more embodiments of the present disclosure.

[0031] Figure 22A and Figure 22B is a schematic diagram according to one or more embodiments of the present disclosure.

[0032] Figure 23A and Figure 23B is a schematic diagram according to one or more embodiments of the present disclosure.

[0033] Figure 24A and Figure 24B is a schematic diagram according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments or examples for implementing the different features of the provided theme. The specific examples of the elements and arrangements will be described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, "a first component is formed above or on a second component" may include embodiments in which the first component and the second component are directly contacted, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component may not be directly contacted. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition is intended to simplify and clarify and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0035] Furthermore, for convenience of description, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," and the like) may be used herein to describe the relationship of one element or component to another element or component, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0036] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, and these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or section from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and "third" as used herein do not imply a sequence or order.

[0037] Although the numerical ranges and parameters describing the broad scope of the present disclosure are approximate, the numerical values ​​described in the specific examples should be reported as precisely as possible. However, any numerical value inherently contains certain errors that are necessarily caused by the standard deviation present in the respective test measurements. In addition, as used herein, the terms "substantially," "approximately," or "about" generally mean within a value or range that one of ordinary skill in the art would consider. Alternatively, the terms "substantially," "approximately," or "about" mean within an acceptable standard deviation of the mean value as one of ordinary skill in the art would consider. One of ordinary skill in the art will understand that acceptable standard deviations can vary depending on the technology. Except in the operating / working examples or unless otherwise expressly stated, all numerical ranges, quantities, values, and percentages disclosed herein (e.g., numerical ranges, quantities, values, and percentages of material quantities, durations, temperatures, operating conditions, quantitative ratios, and the like) should be understood as being modified in all instances by the terms "substantially," "approximately," or "about." Therefore, unless otherwise indicated, the numerical parameters described in the present disclosure and the appended claims are approximate values ​​that can vary as desired. Finally, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other or between two endpoints. Unless otherwise indicated, all ranges disclosed herein include endpoints.

[0038] Conductive terminals within packaging structures, such as those formed during back-end-of-line (BEOL) and far-back-end-of-line (FBEOL) processes, can experience electrical overstress due to the accumulation of charge during the process. This can damage internal IC structures, such as interconnect structures formed during the back-end-of-line (BBEOL) process. Generally speaking, electrical overstress can be categorized into two types: metal burnout and dielectric breakdown. As the width and thickness of metal layers within interconnect structures decrease, the likelihood of metal burnout increases. Furthermore, the frequent use of ultralow-k (ULK) or extremely low-k (ELK) dielectric materials in interconnect structures further increases the likelihood of dielectric breakdown. However, currently, there is no test structure that can simultaneously detect both types of electrical overstress.

[0039] In addition, as mentioned above, charge accumulation occurs gradually during the process, and there is currently a lack of a test structure that can be used to detect whether the current process station is experiencing electrical overload.

[0040] Therefore, the present disclosure provides a semiconductor test element and a test method, wherein the semiconductor test element can be integrated into the back-end process and the remote back-end process, and a simple continuity / disconnection test is performed to determine whether an electrical overload has occurred. In some embodiments, a continuity / disconnection test is performed on a semiconductor test element used to test metal melting electrical overload. When the test result is a disconnection, it can be determined that a metal melting electrical overload has occurred. In some embodiments, a continuity / disconnection test is performed on a semiconductor test element used to test dielectric layer breakdown electrical overload. When the test result is continuity, it can be determined that a dielectric layer breakdown electrical overload has occurred. In addition, as previously mentioned, since the semiconductor test element can be integrated into the back-end process and the remote back-end process, it is possible to test endpoints of different layers after the back-end process is completed and during the remote back-end process, so as to promptly identify which process has the aforementioned electrical overload problem.

[0041] See also Figure 1 , Figure 1 FIG. 1 is a partial schematic diagram of a semiconductor chip provided by the present disclosure. According to the embodiment provided by the present disclosure, a semiconductor test device can be disposed on a semiconductor chip 100. Figure 1As shown, a semiconductor wafer 100 includes a plurality of scribe line regions 102 and a plurality of die regions 104 defined by the scribe line regions 102. In some embodiments, the die regions 104 are separated from each other by intersecting scribe line regions 102 and arranged in an array. During die singulation, the semiconductor wafer 100 is segmented along the scribe line regions 102 to separate the die regions 104, thereby obtaining a plurality of dies.

[0042] See also Figure 1 . In some embodiments, the semiconductor wafer 100 includes silicon or other semiconductor materials, such as III-V semiconductor materials. Those skilled in the art will appreciate that a variety of components (e.g., transistors, memory or power components, capacitors, resistors, diodes, photodiodes, sensors, fuses, and combinations thereof, and the like) may be formed in each die region 104. For example, the aforementioned components may be formed using a front-end process, and the combination of the components may form an integrated circuit in each die region 104. After the front-end process is completed, a plurality of contact plugs may be formed in each die region 104 using a middle-end-of-line (MEOL) process, but the present embodiment is not limited thereto. After the front-end process and the middle-end process are completed, a plurality of internal interconnect structures may be formed in each die region 104 using a back-end process. For example, multiple dielectric layers may be formed within each die region 104, and conductive layers may be formed within these dielectric layers, along with conductive plugs (vias) electrically connecting these conductive layers. This multi-layer structure of dielectric layers, conductive layers, and conductive plugs may form multiple internal interconnect structures within the die region 104, electrically connecting various components formed in the previous process steps and providing channels for connection to external circuits.

[0043] In some embodiments of the present disclosure, a semiconductor test device 200a is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 2 shown. Figure 2 is a cross-sectional view of a semiconductor test device according to an embodiment of the present disclosure, and can also be Figure 1 Schematic diagram of the cross section obtained along the A-A' tangent line. Figure 2As shown, a semiconductor test device 200a may include a semiconductor substrate 202. Within the semiconductor substrate 202, various components and combinations thereof formed using the aforementioned front-end processes may be included. The semiconductor test device 200a includes a first internal interconnect structure 210-1 and a second internal interconnect structure 210-2 disposed on the semiconductor substrate 202. The first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 are electrically isolated from the semiconductor substrate 202. In some embodiments, the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 are further physically isolated from the semiconductor substrate 202. The semiconductor test device 200a includes a connection metal layer 220 that electrically connects the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2, but the connection metal layer 220 is also electrically isolated from the semiconductor substrate 202. The semiconductor testing device 200a further includes a first terminal 230-1 and a second terminal 230-2. The first terminal 230-1 is electrically connected to the first internal interconnection structure 210-1, and the second terminal 230-2 is electrically connected to the second internal interconnection structure 210-2.

[0044] In some embodiments, the semiconductor test device 200a further includes a dummy internal interconnect structure 240. The dummy internal interconnect structure 240 is disposed on the semiconductor substrate 202 and is electrically isolated from the semiconductor substrate 202. Furthermore, the dummy internal interconnect structure 240 is disposed between the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 and is electrically isolated from both the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2.

[0045] In some embodiments, the semiconductor test device 200a further includes a third internal interconnect structure 250 disposed on the semiconductor substrate 202. The third internal interconnect structure 250 is electrically isolated from the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the dummy internal interconnect structure 240, and the connection metal layer 220. In other words, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the connection metal layer 220, and the dummy internal interconnect structure 240 are electrically floating structures. Unlike the aforementioned electrically floating structures, the third internal interconnect structure 250 is electrically connected to the semiconductor substrate 202. For example, the third internal interconnect structure 250 can be electrically connected to various components within the semiconductor substrate 202 via contact plugs formed during a mid-stage process to provide electrical connections between these components.

[0046] like Figure 2As shown, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 may include a plurality of dielectric layers, which may form a dielectric layer stack 204. The first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 may further include a plurality of conductive layers 206 and a plurality of conductive plugs 208 electrically connected to the conductive layers 206. The dielectric layer stack 204, the conductive layers 206, and the conductive plugs 208 may be formed on the semiconductor substrate 202 using the back-end of line (BOL) process described above. In some embodiments, the dummy internal interconnect structure 240 does not provide any effective electrical connection. However, during the back-end of line (BOL) process, the dummy internal interconnect structure 240 may prevent dishing between the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 during planarization in the back-end of line (BOL) process. Furthermore, the dummy internal interconnection structure 240 may also provide mechanical strength between the first internal interconnection structure 210 - 1 and the second internal interconnection structure 210 - 2 .

[0047] Please continue reading Figure 2 The conductive layer 206 of the third internal interconnect structure 250 includes a bottommost conductive layer. This bottommost conductive layer is the conductive line or metal line closest to the semiconductor substrate 202 and can be considered as the zeroth metal layer (M0). In some embodiments, the connecting metal layer 220 and the bottommost conductive layer M0 of the third internal interconnect structure 250 are disposed at the same level, but the present disclosure is not limited thereto.

[0048] In some embodiments, after the back-end process is completed, conductive bumps or conductive pads may be formed on the first and second internal interconnect structures 210-1, 210-2, respectively, to serve as first and second terminals 230-1, 230-2. The first terminal 230-1, the first internal interconnect structure 210-1, the connection metal layer 220, the second internal interconnect structure 210-2, and the second terminal 230-2 may form a via. The first and second terminals 230-1, 230-2 may serve as test terminals during semiconductor testing. This semiconductor testing may be used to determine whether electrical overloads occur at back-end manufacturing sites. This back-end semiconductor testing will be described in detail later.

[0049] See also Figure 2. In some embodiments, after semiconductor testing, the first terminal 230-1 and the second terminal 230-2 may be damaged by stress, so when the remote back-end process is subsequently performed, no other connection layer may be formed on the first terminal 230-1 and the second terminal 230-2. For example, after the semiconductor test, the die may be singulated, and then a molding compound 260 surrounding the die (or semiconductor substrate 202) may be formed. Next, the remote back-end process is performed to form a redistribution layer (RDL) structure 270 and a contact terminal 280 on the semiconductor substrate 202 and the molding compound 260. As Figure 2 As shown, the redistribution layer structure 270 may include a plurality of redistribution layers, and the redistribution layers respectively include an insulating layer, a plurality of connection portions 274 disposed in the insulating layer, and a plug portion 276 electrically connected to the connection portion 274. In some embodiments, the insulating layer of the redistribution layer may be regarded as an insulating layer stack 272. In addition, a contact terminal 280 may be provided on the redistribution layer structure 270, and the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnect structure 250. In some embodiments, the above-mentioned remote back-end process may form the above-mentioned insulating layer stack 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2 and the dummy internal interconnect structure 240, and the insulating layer stack 272 may cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. Figure 2 However, in other embodiments, multiple connection portions 274 and multiple plug portions 276 may be formed in the insulating layer on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240. However, these connection portions 274 and plug portions 276 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240 do not have contact terminals, or these connection portions 274 and plug portions 276 are electrically isolated from the first terminal 230-1 and the second terminal 230-2. Therefore, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the connection metal layer 220 are still electrically isolated from other components or structures by the dielectric layer stack 204 and the insulating layer stack 272, and remain electrically floating.

[0050] See also Figure 3 , Figure 3 is a cross-sectional view of another semiconductor test device 200b provided according to an embodiment of the present disclosure, and can also be Figure 1Schematic cross-sectional view taken along the A-A' line in FIG. 2. Note that similar elements in the semiconductor test device 200b and the semiconductor test device 200a are described with the same symbols, and therefore the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 200b is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 3 In addition, the semiconductor test device 200b may include a semiconductor substrate 202, a first internal interconnect structure 210-1, a second internal interconnect structure 210-2, a connection metal layer 220, a dummy internal interconnect structure 240, and a third internal interconnect structure 250. The relative relationships and connection relationships among the semiconductor substrate 202, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the connection metal layer 220, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 may be the same as those of the semiconductor test device 200a, and thus will not be further described herein.

[0051] Please continue reading Figure 3 . In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die may be singulated and then the molding material 260 may be formed. A remote back-end process is then performed to form a redistribution layer structure on the semiconductor substrate 202 and the molding material 260. As previously mentioned, the redistribution layer structure may include multiple redistribution layers. In some embodiments, a first redistribution layer 270-1 may be formed on the semiconductor substrate 202 and the molding material 260. The first redistribution layer 270-1 includes an insulating layer 272-1, a plurality of connection portions 274-1 disposed in the insulating layer 272-1, and a plurality of plug portions 276-1 electrically connecting the third internal interconnect structure 250 and the connection portion 274-1. As Figure 3As shown, the first redistribution layer 270-1 can be electrically connected to the third internal interconnect structure 250. When forming the first redistribution layer 270-1, an insulating layer 272-1, a connecting portion 274-1, and a plug portion 276-1 can be simultaneously formed on the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2. In some embodiments, a portion of the connecting portion 274-1 on the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 serves as a first terminal 230-1 and a second terminal 230-2, and the first terminal 230-1 is electrically connected to the first internal interconnect structure 210-1 through the plug portion 276-1, while the second terminal 230-2 is electrically connected to the second internal interconnect structure 210-2 through the plug portion 276-1. In other words, the first terminal 230-1 and the second terminal 230-2 are disposed on the same horizontal layer as the connecting portion 274-1 in the first redistribution layer 270-1. It is worth noting that the first terminal 230-1, the first internal interconnect structure 210-1, the connecting metal layer 220, the second internal interconnect structure 210-2 and the second terminal 230-2 can form a path, and the first terminal 230-1 and the second terminal 230-2 serve as test terminals when performing semiconductor testing. This semiconductor test can be used to test whether the manufacturing site of the first redistribution layer 270-1 is electrically overloaded. The semiconductor test of this site will be described in detail later.

[0052] In some embodiments, after the semiconductor test of the first redistribution layer 270-1 is completed, multiple redistribution layers may be fabricated on the first redistribution layer 270-1 to complete the following steps: Figure 3 In addition, after the redistribution layer structure 270 is completed, contact terminals 280 can be set on the redistribution layer structure 270. Figure 3 As shown, the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnect structure 250. In some embodiments, the remote back-end process can form the above-mentioned insulating layer stack 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2 and the dummy internal interconnect structure 240, and the insulating layer stack 272 can cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. Figure 3However, in other embodiments, multiple connection portions and multiple plug portions may be formed within the insulating layer 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240. However, these connection portions and plug portions on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240 do not have contact terminals, or these connection portions and plug portions, as well as the first terminal 230-1 and the second terminal 230-2, are electrically isolated. Therefore, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the connection metal layer 330 are still electrically isolated from other components or structures by the dielectric layer stack 204 and the insulating layer stack 272, and remain electrically floating.

[0053] See also Figure 4 , Figure 4 is a cross-sectional view of another semiconductor test device 200c provided according to an embodiment of the present disclosure, and can also be Figure 1 It should be noted that similar elements in the semiconductor test device 200c and the semiconductor test device 200b are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 200c is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 4 As shown, the semiconductor test device 200c may include a semiconductor substrate 202, a first internal interconnect structure 210-1, a second internal interconnect structure 210-2, a connection metal layer 220, a dummy internal interconnect structure 240, and a third internal interconnect structure 250. The relative relationships and connection relationships among the semiconductor substrate 202, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the connection metal layer 220, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 are the same as those of the semiconductor test device 200b and are therefore not further described herein.

[0054] Please continue reading Figure 4. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die may be singulated and then the molding material 260 may be formed. A remote back-end process is then performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260. As described above, the redistribution layer structure 270 may include multiple redistribution layers. In some embodiments, a first redistribution layer 270-1 may be formed on the semiconductor substrate 202 and the molding material 260. As described above, the first redistribution layer 270-1 includes an insulating layer 272-1, a plurality of connection portions 274-1, and a plurality of plug portions 276-1. After the first redistribution layer 270-1 is formed, a second redistribution layer 270-2 may be formed on the first redistribution layer 270-1. The second redistribution layer 270-2 may include an insulating layer 272-2, a plurality of connection portions 274-2 disposed in the insulating layer 272-2, and a plurality of plug portions 276-2 electrically connecting the connection portion 274-1 and the connection portion 274-2. Figure 4 As shown, the first redistribution layer 270 - 1 and the second redistribution layer 270 - 2 may be electrically connected to the third internal interconnect structure 250 .

[0055] Furthermore, when fabricating the first and second redistribution layers 270-1, 270-2, the first and second redistribution layers 270-1, 270-2 are simultaneously formed on the first and second internal interconnect structures 210-1, 210-2. In some embodiments, a portion of the connecting portion 274-2 on the second internal interconnect structure 210-2 serves as the first terminal 230-1 and the second terminal 230-2, with the first terminal 230-1 being electrically connected to the first internal interconnect structure 210-1, and the second terminal 230-2 being electrically connected to the second internal interconnect structure 210-2. In other words, the first terminal 230-1 and the second terminal 230-2 are disposed on the same horizontal layer as the connecting portion 274-2 within the second redistribution layer 270-2. It is worth noting that the first terminal 230-1, the first internal interconnect structure 210-1, the connecting metal layer 220, the second internal interconnect structure 210-2 and the second terminal 230-2 form a path, and the first terminal 230-1 and the second terminal 230-2 serve as test terminals when performing semiconductor testing. This semiconductor test can be used to test whether the manufacturing site of the second redistribution layer 270-2 is electrically overloaded. The semiconductor test of this site will be described in detail later.

[0056] In some embodiments, after the semiconductor test of the second redistribution layer 270-2 is completed, the production of multiple redistribution layers can be continued on the second redistribution layer 270-2 to complete the following steps: Figure 4 In addition, after the redistribution layer structure 270 is completed, contact terminals 280 can be set on the redistribution layer structure 270. Figure 4As shown, the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnect structure 250. In some embodiments, the remote back-end process can form the above-mentioned insulating layer stack 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2 and the dummy internal interconnect structure 240, and the insulating layer stack 272 can cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. Figure 4 However, in other embodiments, multiple connection portions and multiple plug portions may be formed within the insulating layer 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240. However, these connection portions and plug portions on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the dummy internal interconnect structure 240 do not have contact terminals, or these connection portions and plug portions are electrically isolated from the first terminal 230-1 and the second terminal 230-2. Therefore, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the connection metal layer 330 are still electrically isolated from other components or structures by the dielectric layer stack 204 and the insulating layer stack 272, maintaining an electrically floating state.

[0057] See also Figure 5 , Figure 5 is a cross-sectional view of another semiconductor test device 200d provided according to an embodiment of the present disclosure, and can also be Figure 1 It should be noted that similar elements in the semiconductor test device 200d and the semiconductor test device 200c are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 200d is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 5 As shown, the semiconductor test device 200d may include a semiconductor substrate 202, a first internal interconnect structure 210-1, a second internal interconnect structure 210-2, a connection metal layer 220, a dummy internal interconnect structure 240, and a third internal interconnect structure 250. The relative relationship and connection relationship among the semiconductor substrate 202, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the connection metal layer 220, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 are the same as those of the semiconductor test device 200c and are not further described herein.

[0058] Please continue reading Figure 5. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die can be singulated and then the molding material 260 can be formed. Then, a remote back-end process is performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260. As described above, the redistribution layer structure 270 can include multiple redistribution layers. In some embodiments, a first redistribution layer 270-1 and a second redistribution layer 270-2 can be formed on the semiconductor substrate 202 and the molding material 260. As described above, the first redistribution layer 270-1 includes an insulating layer 272-1, multiple connection portions 274-1 and multiple plug portions 276-1; the second redistribution layer 270-2 includes an insulating layer 272-2, multiple connection portions 274-2 and multiple plug portions 276-2. After the second redistribution layer 270-2 is formed, a third redistribution layer 270-3 can be formed on the second redistribution layer 270-2. The third redistribution layer 270-3 may include an insulating layer 272-3, a plurality of connection portions 274-3 disposed in the insulating layer 272-3, and a plurality of plug portions 276-3 electrically connecting the connection portions 274-2 and the connection portions 274-3. Figure 5 As shown, the first redistribution layer 270 - 1 , the second redistribution layer 270 - 2 , and the third redistribution layer 270 - 3 may be electrically connected to the third internal interconnect structure 250 .

[0059] In addition, when making the above-mentioned three redistribution layers 270-1, 270-2 and 270-3, the three redistribution layers 270-1, 270-2 and 270-3 are formed on the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2 at the same time. In some embodiments, a partial connection portion 274-3 of the third redistribution layer 270-3 serves as a first terminal 230-1 and a second terminal 230-2, and the first terminal 230-1 is electrically connected to the first internal interconnect structure 210-1, and the second terminal 230-2 is electrically connected to the second internal interconnect structure 210-2. In other words, the first terminal 230-1 and the second terminal 230-2 can be arranged on the same horizontal layer as the connection portion 274-3 in the third redistribution layer 270-3. Figure 5 As shown, the first terminal 230-1, the first internal interconnect structure 210-1, the connecting metal layer 220, the second internal interconnect structure 210-2 and the second terminal 230-2 can form a path, and the first terminal 230-1 and the second terminal 230-2 can be used as test terminals when performing semiconductor testing. This semiconductor test can be used to test whether the manufacturing site of the third redistribution layer 270-3 is electrically overloaded. The semiconductor test of this site will be described in detail later.

[0060] In some embodiments, after completing the semiconductor test of the third redistribution layer 270-3 process station, the production of multiple redistribution layers can be continued on the third redistribution layer 270-3 to complete the production of the redistribution layer structure 270. Alternatively, the contact terminal 280 can be directly set on the third redistribution layer 270-3 (i.e., the redistribution layer structure 270). Figure 5 As shown, the contact terminal 280 is electrically connected to the circuit inside the semiconductor substrate 202 through the redistribution layer structure 270 and the third internal interconnect structure 250. In some embodiments, the remote back-end process can form the above-mentioned insulating layer stack 272 on the first internal interconnect structure 210-1, the second internal interconnect structure 210-2 and the dummy internal interconnect structure 240, and the insulating layer stack 272 can cover the first terminal 230-1 and the second terminal 230-2, as shown in FIG. Figure 5 Therefore, the first internal interconnect structure 210 - 1 , the second internal interconnect structure 210 - 2 , and the connection metal layer 230 are still electrically isolated from other elements or structures by the dielectric layer stack 204 and the insulation layer stack 272 , and remain electrically floating.

[0061] See also Figure 6 , Figure 6 is a cross-sectional view of another semiconductor test device 200e provided according to an embodiment of the present disclosure, and can also be Figure 1 It should be noted that similar elements in the semiconductor test device 200e and the semiconductor test device 200d are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 200e is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 6 As shown, the semiconductor test device 200e may include a semiconductor substrate 202, a first internal interconnect structure 210-1, a second internal interconnect structure 210-2, a connection metal layer 220, a dummy internal interconnect structure 240, and a third internal interconnect structure 250. The relative relationship and connection relationship among the semiconductor substrate 202, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the connection metal layer 220, the dummy internal interconnect structure 240, and the third internal interconnect structure 250 are the same as those of the semiconductor test device 200d and will not be further described herein.

[0062] Please continue reading Figure 6. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die may be singulated and then the molding material 260 may be formed. A remote back-end process is then performed to form a redistribution layer structure 270 on the semiconductor substrate 202 and the molding material 260. As previously described, the redistribution layer structure 270 may include a plurality of redistribution layers, such as the first redistribution layer 270-1, the second redistribution layer 270-2, and the third redistribution layer 270-3 mentioned above. In some embodiments, the redistribution layer structure 270 may include more redistribution layers. Each redistribution layer 270-1, 270-2, 270-3 includes an insulating layer, and the insulating layer can be regarded as an insulating layer stack 272. Each redistribution layer 270-1, 270-2, 270-3 also includes a plurality of connection portions 274 disposed in the insulating layer, and a plurality of plug portions 276 electrically connecting the connection portions 274 in each insulating layer and the third internal interconnect structure 250. After forming the redistribution layer structure 270, contact terminals 280 may be formed on the redistribution layer structure 270. Figure 6 As shown, contact terminal 280 is electrically connected to the circuitry within semiconductor substrate 202 via redistribution layer structure 270 and third internal interconnect structure 250. When forming contact terminal 280, first terminal 230-1 can be formed on first internal interconnect structure 210-1 and second terminal 230-2 can be formed on second internal interconnect structure 210-2 simultaneously. First terminal 230-1 is electrically connected to first internal interconnect structure 210-1, and second terminal 230-2 is electrically connected to second internal interconnect structure 210-2. In other words, first terminal 230-1 and second terminal 230-2 can be disposed on the same horizontal layer as contact terminal 280. It is worth noting that the first terminal 230-1, the first internal interconnect structure 210-1, the connecting metal layer 220, the second internal interconnect structure 210-2 and the second terminal 230-2 can form a path, and the first terminal 230-1 and the second terminal 230-2 can be used as test terminals when performing semiconductor testing. This semiconductor test can be used to test whether the manufacturing site of the contact terminal 280 is electrically overloaded. The semiconductor test of this site will be described in detail later.

[0063] In some embodiments, because the first terminal 230-1 and the second terminal 230-2 can be used for semiconductor testing, they may not be electrically connected to other circuits or structures during subsequent processing. Therefore, the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, and the connection metal layer 220 may remain electrically floating except during semiconductor testing.

[0064] Based on the above description, it can be seen that multiple semiconductor test devices 200a, 200b, 200c, 200d, and 200e can be disposed within the die area 104. Different semiconductor test devices can be used to test different process sites for electrical overstress. In some embodiments, the semiconductor test devices 200a, 200b, 200c, 200d, and 200e are further used to detect metal melting electrical overstress at different process sites. These test sites and semiconductor testing will be described in detail later. Furthermore, since semiconductor testing is performed by contacting the first terminal 230-1 and the second terminal 230-2 with a probe, the first terminal 230-1 and the second terminal 230-2 may be subjected to stress and damaged. Therefore, the first terminal 230-1 and the second terminal 230-2 will no longer participate in any subsequent electrical connection establishment. As previously described, the first terminal 230-1 or the second terminal 230-2 can be covered by the insulating layer stack 272, or the first terminal 230-1 or the second terminal 230-2 can be electrically disconnected from other circuits. In other words, the first terminal 230-1 and the second terminal 230-2 can be considered sacrificial terminals, but the present disclosure is not limited thereto.

[0065] See also Figure 7 . The semiconductor test element provided by the present disclosure can adjust its sensitivity by the setting position of the connecting metal layer 220. Generally speaking, in the internal interconnection structure, the closer the conductive layer is to the semiconductor substrate 202, the smaller the thickness. For example, the thickness of the M0 conductive layer, the M1 conductive layer and the M2 conductive layer may be smaller than the thickness of the M3 conductive layer and the conductive layer thereon. The production of the connecting metal layer 220 can be simultaneous with the production of any layer of the conductive layer. Therefore, when the location where the connecting metal layer 220 is set is made at the same time as these lower conductive layers (that is, located at the same horizontal layer), it will of course have the same thickness as them. The sensitivity of the semiconductor test element is inversely proportional to the thickness of the connecting metal layer. That is to say, when the connection metal layer 220 of the semiconductor test element is set at the same horizontal layer as these lower conductive layers, its sensitivity is greater than that of the semiconductor test element whose connection metal layer 220 is set at the same horizontal layer as the higher conductive layers. As Figure 7As shown, in some embodiments, the connection metal layer 220 of the semiconductor test device 200f may be co-located with a higher conductive layer, such as an M3 conductor layer. Therefore, the sensitivity of the semiconductor test device 200f may be lower than that of the semiconductor test devices 200a, 200b, 200c, 200d, and 200e. It should also be noted that, to avoid CMP dishing and provide sufficient mechanical strength, in some embodiments, the semiconductor test device 200f includes not only a dummy internal interconnect structure 240-1 disposed between the first internal interconnect structure 210-1 and the second internal interconnect structure 210-2, but also a dummy internal interconnect structure 240-2 disposed beneath the first internal interconnect structure 210-1, the second internal interconnect structure 210-2, the dummy internal interconnect structure 240-1, and the connection metal layer 220. The dummy internal interconnection structure 240 - 2 is electrically isolated from the first internal interconnection structure 210 - 1 , the second internal interconnection structure 210 - 2 , the dummy internal interconnection structure 240 - 1 , and the connection metal layer 220 .

[0066] Also, it should be noted that although Figure 7 The disclosed semiconductor test device 200f has its first terminal 230-1 and second terminal 230-2 positioned in the same locations as those of the semiconductor test device 200e. However, the positions of the first terminal 230-1 and second terminal 230-2 of the semiconductor test device 200f can also be the same as those of the semiconductor test devices 200a, 200b, 200c, and 200d. In other words, the semiconductor test device provided by the present disclosure can have its connection metal layer 220 positioned at different conductive layer levels according to different sensitivity requirements. Furthermore, by configuring different terminal layers, semiconductor test devices can be provided for use at different process stations.

[0067] In addition, the sensitivity of the semiconductor test device can be adjusted not only by the setting position of the connection metal layer 220, but also by the width of the connection metal layer 220. Since the thickness of the connection metal layer 220 is the same as the thickness of the conductive layer at the same level, after determining the production level of the connection metal layer 220, the sensitivity of the semiconductor test device can be adjusted by adjusting the width of the connection metal layer 220. For example, when the connection metal layer 220 is set at the same level as the M0 conductive layer, the connection metal layer 220 with a larger width makes the semiconductor test device have a higher sensitivity. Therefore, in some embodiments, according to the sensitivity requirements of the semiconductor test device, the width of the connection metal layer 220 can be increased or decreased to obtain higher or lower sensitivity.

[0068] See next Figure 8 , Figure 8 is a cross-sectional view of another semiconductor test device 300a provided according to an embodiment of the present disclosure, and can also be Figure 1 In some embodiments of the present disclosure, a semiconductor test device 300a is provided. As shown above, the semiconductor test device 300a can be arranged in a Figure 1 On the semiconductor wafer 100 shown, it can be disposed in the die area 104. Figure 8 As shown, the semiconductor test device 300a may include a semiconductor substrate 302, and within the semiconductor substrate 302, various components and combinations thereof formed using the aforementioned front-end process may be included. The semiconductor test device 300a includes a first internal interconnect structure 310-1, a second internal interconnect structure 310-2, and a third internal interconnect structure 310-3, which are disposed on the semiconductor substrate 302. The first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3 are electrically isolated from the semiconductor substrate 302, respectively. In some embodiments, the first interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3 are further physically isolated from the semiconductor substrate 302. As Figure 8 As shown, the third internal interconnect structure 310-3 is disposed between the first internal interconnect structure 310-1 and the second internal interconnect structure 310-2. More importantly, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3 are electrically isolated from each other. In some embodiments, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3 are further physically isolated from each other, such as Figure 8 The semiconductor test device 300a further includes a first terminal 330-1 and a second terminal 330-2, wherein the first terminal 330-1 is electrically connected to the first internal interconnection structure 310-1, and the second terminal 330-2 is electrically connected to the second internal interconnection structure 310-2.

[0069] In some embodiments, the semiconductor test device 300a further includes a fourth internal interconnect structure 350 disposed on the semiconductor substrate 302. The fourth internal interconnect structure 350 is electrically isolated from the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3. In other words, the first internal interconnect structure 330-1, the second internal interconnect structure 330-2, and the third internal interconnect structure 330-3 are electrically floating structures. Unlike the aforementioned electrically floating structures, the fourth internal interconnect structure 350 is electrically connected to the semiconductor substrate 302. For example, the fourth internal interconnect structure 350 can be electrically connected to various components within the semiconductor substrate 302 via contact plugs formed during a mid-stage process to provide electrical connectivity between these components.

[0070] like Figure 8As shown, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, the third internal interconnect structure 310-3, and the fourth internal interconnect structure 350 may include a plurality of dielectric layers, which may form a dielectric layer stack 304. The first internal interconnect structure 310-1, the second internal interconnect structure 310-2, the third internal interconnect structure 310-3, and the fourth internal interconnect structure 350 further include a plurality of conductive layers 306 and a plurality of conductive plugs 308 electrically connected to the conductive layers 306. The dielectric layer stack 304, the conductive layers 306, and the conductive plugs 308 may be formed on the semiconductor substrate 302 by performing the aforementioned back-end-of-line process.

[0071] In some embodiments, the conductive layer of the first internal interconnect structure 310-1 includes at least the bottom conductive layer M0-1, the conductive layer of the second internal interconnect structure 310-2 includes at least the bottom conductive layer M0-2, and the conductive layer of the third internal interconnect structure 310-3 includes at least the bottom conductive layer M0-3. Figure 8 As shown, a gap G1 is defined between the bottommost conductive layer M0-1 and the bottommost conductive layer M0-2, and a gap G2 is defined between the bottommost conductive layer M0-2 and the bottommost conductive layer M0-3. In some embodiments, the widths of gaps G1 and G2 are equal, but the present disclosure is not limited thereto. Furthermore, the first internal interconnect structure 310-1 and the third internal interconnect structure 310-3 can be physically and electrically isolated by gap G1; and the second internal interconnect structure 310-2 and the third internal interconnect structure 310-3 can be physically and electrically isolated by gap G2.

[0072] In some embodiments, after the back-end (BOL) process is completed, conductive bumps or pads may be formed on the first and second internal interconnect structures 310-1, 310-2, respectively, to serve as first and second terminals 330-1, 330-2. The first terminal 330-1 is electrically connected to the first internal interconnect structure 310-1, while the second terminal 330-2 is electrically connected to the second internal interconnect structure 310-2. The first and second terminals 330-1, 330-2 can serve as test terminals during semiconductor testing. This semiconductor testing can be used to detect electrical overloads at back-end (BOL) manufacturing sites. This BOL semiconductor testing will be described in detail later.

[0073] See also Figure 8In some embodiments, after semiconductor testing, the first terminal 330-1 and the second terminal 330-2 may be damaged by stress. Therefore, when performing a remote back-end process, no other connection layer may be formed on the first terminal 330-1 and the second terminal 330-2. For example, after semiconductor testing, the die may be singulated and then the molding material 360 may be formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 and a contact terminal 380 on the semiconductor substrate 302 and the molding material 360. Figure 8 As shown. Redistribution layer structure 370 may include multiple redistribution layers, each of which includes an insulating layer, multiple connection portions 374 disposed in the insulating layer, and multiple plug portions 376 electrically connected to the connection portions 374. In some embodiments, the insulating layer of the redistribution layer can be considered as an insulating layer stack 372. Furthermore, contact terminals 380 may be disposed on redistribution layer structure 370. Contact terminals 380 are electrically connected to circuits within semiconductor substrate 302 through redistribution layer structure 370 and fourth internal interconnect structure 350.

[0074] In some embodiments, the remote back-end process may form the insulating layer stack 372 on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3, and the insulating layer stack 372 may cover the first terminal 330-1 and the second terminal 330-2. Figure 8 However, in other embodiments, multiple connection portions 374 and multiple plug portions 376 may be formed in the insulating layer stack 372 on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3. However, these connection portions 374 and plug portions 376 on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 are not provided with contact terminals, or these connection portions 374 and plug portions 376 are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 are still electrically isolated from other components or structures by the dielectric layer stack 304 and the insulating layer stack 372, and remain electrically floating.

[0075] See also Figure 9 , Figure 9 is a cross-sectional view of another semiconductor test device 300b provided according to an embodiment of the present disclosure, and can also be Figure 1. It should be noted that similar elements in the semiconductor test device 300b and the semiconductor test device 300a are described with the same symbols, so the relevant details are not repeated. In some embodiments of the present disclosure, a semiconductor test device 300b is provided, which can be disposed in the die area 104, such as Figure 1 and Figure 9 As shown, the semiconductor test device 300b may include a semiconductor substrate 302, a first internal interconnection structure 310-1, a second internal interconnection structure 310-2, a third internal interconnection structure 310-3, and a fourth internal interconnection structure 350. The composition, structure, and relative relationships of the semiconductor substrate 302, the first internal interconnection structure 310-1, the second internal interconnection structure 310-2, the third internal interconnection structure 310-3, and the fourth internal interconnection structure 350 are the same as those of the semiconductor test device 300a, and thus will not be further described herein.

[0076] Please continue reading Figure 9 . In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die may be singulated and then the molding material 360 may be formed. A remote back-end process is then performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360. As previously mentioned, the redistribution layer structure may include multiple redistribution layers. In some embodiments, a first redistribution layer 370-1 may be formed on the semiconductor substrate 302 and the molding material 360. The first redistribution layer 370-1 includes an insulating layer 372-1, a plurality of connection portions 374-1 disposed in the insulating layer 372-1, and a plurality of plug portions 376-1 electrically connecting the fourth internal interconnect structure 350 and the connection portion 374-1. As Figure 9 As shown, the first redistribution layer 370 - 1 may be electrically connected to the fourth internal interconnect structure 350 .

[0077] When forming the first redistribution layer 370-1, an insulating layer 372-1, a connecting portion 374-1, and a plug portion 376-1 may be simultaneously formed on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3. In some embodiments, a portion of the connecting portion 374-1 on the first internal interconnect structure 310-1 and the second internal interconnect structure 310-2 serves as a first terminal 330-1 and a second terminal 330-2. The first terminal 330-1 is electrically connected to the first internal interconnect structure 310-1 via the plug portion 376-1, and the second terminal 330-2 is electrically connected to the second internal interconnect structure 310-2 via the plug portion 376-1. In other words, the first terminal 330-1 and the second terminal 330-2 are disposed on the same horizontal layer as the connecting portion 374-1 within the first redistribution layer 370-1. The first terminal 330 - 1 and the second terminal 330 - 2 can be used as test terminals during semiconductor testing. This semiconductor testing can be used to test whether electrical overload occurs at a manufacturing site of a back-end process. The semiconductor testing of the back-end process will be described in detail later.

[0078] In some embodiments, after the semiconductor test of the first redistribution layer 370-1 is completed, multiple redistribution layers may be fabricated on the first redistribution layer 370-1 to complete the following steps: Figure 9 In addition, after the redistribution layer structure 370 is completed, a contact terminal 380 can be set on the redistribution layer structure 370. Figure 9 As shown, the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnect structure 350. In some embodiments, the remote back-end process can form the above-mentioned insulating layer stack 372 on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2 and the third internal interconnect structure 310-3, and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. Figure 9 However, in other embodiments, multiple connection portions and multiple plug portions may be formed within the insulating layer 372 on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3. However, these connection portions and plug portions on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 do not have contact terminals, or these connection portions and plug portions are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 are still electrically isolated from other components or structures by the dielectric layer stack 304 and the insulating layer stack 372, and remain electrically floating.

[0079] See also Figure 10 , Figure 10 1 is a cross-sectional view of another semiconductor test device 300c provided according to an embodiment of the present disclosure. It should be noted that similar elements in the semiconductor test device 300c and the semiconductor test device 300b are described with the same symbols, and the relevant details are not repeated here. In some embodiments of the present disclosure, a semiconductor test device 300c is provided, which can be disposed in the bare die area 104. The semiconductor test device 300c can include a semiconductor substrate 302, a first internal interconnect structure 310-1, a second internal interconnect structure 310-2, a third internal interconnect structure 310-3, and a fourth internal interconnect structure 350. The composition, structure, and relative relationship of the aforementioned semiconductor substrate 302, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, the third internal interconnect structure 310-3, and the fourth internal interconnect structure 350 are the same as those of the semiconductor test device 300b, and therefore will not be repeated here.

[0080] Please continue reading Figure 10 . In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die can be singulated and then the molding material 360 can be formed. The remote back-end process is then performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360. As described above, the redistribution layer structure 370 may include multiple redistribution layers. In some embodiments, a first redistribution layer 370-1 can be formed on the semiconductor substrate 302 and the molding material 360. As described above, the first redistribution layer 370-1 includes an insulating layer 372-1, a plurality of connection portions 374-1, and a plurality of plug portions 376-1. After the first redistribution layer 370-1 is formed, a second redistribution layer 370-2 can be formed on the first redistribution layer 370-1. The second redistribution layer 370-2 may include an insulating layer 372-2, a plurality of connection portions 374-2 disposed in the insulating layer 372-2, and a plurality of plug portions 376-2 electrically connecting the connection portion 374-1 and the connection portion 374-2. Figure 10 As shown, the first redistribution layer 370 - 1 and the second redistribution layer 370 - 2 may be electrically connected to the fourth internal interconnect structure 350 .

[0081] Furthermore, when fabricating the first and second redistribution layers 370-1, 370-2, the first and second redistribution layers 370-1, 370-2 are simultaneously formed on the first, second, and third internal interconnect structures 310-1, 310-2, and 310-3. In some embodiments, a portion of the connecting portion 374-2 on the first, second, and third internal interconnect structures 310-1, 310-2, and 310-3 serves as a first terminal 330-1 and a second terminal 330-2, with the first terminal 330-1 being electrically connected to the first internal interconnect structure 310-1, and the second terminal 330-2 being electrically connected to the second internal interconnect structure 310-2. In other words, the first terminal 330-1 and the second terminal 330-2 can be disposed on the same horizontal layer as the connecting portion 374-2 within the second redistribution layer 370-2. The first terminal 330 - 1 and the second terminal 330 - 2 can be used as test terminals during semiconductor testing. This semiconductor testing can be used to test whether electrical overload occurs at a manufacturing site of a back-end process. The semiconductor testing of the back-end process will be described in detail later.

[0082] In some embodiments, after the semiconductor test of the second redistribution layer 370-2 is completed, the production of multiple redistribution layers can be continued on the second redistribution layer 370-2 to complete the following steps: Figure 10 In addition, after the redistribution layer structure 370 is completed, contact terminals 380 can be set on the redistribution layer structure 370. Figure 10 As shown, the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnect structure 350. In some embodiments, the remote back-end process can form the above-mentioned insulating layer stack 372 on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2 and the third internal interconnect structure 310-3, and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. Figure 10 However, in other embodiments, multiple connection portions and multiple plug portions may be formed within the insulating layer 372 on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3. However, these connection portions and plug portions on the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 do not have contact terminals, or these connection portions and plug portions are electrically isolated from the first terminal 330-1 and the second terminal 330-2. Therefore, the first inner interconnect structure 310-1, the second inner interconnect structure 310-2, and the third inner interconnect structure 310-3 are still electrically isolated from other components or structures by the dielectric layer stack 304 and the insulating layer stack 372, and remain electrically floating.

[0083] See also Figure 11 , Figure 11 1 is a cross-sectional view of another semiconductor test device 300d provided according to an embodiment of the present disclosure. It should be noted that similar elements in the semiconductor test device 300d and the semiconductor test device 300c are indicated by the same reference numerals, and therefore the relevant details are not repeated here. In some embodiments of the present disclosure, a semiconductor test device 300d is provided, which can be disposed in the die area 104. The semiconductor test device 300d can include a semiconductor substrate 302, a first internal interconnect structure 310-1, a second internal interconnect structure 310-2, a third internal interconnect structure 310-3, and a fourth internal interconnect structure 350. The composition, structure, and relative relationship of the aforementioned semiconductor substrate 302, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, the third internal interconnect structure 310-3, and the fourth internal interconnect structure 350 are the same as those of the semiconductor test device 300a, and therefore are not repeated here.

[0084] Please continue reading Figure 11 . In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, die singulation can be performed, and then a molding material 360 can be formed. A remote back-end process is then performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360. As described above, the redistribution layer structure 370 can include multiple redistribution layers. In some embodiments, a first redistribution layer 370-1 and a second redistribution layer 370-2 can be formed on the semiconductor substrate 302 and the molding material 360. As described above, the first redistribution layer 370-1 can include an insulating layer 372-1, multiple connection portions 374-1, and multiple plug portions 376-1. The second redistribution layer 370-2 can include an insulating layer 372-2, multiple connection portions 374-2, and multiple plug portions 376-2. After the second redistribution layer 370-2 is formed, a third redistribution layer 370-3 can be formed on the second redistribution layer 370-2. The third redistribution layer 370-3 may include an insulating layer 372-3, a plurality of connection portions 374-3 disposed in the insulating layer 372-3, and a plurality of plug portions 376-3 electrically connecting the connection portions 374-2 and the connection portions 374-3. Figure 11 As shown, the first redistribution layer 370 - 1 , the second redistribution layer 370 - 2 , and the third redistribution layer 370 - 3 may be electrically connected to the fourth internal interconnect structure 350 .

[0085] Furthermore, when fabricating the three redistribution layers 370-1, 370-2, and 370-3, the three redistribution layers 370-1, 370-2, and 370-3 are simultaneously formed on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3. In some embodiments, a portion of the connecting portion 374-3 on the first internal interconnect structure 310-1 and the second internal interconnect structure 310-2 serves as a first terminal 330-1 and a second terminal 330-2, with the first terminal 330-1 being electrically connected to the first internal interconnect structure 310-1, and the second terminal 330-2 being electrically connected to the second internal interconnect structure 310-2. In other words, the first terminal 330-1 and the second terminal 330-2 can be disposed on the same horizontal layer as the connecting portion 374-3 within the third redistribution layer 370-3. The first terminal 330 - 1 and the second terminal 330 - 2 can be used as test terminals during semiconductor testing. This semiconductor testing can be used to test whether electrical overload occurs at a manufacturing site of a back-end process. The semiconductor testing of the back-end process will be described in detail later.

[0086] In some embodiments, after the third redistribution layer 370-3 is completed, the redistribution layer structure 370 is completed. After the semiconductor test of this process station is completed, contact terminals 380 can be set on the redistribution layer structure 370. Figure 11 As shown, the contact terminal 380 is electrically connected to the circuit inside the semiconductor substrate 302 through the redistribution layer structure 370 and the fourth internal interconnect structure 350. In some embodiments, the remote back-end process can form an insulating layer stack 372 on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2 and the third internal interconnect structure 310-3, and the insulating layer stack 372 can cover the first terminal 330-1 and the second terminal 330-2, as shown in FIG. Figure 11 As shown, the first internal interconnect structure 310 - 1 , the second internal interconnect structure 310 - 2 and the third internal interconnect structure 310 - 3 are still electrically isolated from other elements or structures by the dielectric layer stack 304 and the insulation layer stack 372 , and remain electrically floating.

[0087] See also Figure 12 , Figure 121 is a cross-sectional view of another semiconductor test device 300e provided according to an embodiment of the present disclosure. It should be noted that similar elements in the semiconductor test device 300e and the semiconductor test device 300d are represented by the same reference numerals, and therefore the relevant details are not repeated here. In some embodiments of the present disclosure, a semiconductor test device 300e is provided, which can be disposed in the die area 104. The semiconductor test device 300e can include a semiconductor substrate 302, a first internal interconnect structure 310-1, a second internal interconnect structure 310-2, a third internal interconnect structure 310-3, and a fourth internal interconnect structure 350. The composition, structure, and relative relationship of the semiconductor substrate 302, the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, the third internal interconnect structure 310-3, and the fourth internal interconnect structure 350 are the same as those of the semiconductor test device 300a, and therefore are not repeated here.

[0088] Please continue reading Figure 12. In some embodiments, after the back-end process is performed to complete the above-mentioned internal interconnect structure, the die can be singulated and then the molding material 360 can be formed. Then, a remote back-end process is performed to form a redistribution layer structure 370 on the semiconductor substrate 302 and the molding material 360. As mentioned above, the redistribution layer structure 370 may include multiple redistribution layers, such as the first redistribution layer 370-1, the second redistribution layer 370-2 and the third redistribution layer 370-3 mentioned above. In some embodiments, the redistribution layer structure 370 may include more redistribution layers. Each redistribution layer 370-1, 370-2, 370-3 includes an insulating layer, and the insulating layer can be regarded as an insulating layer stack 372. Each redistribution layer 370-1, 370-2, 370-3 also includes a plurality of connection portions 374 disposed in the insulating layer, and a plurality of plug portions 376 electrically connecting the connection portions 374 in each insulating layer. Furthermore, when forming the first redistribution layer 370-1, the second redistribution layer 370-2, and the third redistribution layer 370-3, a redistribution layer structure 370 including three redistribution layers is simultaneously formed on the first internal interconnect structure 310-1, the second internal interconnect structure 310-2, and the third internal interconnect structure 310-3. After the redistribution layer structure 370 is formed, a contact terminal 380 can be formed on the redistribution layer structure 370. It is noteworthy that, while forming the contact terminal 380, a first terminal 330-1 can be formed on the first internal interconnect structure 310-1, and a second terminal 330-2 can be formed on the second internal interconnect structure 310-2. In other words, the first terminal 330-1 and the second terminal 330-2 can be arranged on the same horizontal layer as the contact terminal 380. In these embodiments, first terminal 330-1 is electrically connected to first internal interconnect structure 310-1, and second terminal 330-2 is electrically connected to second internal interconnect structure 310-2. First terminal 330-1 and second terminal 330-2 can serve as test terminals during semiconductor testing. This semiconductor testing can be used to detect electrical overloads at back-end manufacturing sites. Back-end semiconductor testing will be described in detail later.

[0089] In some embodiments, first terminal 330-1 and second terminal 330-2 can be used for semiconductor testing. In subsequent processes, first terminal 330-1 and second terminal 330-2 may not be electrically connected to other circuits or structures. Therefore, first internal interconnect structure 310-1, second internal interconnect structure 310-2, and third internal interconnect structure 310-3 can remain electrically floating except during semiconductor testing.

[0090] Based on the above description, it can be seen that multiple semiconductor test devices 300a, 300b, 300c, 300d, and 300e can be disposed within the die area 104. Different semiconductor test devices can be used to test different process sites for electrical overstress. In some embodiments, the semiconductor test devices 300a, 300b, 300c, 300d, and 300e are further used to detect dielectric breakdown and electrical overstress at different process sites. These test sites and semiconductor testing will be described in detail later. As previously described, since semiconductor testing is performed by contacting the first terminal 330-1 and the second terminal 330-2 with a probe, the first terminal 330-1 and the second terminal 330-2 may be subjected to stress and damaged. Therefore, the first terminal 330-1 and the second terminal 330-2 no longer participate in any subsequent electrical connection construction. As previously described, the first terminal 330-1 or the second terminal 330-2 can be covered by the insulating layer stack 372, or the first terminal 330-1 or the second terminal 330-2 can be electrically disconnected from other circuits. In other words, the first terminal 330-1 and the second terminal 330-2 can be considered sacrificial terminals, but the present disclosure is not limited thereto.

[0091] See also Figure 13 In the semiconductor test devices 300a, 300b, 300c, 300d, and 300e used to test dielectric layer breakdown, the third internal interconnect structure 310-3 is used as an antenna to attract charge. Therefore, the total area of ​​the conductive layers in the third internal interconnect structure 310-3 can affect the sensitivity of the semiconductor test devices 300a, 300b, 300c, 300d, and 300e. For example, the larger the total area of ​​the conductive layers in the third internal interconnect structure 310-3, the higher the sensitivity of the semiconductor test device. Figure 13 As shown, in some embodiments, the total area of ​​the conductive layers in the third internal interconnect structure 310-3 of semiconductor test device 300f is smaller than the total area of ​​the conductive layers in semiconductor test devices 300a, 300b, 300c, 300d, and 300e. Therefore, the sensitivity of semiconductor test device 300f is lower than that of semiconductor test devices 300a, 300b, 300c, 300d, and 300e. In other words, the semiconductor test device provided by the present disclosure can adjust the sensitivity of the semiconductor test device by adjusting the total area of ​​the conductive layers in the third internal interconnect structure 310-3.

[0092] Also, it should be noted that although Figure 13The first terminal 330-1 and the second terminal 330-2 of the disclosed semiconductor test device 300f are disposed at the same positions as those of the semiconductor test device 300e. However, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300f may also be disposed at the same positions as those of the semiconductor test devices 300a, 300b, 300c, and 300d.

[0093] See also Figure 14 , Figure 14 FIG. 1 is a flow chart of a semiconductor testing method according to an embodiment of the present disclosure. Figure 14 As shown, the semiconductor testing method 40 includes operations 401, 410, 420, 412a, 412b, 414a, and 414b. Furthermore, the semiconductor testing method 40 provided herein may include other steps for additional operations before, during, and after the method 40. Only some of these additional operations are briefly described herein, but the method is not limited thereto.

[0094] In some embodiments, as described in operation 401, a semiconductor structure is received. The semiconductor structure can be a semiconductor wafer, such as Figure 1 As shown, it includes multiple die areas 104 and cutting road areas 102, which are defined on the semiconductor substrate. Each die area 104 may include various types of semiconductor elements or combinations thereof arranged on the semiconductor substrate. The elements may be the same as those described above, so they will not be described in detail here. The semiconductor structure may include a first semiconductor test element and a second semiconductor test element. The first semiconductor test element and the second semiconductor test element are electrically isolated from each other and from the semiconductor substrate respectively. In some embodiments, the first semiconductor test element may be a semiconductor test element 200a, and the second semiconductor test element may be a semiconductor test element 300a. In some embodiments, the semiconductor test element 200a and the semiconductor test element 300a can be manufactured through the back-end process with the interconnection structure in the die area 104. Therefore, at the end of the back-end process, the semiconductor test element 200a and the semiconductor test element 300a can be used to test whether the back-end process has an electrical overload problem. It is also worth noting that the semiconductor testing method disclosed herein is a wafer-level test.

[0095] See also Figure 15A and Figure 15BIn some embodiments, operations 410 and 420 may be performed simultaneously. For example, in operation 410, a probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the semiconductor test device 200a, and operation 412a or operation 412b is performed according to the detection result. As previously described, the first terminal 230-1, the first internal interconnection structure 210-1, the connecting metal layer 220, the second internal interconnection structure 210-2 and the second terminal 230-2 of the semiconductor test device 200a constitute a circuit path. Therefore, as Figure 15A As shown, when the probe P contacts the first terminal 230-1 and the second terminal 230-2 and the detection result is continuity, it is determined that the semiconductor structure has no electrical overload problem in this process, as described in operation 412a, and the next process station can be entered.

[0096] However, if an electrical overload problem occurs in the back-end process, excessive charge may be accumulated in the connection metal layer 220, causing the connection metal layer 220 to melt. Figure 15B As shown by the middle melt break MB, the path originally formed by the first terminal 230-1, the first internal interconnect structure 210-1, the connecting metal layer 220, the second internal interconnect structure 210-2, and the second terminal 230-2 becomes an open circuit. Therefore, when the probe P contacts the first terminal 230-1 and the second terminal 230-2 and the detection result is an open circuit, it is determined that the semiconductor structure has experienced a metal melt electrical overstress problem during this process step, as described in operation 412b.

[0097] See also Figure 16A and Figure 16B At the same time as operation 410, in operation 420, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300a are contacted with a probe P, and operation 414a or operation 414b is performed according to the detection result. As described above, the first internal interconnection structure 310-1 (and the first terminal 330-1), the second internal interconnection structure 310-2 (and the second terminal 330-2), and the third internal interconnection structure 310-3 of the semiconductor test device 300a are electrically isolated from each other. Therefore, Figure 16A As shown, when the probe P contacts the first terminal 330-1 and the second terminal 330-2 and the detection result is a disconnection, as described in operation 414a, it is determined that the semiconductor structure does not have an electrical overload problem in this process, so it can enter the next process station.

[0098] However, if an electrical overload problem occurs in the back-end process, then excessive charge may accumulate between the conductive layers and eventually exceed the breakdown voltage of the dielectric layer 304, causing current to flow through the dielectric layer, such as Figure 16BAs indicated by the arrow in the middle, the first terminal 330-1, the first internal interconnect structure 310-1, the third internal interconnect structure 310-3, the second internal interconnect structure 310-2, and the second terminal 330-2 form a circuit path. Therefore, when the probe P contacts the first terminal 330-1 and the second terminal 330-2 and the detection result is an open circuit, it is determined that the semiconductor structure has experienced dielectric layer breakdown and electrical overstress during this process step, as described in operation 414b.

[0099] As previously mentioned, the semiconductor test method 30 can be performed at other process sites. For example, after the back-end process is completed, the die can be singulated, the die can be divided and placed on a carrier wafer, and then a molding material can be formed, and the remote back-end process can be started to form the redistribution layer structure and the contact terminals. In some embodiments, the semiconductor test method 40 can be implemented after each redistribution layer is completed in the remote back-end process to detect whether the redistribution layer has an electrical overload problem. In addition, the semiconductor test method provided by the present disclosure is still a wafer-level test method when used to detect the remote back-end process.

[0100] See also Figure 17A and Figure 17B as well as Figure 18A and Figure 18B In some embodiments, the first semiconductor test device may be the semiconductor test device 200 b , and the second semiconductor test device may be the semiconductor test device 300 b .

[0101] After the first redistribution layer 270-1 / 370-1 in the redistribution layer structure 270 / 370 is completed, operations 410 and 420 may be performed simultaneously. For example, in operation 410, a probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the semiconductor test device 200b, and operation 412a or operation 412b is performed according to the test result. Figure 17A As shown, when the probe P contacts the first terminal 230-1 and the second terminal 230-2, if the detection result is a continuity, it is determined that the semiconductor structure has not experienced an electrical overload problem in this process, as described in operation 412a, and the next process station can be entered. However, if an electrical overload occurs in the back-end process, causing the connection metal layer 220 to melt, as shown in FIG. Figure 17B As shown in the middle melt MB, the detection result is a short circuit. As described in operation 412b, when the detection result is a short circuit, it is determined that the semiconductor structure has a metal melting electrical overload problem in this process.

[0102] See also Figure 18A and Figure 18BSimultaneously with operation 410, in operation 420, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300b are contacted with a probe P, and operation 414a or operation 414b is performed according to the detection result. Figure 18A As shown, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, if the detection result is a disconnection, it is as described in operation 414a, that is, it is determined that the semiconductor structure has no electrical overload problem in this process, so it can enter the next process station. However, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, the detection result is as shown in FIG. Figure 18B When a via is shown, it is as described in operation 414b, that is, it is determined that the semiconductor structure has experienced dielectric layer breakdown electrical overstress during this stage of the process.

[0103] See also Figure 19A and Figure 19B as well as Figure 20A and Figure 20B In some embodiments, the first semiconductor test device may be the semiconductor test device 200 c , and the second semiconductor test device may be the semiconductor test device 300 c .

[0104] In these embodiments, after the second redistribution layer 270-2 / 370-2 in the redistribution layer structure 270 / 370 is completed, operations 410 and 420 may be performed simultaneously. For example, in operation 410, a probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the semiconductor test device 200c, and operation 412a or operation 412b is performed based on the detection result. Figure 19A As shown, when the probe P contacts the first terminal 230-1 and the second terminal 230-2, if the detection result is continuity, it is determined that the semiconductor structure has not experienced electrical overload during this process, as described in operation 412a, and the next process station can be entered. However, if electrical overload occurs during this process, causing the connection metal layer 220 to melt, as shown in FIG. Figure 19B As shown in the middle melt MB, the detection result is a short circuit. As described in operation 412b, when the detection result is a short circuit, it is determined that the semiconductor structure has a metal melting electrical overload problem in this process.

[0105] See also Figure 20A and Figure 20B Simultaneously with operation 410, in operation 420, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300c are contacted with a probe P, and operation 414a or operation 414b is performed according to the detection result. Figure 20AAs shown, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, if the detection result is a disconnection, it is as described in operation 414a, that is, it is determined that the semiconductor structure has not experienced an electrical overload problem in this process, so it can enter the next process station. However, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, the detection result is as shown in FIG. Figure 20B When a via is shown, it is as described in operation 414b, that is, determining whether the semiconductor structure has a dielectric layer breakdown electrical overstress problem in this stage of the process.

[0106] See also Figure 21A and Figure 21B as well as Figure 22A and Figure 22B In some embodiments, the first semiconductor test device may be the semiconductor test device 200d, and the second semiconductor test device may be the semiconductor test device 300d.

[0107] In these embodiments, after the third redistribution layer 270-3 / 370-3 in the redistribution layer structure 270 / 370 is completed, operations 410 and 420 may be performed simultaneously. For example, in operation 410, a probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the semiconductor test device 200d, and operation 412a or operation 412b is performed according to the detection result. Figure 21A As shown, when the probe P contacts the first terminal 230-1 and the second terminal 230-2, if the detection result is continuity, it is determined that the semiconductor structure has not experienced electrical overload during this process, as described in operation 412a, and the next process station can be entered. However, if electrical overload occurs during this process, causing the connection metal layer 220 to melt, as shown in FIG. Figure 21B As shown in the middle melt MB, the detection result is a short circuit. As described in operation 412b, when the detection result is a short circuit, it is determined that the semiconductor structure has a metal melting electrical overload problem in this process.

[0108] See also Figure 22A and Figure 22B Simultaneously with operation 410, in operation 420, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300d are contacted by a probe P, and operation 414a or operation 414b may be performed according to the detection result. Figure 22A As shown, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, if the detection result is a disconnection, it is as described in operation 414a, that is, it is determined that the semiconductor structure has not experienced an electrical overload problem in this process, so it can enter the next process station. However, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, the detection result is as shown in FIG. Figure 22BWhen a via is shown, it is as described in operation 414b, that is, determining whether the semiconductor structure has a dielectric layer breakdown electrical overstress problem in this stage of the process.

[0109] See also Figure 23A and Figure 23B as well as Figure 24A and Figure 24B In some embodiments, the first semiconductor test device may be the semiconductor test device 200 e , and the second semiconductor test device may be the semiconductor test device 300 e .

[0110] In these embodiments, after the redistribution layer structure 270 / 370 is completed, contact terminals 280 / 380 may be formed on the redistribution layer 270 / 370, and first terminals 230-1 / 330-1 and second terminals 230-2 / 330-2 may be formed on the redistribution layer structure 270 / 370 of the semiconductor test device 200e and the semiconductor test device 300e at the same time. Thereafter, operations 410 and 420 may be performed. For example, in operation 410, a probe P is used to contact the first terminal 230-1 and the second terminal 230-2 of the semiconductor test device 200e, and operation 412a or operation 412b is performed according to the detection result. Figure 23A As shown, when the probe P contacts the first terminal 230-1 and the second terminal 230-2, if the detection result is a continuity, it is determined that the semiconductor structure has not experienced an electrical overload problem in this process, as described in operation 412a, and the next process station can be entered. However, if an electrical overload occurs in the back-end process, causing the connection metal layer 220 to melt, as shown in FIG. Figure 23B As shown in the middle melt MB, the detection result is a short circuit. As described in operation 412b, when the detection result is a short circuit, it is determined that the semiconductor structure has a metal melting electrical overload problem in this process.

[0111] See also Figure 24A and Figure 24B Simultaneously with operation 410, in operation 420, the first terminal 330-1 and the second terminal 330-2 of the semiconductor test device 300e are contacted with a probe P, and operation 414a or operation 414b is performed according to the detection result. Figure 24A As shown, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, if the detection result is a disconnection, it is as described in operation 414a, that is, it is determined that the semiconductor structure has not experienced an electrical overload problem in this process, so it can enter the next process station. However, when the probe P contacts the first terminal 330-1 and the second terminal 330-2, the detection result is as shown in FIG. Figure 24B When a via is shown, it is as described in operation 414b, that is, determining whether the semiconductor structure has a dielectric layer breakdown electrical overstress problem in this stage of the process.

[0112] Simply put, this method allows for simple continuity / disconnection testing at different process stations using multiple semiconductor test devices disposed on a semiconductor substrate. The continuity or disconnection test results can be used to easily determine whether an electrical overload has occurred at that process station, directly determining whether the overload has resulted in metal meltdown or dielectric breakdown. In other words, the semiconductor test device provided by this disclosure can provide timely and accurate test results, further contributing to increased reliability and process yield in semiconductor packaging processes.

[0113] In some embodiments, a semiconductor test element is provided. The semiconductor test element includes: a semiconductor substrate, a first internal interconnect structure, a second internal interconnect structure, a connecting metal layer, a redistribution layer structure, a first terminal, and a second terminal. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The connecting metal layer electrically connects the first internal interconnect structure and the second internal interconnect structure, and the connecting metal layer is electrically isolated from the semiconductor substrate. The redistribution layer structure is disposed on the first internal interconnect structure and the second internal interconnect structure, and is electrically connected to the first internal interconnect structure and the second internal interconnect structure. The first terminal is electrically connected to the first internal interconnect structure through the redistribution layer structure; and the second terminal is electrically connected to the second internal interconnect structure through the redistribution layer structure.

[0114] In some embodiments, a semiconductor test device is provided. The semiconductor test device includes: a semiconductor substrate, a first internal interconnect structure, a second internal interconnect structure, a third internal interconnect structure, a redistribution layer structure, a first terminal, and a second terminal. The first internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate. The second internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate and the first internal interconnect structure. The third internal interconnect structure is disposed on the semiconductor substrate and is electrically isolated from the semiconductor substrate, the first internal interconnect structure, and the second internal interconnect structure. The redistribution layer structure is disposed on the first internal interconnect structure, the second internal interconnect structure, and the third internal interconnect structure, and is electrically connected to the first internal interconnect structure and the second internal interconnect structure. The first terminal is electrically connected to the first internal interconnect structure through the redistribution layer structure; and the second terminal is electrically connected to the second internal interconnect structure through the redistribution layer structure.

[0115] In some embodiments, a semiconductor testing method is provided. The method includes receiving a semiconductor structure, the semiconductor structure including a semiconductor substrate, a first semiconductor test element disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and a second semiconductor test element disposed on the semiconductor substrate and electrically isolated from both the semiconductor substrate and the first semiconductor test element. The method further includes performing a first continuity / disconnection test on the first semiconductor test element and a second continuity / disconnection test on the second semiconductor test element. The method further includes determining that a metal melting electrical overstress has occurred when the result of the first continuity / disconnection test is a disconnection; and determining that a dielectric breakdown electrical overstress has occurred when the result of the second continuity / disconnection test is a continuity.

[0116] The features of several embodiments have been summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications thereto.

[0117] Explanation of symbols

[0118] 100 semiconductor chips

[0119] 102 Cutting area

[0120] 104 die area

[0121] 200a~200e、300a~300e semiconductor test components

[0122] 202, 302 semiconductor substrate

[0123] 204, 304 dielectric layer stack

[0124] 206, 306 conductive layer

[0125] 208, 308 conductive plugs

[0126] 210-1, 310-1 First internal interconnection structure

[0127] 210-2, 310-2 Second internal interconnection structure

[0128] 220 Connecting metal layer

[0129] 230-1, 330-1 First endpoint

[0130] 230-2, 330-2 Second endpoint

[0131] 240, 240-1, 240-2 virtual internal interconnection structure

[0132] 250, 310-3 Third internal interconnection structure

[0133] 350 Fourth Internal Interconnection Structure

[0134] 260, 360 molding materials

[0135] 270, 370 heavy layer structure

[0136] 270-1, 370-1 first layer

[0137] 270-2, 370-2 second layer

[0138] 270-3, 370-3 third layer

[0139] 272 Insulation stack

[0140] 272-1 to 272-3, 372-1 to 372-3 insulation layer

[0141] 274 connection part

[0142] 274-1 to 274-3, 374-1 to 374-3 connecting part

[0143] 276-1 to 276-3, 376-1 to 376-3 plug part

[0144] 280, 380 contact endpoints

[0145] G1, G2 interval

[0146] MB Metal layer melted

[0147] 40 methods.

Claims

1. A semiconductor test element, comprising: semiconductor substrates; a first internal interconnect structure, disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate; a second internal interconnect structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate; a connecting metal layer electrically connecting the first internal interconnect structure and the second internal interconnect structure, wherein the connecting metal layer is electrically isolated from the semiconductor substrate; a redistribution layer structure, disposed on the first internal interconnection structure and the second internal interconnection structure, and electrically connected to the first internal interconnection structure and the second internal interconnection structure; a first endpoint electrically connected to the first internal interconnect structure through the redistribution layer structure; a second endpoint electrically connected to the second internal interconnect structure through the redistribution layer structure; as well as A dummy internal interconnection structure is disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, wherein the dummy internal interconnection structure is disposed between the first internal interconnection structure and the second internal interconnection structure and electrically isolated from the first internal interconnection structure and the second internal interconnection structure.

2. The semiconductor test device according to claim 1, further comprising a third internal interconnect structure disposed on the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the third internal interconnect structure is electrically isolated from the first internal interconnect structure and the second internal interconnect structure. 3 . The semiconductor test device according to claim 1 , wherein the first internal interconnect structure and the second internal interconnect structure respectively comprise a plurality of dielectric layers, a plurality of conductive layers disposed within the dielectric layers, and a plurality of conductive plugs electrically connected to the conductive layers. 4 . The semiconductor test device according to claim 1 , wherein the RDL structure comprises a plurality of RDLs, and each of the RDLs comprises a plurality of connection portions and plug portions electrically connected to the connection portions.

5. A semiconductor test element comprising: semiconductor substrates; a first internal interconnect structure, disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate; a second internal interconnect structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate and the first internal interconnect structure; a third internal interconnect structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, the first internal interconnect structure, and the second internal interconnect structure; a redistribution layer structure, disposed on the first internal interconnection structure, the second internal interconnection structure, and the third internal interconnection structure, and electrically connected to the first internal interconnection structure and the second internal interconnection structure; a first endpoint electrically connected to the first internal interconnect structure through the redistribution layer structure; as well as a second terminal electrically connected to the second internal interconnect structure through the redistribution layer structure, The third internal interconnection structure is disposed between the first internal interconnection structure and the second internal interconnection structure.

6. The semiconductor test device according to claim 5, further comprising a fourth internal interconnection structure disposed on the semiconductor substrate and electrically connected to the semiconductor substrate, wherein the fourth internal interconnection structure is electrically isolated from the first internal interconnection structure, the second internal interconnection structure, and the third internal interconnection structure.

7. The semiconductor test device according to claim 5, wherein the first internal interconnection structure, the second internal interconnection structure, and the third internal interconnection structure respectively include a plurality of dielectric layers, a plurality of conductive layers disposed within the dielectric layers, and a plurality of conductive plugs electrically connected to the conductive layers.

8. A semiconductor testing method comprising: receiving a semiconductor structure comprising a semiconductor substrate, a first semiconductor test element disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and a second semiconductor test element disposed on the semiconductor substrate and electrically isolated from both the semiconductor substrate and the first semiconductor test element; performing a first continuity / disconnection test on the first semiconductor test element; performing a second continuity / disconnection test on the second semiconductor test element; When the result of the first open / closed circuit test is open circuit, it is determined that a metal melting electrical overload has occurred; as well as When the result of the second continuity / disconnection test is continuity, it is determined that dielectric layer breakdown electrical overload has occurred. The first semiconductor test element further includes a dummy internal interconnection structure disposed on the semiconductor substrate and electrically isolated from the semiconductor substrate, and the dummy internal interconnection structure is disposed between the first internal interconnection structure and the second internal interconnection structure and electrically isolated from the first internal interconnection structure and the second internal interconnection structure.

9. The testing method according to claim 8, wherein the first semiconductor testing device comprises: a connecting metal layer, disposed between the first internal interconnect structure and the second internal interconnect structure and electrically isolated from the semiconductor substrate; a first endpoint electrically connected to the first internal interconnection structure; as well as The second terminal is electrically connected to the second internal interconnection structure.

10. The testing method according to claim 8, wherein the second semiconductor testing device comprises: a third internal interconnection structure; a fourth internal interconnect structure electrically isolated from the third internal interconnect structure; and The fifth internal interconnection structure is disposed between the third internal interconnection structure and the fourth internal interconnection structure.

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