Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure describes a semiconductor structure and a method for manufacturing the same, wherein the semiconductor structure has an insulating layer disposed on the active surface of a semiconductor wafer for covering the active surface of the wafer. The insulating layer may be a protective layer in some embodiments and a covering layer in other embodiments. The insulating layer has a through-hole opening to expose a contact pad for leading out an electrical connection. Specifically, the through-hole opening is formed by a multi-step etching process (e.g., a two-step etching process) without damaging the contact pad. The two-step etching process includes a first laser etching process that uses a normal pulse (P) and normal energy (E) to form a through-hole half-opening in the covering layer; and a second etching process that uses a low P and low E laser etching process or a plasma etching process. The second etching process avoids damaging the contact pad.

Description

[0001] Cross-references

[0002] This disclosure claims priority to U.S. Provisional Application No. 63 / 114,536, filed on November 17, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure having a through-hole opening. The present disclosure also relates to a method for manufacturing the semiconductor structure having a through-hole opening. Background Art

[0004] Semiconductor devices, or dies, are processed simultaneously on a semiconductor wafer. After processing, the wafer is singulated into individual dies. For example, a wafer singulation process is performed to separate the wafer into individual dies, including sawing the wafer along dicing lines or sawing wires. The dies are then packaged to form packaged devices, including forming a redistribution layer with interconnects on top of the passivation layer.

[0005] An insulating layer can be provided on the active side of a semiconductor wafer. The insulating layer is patterned to form via openings that expose contact pads located on the active side of the wafer. However, conventional techniques for forming via openings in the insulating layer can damage the contact pads, thereby impacting the reliability of the contact pads leading out of the functional circuitry on the active side of the wafer.

[0006] Therefore, there is an urgent need in the industry to form a through-hole opening in an insulating layer located on the active surface of a semiconductor wafer without damaging the contact pads. Summary of the Invention

[0007] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure comprises: a semiconductor wafer having an active surface and an inactive surface facing each other, wherein a plurality of contact pads are formed on the active surface; an insulating layer disposed on the active surface of the wafer, covering the active surface of the wafer and the contact pads; and a plurality of through-hole openings formed in the insulating layer, exposing the contact pads from the insulating layer without damaging the contact pads. The semiconductor structure can be further separated into grain structures for further processing.

[0008] In some embodiments, the semiconductor structure further includes an adhesion promoting layer located between the active surface of the wafer and the insulating layer, for adhering the insulating layer to the active surface of the wafer.

[0009] In some embodiments, the semiconductor structure is formed by removing a top portion of the insulating layer corresponding to the contact pad through a multi-step etching process to form a through-hole opening.

[0010] In some embodiments, the semiconductor structure may include a half-hole opening formed by leaving a remaining insulating layer in the through-hole opening before the last etching step of the multi-step etching process.

[0011] In some embodiments, the semiconductor structure further includes a mask layer disposed on the insulating layer, wherein the mask layer forms a plurality of mask layer openings in the multi-step etching process for exposing the top of the insulating layer corresponding to the contact pad from the mask layer.

[0012] In some embodiments, in the semiconductor structure, the insulating layer not exposed from the mask layer opening forms a sharp edge relative to the via opening.

[0013] In some embodiments, the semiconductor structure further includes a patterned mask layer disposed on the insulating layer, wherein the patterned mask layer has a plurality of mask layer openings for exposing the top portion of the insulating layer corresponding to the contact pad from the mask layer.

[0014] The present disclosure also provides a method for manufacturing a semiconductor structure. The method includes the following steps: providing a semiconductor wafer having an active surface and an inactive surface facing each other, wherein a plurality of contact pads are formed on the active surface; disposing an insulating layer on the active surface of the wafer to cover the active surface of the wafer and the contact pads; and forming a through-hole opening in the insulating layer to expose the contact pads from the insulating layer without damaging the contact pads.

[0015] In some embodiments, the method further comprises forming an adhesion promoting layer between the active surface of the wafer and the insulating layer for adhering the insulating layer to the active surface of the wafer.

[0016] In some embodiments, the method, wherein the step of forming a through-hole opening in the insulating layer further includes: performing at least one etching step for partially removing the top of the insulating layer corresponding to the contact pad to form a half-hole opening, wherein a remaining insulating layer is left in the half-through-hole opening; and performing a final etching step for removing the remaining insulating layer in the half-hole opening, thereby exposing the contact pad from the insulating layer.

[0017] In some embodiments, the method, wherein the at least one etching step and the final etching step are performed using a high-power laser etching process and a low-power laser etching process, respectively.

[0018] In some embodiments, the method further comprises, after the final etching step, removing residues of the remaining insulating layer in the through-hole opening using a plasma process.

[0019] In some embodiments, the method, wherein the at least one etching step and the final etching step are performed using a high power laser etching process and a plasma process, respectively.

[0020] In some embodiments, the method further includes: before the at least one etching step, setting a mask layer on the insulating layer to completely cover the insulating layer, wherein the mask layer is etched to form a plurality of mask layer openings for exposing the top of the insulating layer corresponding to the contact pad; and removing the mask layer from the insulating layer after the last etching step.

[0021] In some embodiments, the method further includes: before the at least one etching step, providing a patterned mask layer on the insulating layer to expose the top of the insulating layer corresponding to the contact pad; and removing the patterned mask layer from the insulating layer after the last etching step.

[0022] In some embodiments, the method further comprises dividing the semiconductor wafer into a plurality of individual semiconductor dies, wherein the insulating layer remains on each individual semiconductor die and has at least one of the through-hole openings therein.

[0023] The present disclosure also provides a two-step etching method for fabricating a semiconductor grain having an active grain surface into a grain structure. At least one through-hole opening is formed in an insulating layer on the active grain surface, and a contact pad located on the active grain surface and covered by the insulating layer is exposed from the insulating layer through the at least one through-hole opening. The two-step etching process includes the following steps: performing a first etching step to partially remove a top portion of the insulating layer corresponding to the contact pad, wherein a residual insulating layer remains in the at least one through-hole opening; and performing a second etching step to remove the residual insulating layer in the at least one through-hole opening, thereby exposing the contact pad from the insulating layer.

[0024] In some embodiments, the two-step etching method further comprises forming an adhesion promoting layer between the active surface of the die (chip) and the insulating layer for adhering the insulating layer to the active surface of the die.

[0025] In some embodiments, the two-step etching method further includes: before the first etching step, setting a mask layer on the insulating layer to completely cover the insulating layer, wherein in the first etching step, the mask layer is etched to have at least one mask layer opening corresponding to the at least one through-hole opening; and after the second etching step, removing the mask layer from the insulating layer.

[0026] In some embodiments, the two-step etching method further includes: before the first etching step, setting a patterned mask layer on the insulating layer, wherein the patterned mask layer has at least one mask layer opening corresponding to the at least one through-hole opening; and after the second etching step, removing the patterned mask layer from the insulating layer.

[0027] By referring to the following description and drawings, the advantages and features of the embodiments disclosed herein will become apparent.In addition, it should be understood that the features of the various embodiments described herein are not mutually exclusive and can exist in various combinations and permutations. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and form a part of the specification, wherein like numerals represent like parts, illustrate preferred embodiments of the present disclosure and, together with the description, serve to explain the principles of the various embodiments of the invention.

[0029] Figure 1 is a flow chart of a two-step etching process for a wafer according to an exemplary embodiment of the present disclosure;

[0030] Figures 2a to 2m According to an exemplary embodiment of the present disclosure, Figure 1 Schematic diagram of a two-step etching process for fabricating a semiconductor structure;

[0031] Figures 3a to 3f According to another exemplary embodiment of the present invention, using Figure 1 Schematic diagram of a two-step etching process for manufacturing a semiconductor structure with a mask layer;

[0032] Figures 4a to 4e According to another exemplary embodiment of the present invention, using Figure 1 Schematic diagram of a two-step etching process for fabricating a semiconductor structure with a patterned mask layer;

[0033] Figure 5 are images of a top view and a simplified cross-sectional view of a portion of an exemplary embodiment of a processed semiconductor wafer.

[0034] Figures 6a to 6c An embodiment of a process for forming a capping layer on a processed semiconductor wafer and forming a via opening in the capping layer is disclosed.

[0035] Figures 7a and 7b Another embodiment of a process for forming a via opening in a capping layer over a processed wafer.

[0036] Figures 8a to 8d

[0014] Yet another embodiment of a process for forming a via opening in a capping layer over a processed wafer.

[0037] Figures 9a to 9c

[0014] Another embodiment of a process for forming a via opening in a capping layer over a processed wafer.

[0038] Figure 10 is a flow chart of a two-step etching process for a die according to an exemplary embodiment of the present disclosure;

[0039] Figures 11a to 11d For the embodiment of the present invention, use Figure 10 Schematic diagram of the two-step etching process for producing grain structure;

[0040] Figures 12a to 12d In another embodiment of the present invention, using Figure 10 Schematic diagram of a two-step etching process with a mask layer to produce a grain structure;

[0041] Figures 13a to 13d In another embodiment of the present invention, using Figure 10 Schematic diagram of the two-step etching process with a patterned mask layer to produce a grain structure.

[0042] Reference numerals:

[0043] 10: (Wafer) two-step etching process, 11: (Die) two-step etching process, 12: First etching step, 14: Second etching step, 20: High-power laser etcher, 30: Low-power laser etcher, 40: Plasma etcher, 100: Wafer, 100a: Wafer center, 100b: Wafer edge, 1001: Wafer active side, 1002: Wafer inactive side (wafer back side), 101: Adhesion-promoting layer, 103: Contact pad (die pad), 105: Dielectric layer, 107: Protective layer, 107a: (Protective layer) top, 107b: (Protective layer) bottom, 107c: Sharp edge, 107d: Etched edge, 108: Remaining protective layer, 109: Protective layer opening, 110: Protective layer Layer half-opening, 110a: protective layer half-opening at the center of the wafer, 110b: protective layer half-opening at the edge of the wafer, 112: protective layer residue, 113: die, 1131: active side of the die, 1132: back side of the die, 114: mask layer, 115: mask layer opening, 116: patterned mask layer, 118: mask layer sheet, 150: semiconductor structure, 152: die structure, 155: semiconductor structure, 200: processed semiconductor wafer (processed wafer), 201: semiconductor wafer (wafer), 202: active or top wafer side, 203: inactive or bottom wafer side, 210: die (device), 230: back-end-of-line (BEOL) dielectric stack, 240: passivation layer, 242: Die bond pad, 248: pad opening, 300: processed semiconductor wafer (processed wafer), 301: wafer, 302: wafer active side, 303: wafer inactive side, 310: die (device), 330: back-end-of-line (BEOL) dielectric stack, 340: passivation layer, 342: die bond pad, 348: pad opening, 350: (composite) capping layer, 356: erosion, 360: via half-opening, 362: sloped sidewall / via half-opening sidewall / via opening upper sidewall, 364: via opening lower sidewall, 368: bottom surface, 370: via opening, 400: processed wafer, 410: die, 430: BEOL dielectric stack, 442: die bond pad, 444: passivation layer, 44 8: Pad opening, 450: Covering layer, 460: Via half opening, 462: Sloped sidewall / Via upper sidewall, 464: Via lower sidewall, 470: Via opening, 500: Processed wafer, 501: Wafer, 502: Wafer active side, 503: Wafer inactive side, 510: Die, 530: Back-end-of-line (BEOL) dielectric stack, 540: Passivation layer, 542: Die bond pad, 548: Pad opening, 550: Covering layer, 560: Via half opening, 562: Sloped sidewall / Via upper sidewall, 564: Via lower sidewall, 570: Via opening, 590: Mask layer, 600: Processed wafer, 610: Die, 630: Back-end-of-line (BEOL) dielectric stack,642: Die bonding pad, 644: Passivation layer, 650: Covering layer, 660: Via half-opening, 662: Sloped sidewall / upper sidewall of via opening, 670: Via opening, 690: Mask layer, T: Flat thickness of protective layer / covering layer, T': Curved thickness of protective layer, D: Depth of via half-opening, R: Flat thickness of remaining protective layer / remaining covering layer, R': Curved thickness of remaining protective layer, PT: Thickness of protective layer etched by plasma, MT: Mask thickness. DETAILED DESCRIPTION

[0044] Embodiments generally relate to devices, such as semiconductor devices or integrated circuits (ICs). In particular, the present disclosure relates to a wafer having an insulating layer with through-hole openings for exposing contact pads (also known as die pads or die bond pads) located on an active surface of the wafer without damaging the contact pads. Figures 1 to 4e and Figures 10 to 13d In the Figures 5 to 9c It is called the covering layer.

[0045] Figure 1 is a flow chart of a two-step etching process 10 according to an exemplary embodiment of the present disclosure. Figures 2a to 2m is in accordance with Figure 1 , which is a flow chart illustrating a semiconductor structure 150 fabricated using a two-step etching process 10 .

[0046] refer to Figures 2a to 2m , the two-step etching process 10 in an embodiment according to the present disclosure includes the following steps.

[0047] Step S1: providing a wafer 100 .

[0048] like Figure 2a As shown, a wafer 100 is provided; wafer 100 has an active surface 1001 and an inactive surface (also known as the backside of the wafer) 1002. Wafer 100 includes a plurality of crystal grains 113, with the active surfaces of crystal grains 113 constituting the active surface 1001. Active and passive components are formed on the active surface of each crystal grain 113 in wafer 100 through a series of processes such as doping, deposition, and etching. Active components include diodes and transistors, while passive components include voltage elements, capacitors, resistors, and inductors. These active and passive components are connected via wiring to form functional circuits to implement various functions.

[0049] The wafer active surface 1001 also includes contact pads (also known as die pads or die bonding pads) 103 that connect to active and / or passive components to lead to functional circuits; and a dielectric layer 105 for protecting the contact pads 103. The contact pads 103 are typically made of a metal, such as aluminum (Al), copper (Cu), an aluminum-copper alloy, or a combination thereof. Therefore, the contact pads 103 are easily etched or damaged by conventional chemical and / or physical etching processes, such as high-power laser etching, radial etching, reactive ion etching, sputtering, ion milling, ion beam assisted etching, and reactive ion beam etching. The dielectric layer 105 is typically made of silicon dioxide (SiO2) and silicon nitride (Si3N4), which insulates the contact pads 103.

[0050] Step S2: applying a protective layer 107 to cover the active surface 1001 of the wafer.

[0051] like Figure 2b As shown, a protective layer 107 is applied to and covers the wafer active surface 1001. The protective layer 107 electrically insulates the contact pads 103 on the wafer active surface 1001 of the wafer 100. In other words, the protective layer 107 is a type of insulating layer in the present invention.

[0052] Depending on the specific material of the protective layer 107, it can be formed on the wafer active surface 1001 of the wafer 100 by any appropriate method. In one embodiment, the protective layer 107 is a sheet or film material and is applied to the wafer active surface 1001 by lamination, such as vacuum lamination or roller lamination. The sheet or film material is then pressed onto the wafer 100 and cured, thereby fixing the protective layer 107 on the wafer active surface 1001. Alternatively, the protective layer 107 in a granular or liquid state can be applied to the wafer active surface 1001 by compression molding. Alternatively, if the protective layer 107 is in a liquid state, it can be applied to the wafer active surface 1001 by spin coating or slit die coating.

[0053] In a preferred embodiment, the protective layer 107 is an organic / inorganic composite material layer, including an organic substrate (e.g., polyimide, epoxy resin, Ajinomoto buildup film (ABF)) and an inorganic filler or filler particles. The filler particles can be inorganic oxide particles. For example, the filler particles are silica (SiO2) particles. In one embodiment, the filler particles in the protective layer 107 are two or more different types of inorganic oxide particles, such as silica (SiO2) particles and titanium dioxide (TiO2) particles mixed with each other. Preferably, the filler particles in the protective layer 107, such as inorganic oxide particles, are spherical or spheroidal. In a preferred embodiment, the filler particles in the protective layer 107, such as inorganic oxide particles, have a filling amount of 50% or more.

[0054] The protective layer 107 may have a flat thickness T across the entire active surface 1001 of the wafer 100. In one embodiment, the flat thickness T of the protective layer 107 is in the range of 10-100 microns (μm), 15-100 microns, 20-100 microns, 25-100 microns, 45-100 microns, or 60-100 microns. In a preferred embodiment, the flat thickness T of the protective layer 107 is in the range of 20-45 microns (μm). The flat thickness T of the protective layer 107 may have a tolerance of plus or minus (±) 1-5 μm, which also depends on the flat thickness T of the protective layer 107.

[0055] Or, as Figure 2c As shown, if the wafer 100 has a larger size, such as 6 inches, 8 inches, 12 inches or larger. The arc thickness T' gradually becomes thinner from the wafer center 100a of the wafer 100 to the wafer edge 100b of the wafer 100. The total thickness variation (TTV) can be used to represent the difference between the maximum value of the arc thickness T' at the wafer center 100a of the wafer 100 and the minimum value at the wafer edge 100b of the wafer 100. In one embodiment, the total thickness variation (TTV) can be in the range of 1-6 microns, 2-6 microns, 3-6 microns, 4-6 microns or 5-6 microns. In a preferred embodiment, the total thickness variation TTV is about 2 microns.

[0056] exist Figure 2b Afterwards, an adhesion promoting layer 101 may be applied between the wafer active surface 1001 of the wafer 100 and the protective layer 107 having a flat thickness T to enhance the adhesion of the protective layer 107 to the wafer active surface 1001. Figure 2d As shown. Similarly, in Figure 2cAfterwards, the adhesion promoting layer 101 may also be applied between the wafer active surface 1001 of the wafer 100 and the protective layer 107 having an arc-shaped thickness T', as shown in FIG. Figure 2e shown.

[0057] In some embodiments, adhesion-promoting layer 101 has organic groups with affinity for organic substances and inorganic groups with affinity for inorganic substances. Thus, adhesion-promoting layer 101 is bonded to protective layer 107 by generating bonding forces between the organic groups of adhesion-promoting layer 101 and the organic substrate of protective layer 107. Simultaneously, adhesion-promoting layer 101 is bonded to wafer active surface 1001 by generating bonds between the inorganic groups of adhesion-promoting layer 101 and the silicon or doped silicon material on wafer active surface 1001. Furthermore, if fillers or filler particles are exposed to the organic substrate and directly contact adhesion-promoting layer 101, bonding forces can also be generated between the inorganic groups of adhesion-promoting layer 101 and the fillers or filler particles (e.g., silicon dioxide particles and titanium dioxide particles) of protective layer 107.

[0058] Adhesion promoting layer 101 is insulated from contact pad 103 and thus does not interfere with the electrical function of wafer 100. In one embodiment, adhesion promoting layer 101 optionally includes silane or its chemical derivatives, such as tetrahydride, binary silicon-hydrogen compounds, organosilocon compounds, including but not limited to trichlorosilane, tetramethylsilane and tetraethoxysilane. Other chemicals or compounds having similar properties to silane or its chemical derivatives may also be used as adhesion promoting layer 101 in the present disclosure. Silane or its chemical derivatives can be formed using any suitable method, including but not limited to a spin coating process, a spray coating process, a slit die coating process or a screen printing process.

[0059] The two-step etching process 10 can also be applied to a wafer 100 having only a protective layer 107 (e.g. Figure 2b or Figure 2c ) or a wafer 100 having a protective layer 107 and an adhesion promoting layer 101 (as shown Figure 2d or Figure 2e shown). Figure 2f to Figure 2mThe wafer 100 (eg, Figure 2b or Figure 2c The two-step etching process 10 is performed as shown in FIG. 1 , thereby simplifying the description of the two-step etching process 10. It should be understood that the two-step etching process 10 of the present invention is also applicable to a substrate having a protective layer 107 and an adhesion promoting layer 101 (as shown in FIG. Figure 2d or Figure 2e Wafer 100 as shown).

[0060] Step S3: performing the first etching step 12 to form a protective layer half opening 110 in the protective layer 107. When the protective layer 107 is used as the insulating layer, the protective layer half opening 110 can be used as a type of through hole opening in the present invention.

[0061] Reference Figure 2f ,like Figure 2b As described above, the first etching step 12 is performed on the protective layer 107 using a first etching apparatus to remove the top portion 107a of the protective layer 107 corresponding to the contact pad 103, thereby forming a protective layer semi-opening 110 in the protective layer 107. Therefore, the bottom portion 107b of the protective layer 107 remains within the protective layer semi-opening 110, referred to as the remaining protective layer 108, which covers the contact pad 103 and is therefore not damaged during the first etching step 12. When the protective layer 107 serves as the insulating layer, the remaining protective layer 108 is a type of remaining insulating layer in this embodiment.

[0062] The protective layer half opening 110 has a depth D. The remaining protective layer 108 has a planar thickness R, which can be calculated by subtracting the depth D of the protective layer half opening 110 from the thickness T of the protective layer 107. The remaining protective layer 108 having the planar thickness R will be removed in the second etching step 14 of the two-step etching process 10 described below.

[0063] In one embodiment, the first etching device includes a high-power laser etcher 20 having a normal energy (E) and a normal pulse number (P). For example, the normal energy (E) of the high-power laser etcher 20 is in the range of 1-2 joules, 1.2-2 joules, 1.4-2 joules, 1.6-2 joules, or 1.8-2 joules. In a preferred embodiment, the normal energy (E) of the high-power laser etcher 20 is in the range of 1.2-1.5 joules.

[0064] In one embodiment, the normal pulse number (P) of the high power laser etcher 20 is in the range of 5-20 pulses, 7-20 pulses, 9-20 pulses, 11-20 pulses, 13-20 pulses, 15-20 pulses or 17-20 pulses. In a preferred embodiment, the normal pulse number (P) of the high power laser etcher 20 is in the range of 7-10 pulses.

[0065] It can be understood that in order to remove the top 107a of the protective layer 107, the normal energy (E) and the normal pulse number (P) of the high-power laser etcher 20 are related. The higher the normal energy (E) from the high-power laser etcher 20, the fewer the normal pulse number (P) required to remove the top 107a of the protective layer 107. Conversely, the lower the normal energy (E) from the high-power laser etcher 20, the more normal pulse number (P) required to remove the top 107a of the protective layer 107. It can also be understood that the normal energy (E) and the normal pulse number (P) of the high-power laser etcher 20 need to be selected according to the specific material of the protective layer 107. In order to remove a certain thickness of the protective layer 107, in some embodiments, the normal energy (E) and the normal pulse number (P) may have a linear relationship; while in other embodiments, the normal energy (E) and the normal pulse number (P) may have a nonlinear relationship. For example, if the protective layer 107 is formed using Ajinomoto buildup film (ABF), the high-power laser etcher 20 can remove a thickness of 2 microns with one pulse when the normal energy (E) is 1.2 joules; and the high-power laser etcher 20 can remove a thickness of 2.8 microns with one pulse when the normal energy (E) is 2 joules.

[0066] Thus, the remaining protective layer 108 remains in the protective layer half-opening 110. Optionally, the first etching step 12 is performed in a uniform manner so that the thickness R of the remaining protective layer 108 is substantially flat across the entire wafer active surface 1001 of the wafer 100. Optionally, the flattened thickness R of the remaining protective layer 108 is within a range of 1-8 microns, 2-8 microns, 3-8 microns, 4-8 microns, 5-8 microns, 6-8 microns, or 7-8 microns. In a preferred embodiment, the flattened thickness R of the remaining protective layer 108 is approximately 2 microns.

[0067] Similarly, we can Figure 2d The protective layer 107 and the adhesion promoting layer 101 are subjected to the first etching step 12 to form a protective layer half opening 110. Therefore, the contact pad 103 is covered by the adhesion promoting layer 101 and the remaining protective layer 108.

[0068] refer to Figure 2g , the first etching step 12 can also be Figure 2c The protective layer 107 having an arc-shaped thickness T' is formed by using a first etching device (such as a high-power laser etcher 20) to form a protective layer half opening 110. Although the first etching step 12 is still performed in a uniform manner, the remaining protective layer 108 is also formed according to the Figure 2cIn other words, if the first etching step 12 is performed uniformly across the entire active surface 1001 of the wafer 100, the arc-shaped thickness R' of the remaining protective layer 108 gradually decreases from the wafer center 100a of the wafer 100 to the wafer edge 100b of the wafer 100. For example, the remaining protective layer 108 in the protective layer half-opening 110a at the wafer center 100a of the wafer 100 is thicker by approximately the total thickness variation TTV than the remaining protective layer 108 in the protective layer half-opening 110b at the wafer edge 100b of the wafer 100.

[0069] Similarly, we can Figure 2e The protective layer 107 with the adhesion promoting layer 101 is subjected to the first etching step 12 to form a protective layer half opening 110. Therefore, the contact pad 103 is covered by the adhesion promoting layer 101 and the remaining protective layer 108; Figure 2c With the total thickness variation TTV in FIG, the remaining protective layer 108 has a curved thickness R′.

[0070] The laser light emitted by the high power laser etcher 20 has excellent directivity; thus, only the top portion 107a of the protective layer 107 corresponding to the contact pad 103 can be removed, so as to avoid etching away the protective layer 107 outside the protective layer half opening 110. Figure 2f and Figure 2g As shown, at the intersection of the protective layer 107 and the protective layer half-opening 110 , the protective layer 107 therefore has a sharp edge 107 c.

[0071] The high-power laser etcher 20 can quickly perform the first etching step 12 to save processing time, thereby improving the productivity of the two-step etching process 10 in the present disclosure.

[0072] The protective layer half-opening 110 can have any shape depending on the specific design of the semiconductor structure 150. In a preferred embodiment, the protective layer half-opening 110 is circular to facilitate the first etching step 12. The protective layer half-opening 110 can have any size depending on the specific design of the semiconductor structure 150. However, its size should not be too small so as to affect the filling of the conductive material in the subsequent steps (not shown) after the two-step etching process 10.

[0073] Step S4: performing the second etching step 14 to form a protective layer opening 109 in the protective layer 107. When the protective layer 107 is an insulating layer, the protective layer opening 109 is a through hole opening in the embodiment of the present invention.

[0074] like Figure 2fAs described above, the second etching step 14 is performed on the protection layer 107 , using a second etching device to remove the bottom 107 b of the protection layer 107 , that is, to remove the remaining protection layer 108 in the protection layer half opening 110 . Therefore, a protection layer opening 109 is formed in the protection layer 107 .

[0075] Reference Figure 2h In one embodiment, the second etching device includes a low-power laser etcher 30 having low energy (E) and a small number of pulses (P). For example, the low energy (E) of the low-power laser etcher 30 is in the range of 0.3-0.6 joules, 0.4-0.6 joules, or 0.3-0.5 joules. In a preferred embodiment, the low energy (E) of the low-power laser etcher 30 is in the range of 0.3-0.4 joules. In another preferred embodiment, the low energy (E) of the low-power laser etcher 30 is in the range of 0.5-0.6 joules.

[0076] In one embodiment, the number of pulses (P) from the low-power laser etcher 30 is determined by the planarization thickness R and the specific material of the remaining protective layer 108. For example, if the protective layer 107 is formed of Ajinomoto buildup film (ABF), if the low energy (E) is set to 0.3-0.4 joules, the low-power laser etcher 30 can remove a thickness of 1 micron with one pulse; and if the low energy (E) is set to 0.5-0.6 joules, the low-power laser etcher 30 can remove a thickness of 1.3 microns with one pulse.

[0077] It should be understood that the higher the low energy (E) of the low-power laser etcher 30, the fewer the number of pulses (P) required to remove the bottom 107b of the protective layer 107, and the faster the second etching step 14 is performed, thereby saving processing time and thus improving productivity. However, the low energy (E) of the low-power laser 30 should not be too high to damage the contact pad 103.

[0078] The high-power laser etcher 20 and the low-power laser etcher 30 can respectively use pulsed ultraviolet (UV) lasers of the same wavelength to respectively carry out the first etching step 12 and the second etching step 14. For example, the pulsed ultraviolet (UV) laser is an excimer laser (Excimer laser) using compounds such as rare gases and halogens as laser media, such as an ArF excimer laser with a wavelength of 193 nanometers (nm), a KrF excimer laser with a wavelength of 248 nanometers (nm), a XeCl excimer laser with a wavelength of 308 nanometers (nm), or a XeF excimer laser with a wavelength of 351 nanometers (nm). In a preferred embodiment, the wavelength of the excimer laser is 355 nanometers to carry out the two-step etching process 10, i.e., forming a protective layer half opening 110 in the first etching step 12 and forming a protective layer opening 109 in the second etching step 14.

[0079] Similar to the high power laser etcher 20, the laser light emitted from the low power laser etcher 30 may also have excellent directivity; and thus Figure 2h The sharp edge 107c is retained in the second etching step 14. The sharp edge 107c can advantageously meet the production specifications of electronic products produced using the two-step etching process 10.

[0080] Step S5: Remove the protective layer residue 112 from the protective layer opening 109. Figure 1 The dotted squares are used to indicate that step S5 is an unnecessary additional process in the two-step etching process 10 .

[0081] Reference Figure 2i , the protective layer 107 may not be completely removed from the protective layer opening 109; the portion of the protective layer 107 remaining in the protective layer opening 109 is referred to as the protective layer residue 112. An additional process is required to completely remove the protective layer residue 112 from the protective layer opening 109 so that the contact pad 103 is completely exposed from the protective layer 107.

[0082] Optionally, an additional process is performed using an etching technique with a slower etching rate to protect the contact pad 103 from being damaged. In one embodiment, the additional process for removing the protective layer residue 112 uses plasma etching, including but not limited to carbon tetrafluoride (CF4) gas plasma etching, sulfur tetrafluoride (SF4) gas plasma etching, oxygen (O2) gas plasma etching, argon (Ar) gas plasma etching, or any combination thereof.

[0083] Plasma etching does not have superior directionality compared to the laser light emitted from the high-power laser etcher 20 or the low-power laser etcher 30 , and thus also etches away the sharp edge 107 c to form an etched edge 107 d .

[0084] refer to Figure 2j , forming a semiconductor structure 150 including a wafer 100 and a protective layer 107 having a protective layer opening 109. The semiconductor structure 150 is cut along the cutting line to obtain a plurality of grain structures 152. The grain structure 152 includes a grain 113, the grain 113 having a grain active surface 1131 and a grain back surface 1132, and a protective layer 107 formed on the grain active surface 1131 of the grain 113, which has a protective layer opening 109. Figure 2j In the embodiment, if no protective layer residue 112 is left after the second etching step 14 using the low power laser etcher 30, the sharp edge 107c is retained to the grain 113. In contrast, if Figure 2iAfter an additional process to remove the protective layer residue 112 , the semiconductor structure 150 will have an etched edge 107 d in the protective layer 107 .

[0085] It should be understood that by using the low power laser etcher 30 as described above, the second etching step 14 (including Figure 2i Additional process in Figure 2g By completely removing the remaining protective layer 108 from the protective layer half opening 110, a semiconductor structure (not shown) similar to the semiconductor structure 150 can be obtained, but the protective layer 107 has a total thickness variation TTV. Of course, the total thickness variation TTV of the protective layer 107 can be further removed to form a semiconductor structure (not shown). Figure 2j The semiconductor structure 150 in FIG.

[0086] refer to Figure 2k . Alternative Figure 2h The low-power laser etcher 30 in the second etching device may include a plasma etcher 40 for performing the second etching step 14 to remove the remaining protective layer 108 from the protective layer half opening 110 to form a protective layer opening 109. As described in the additional process of step S5, the etching speed of plasma etching is slow, so it will not damage the contact pad 103. Plasma etching includes but is not limited to carbon tetrafluoride (CF4) gas plasma etching, sulfur tetrafluoride (SF4) gas plasma etching, oxygen (O2) gas plasma etching, argon (Ar) plasma etching, or a combination thereof.

[0087] exist Figure 2h In the second etching step 14 shown, since the laser light emitted from the low-power laser etcher 30 has excellent directivity, the low-power laser etcher 30 only removes the remaining protective layer 108 in the protective layer half opening 110, and does not etch the protective layer 107 outside the protective layer half opening 110. In contrast, the plasma emitted from the plasma etching device 40 not only removes the remaining protective layer 108 in the protective layer half opening 110, but also etches away the protective layer 107 outside the protective layer half opening 110. Figure 2k As shown, the protective layer 107 on the active surface 1001 of the wafer can be uniformly plasma-etched, and a certain thickness PT of the protective layer 107 outside the protective layer half-opening 110 is etched by the plasma generated by the plasma etcher 40 in the second etching step 14. Therefore, after the second etching step 14 is performed using the plasma etcher 40, the protective layer 107 has a thickness equal to T-TP.

[0088] The thickness PT of the protective layer 107 can be related to the flattened thickness R of the remaining protective layer 108. In one embodiment, the thickness PT is about 10% to 30% greater than the flattened thickness R of the remaining protective layer 108. The thickness PT can be about 15% to 30% greater than the flattened thickness R, about 10% to 25% greater than the flattened thickness R, or about 15% to 25% greater than the flattened thickness R. In a preferred embodiment, the thickness PT of the protective layer 107 is about 20% greater than the flattened thickness R of the remaining protective layer 108.

[0089] Furthermore, since the plasma emitted from the plasma etcher 40 does not have the superior directivity of the laser light emitted from the low-power laser etcher 30 , the sharp edge 107 c formed in the first etching step 12 is also etched and accordingly forms an etched edge 107 d .

[0090] refer to Figure 2l Compared to using a low-power laser etcher 30, using a plasma etcher 40 in the second etching step 14 can completely remove the remaining protective layer 108 in the protective layer half opening 110 without leaving any protective layer residue 112. Accordingly, the thickness T of the protective layer 107 is reduced by the thickness PT etched away by the plasma in the second etching step 14.

[0091] refer to Figure 2m , forming a semiconductor structure 150 including a wafer 100 and a protective layer 107 having a protective layer opening 109. The semiconductor structure 150 is cut along the cutting line to obtain a plurality of grain structures 152. The grain structure 152 includes a grain 113, the grain having a grain active surface 1131 and a grain back surface 1132, and the protective layer 107 is formed on the grain active surface 1131 of the grain 113 and has the protective layer opening 109. Figure 2m As shown, after dicing, the die 113 still retains the etched edges 107 d formed by the plasma etcher 40 in the second etching step 14 .

[0092] It should be understood that the second etching step 14 of the two-step etching process 10 is also applicable to a wafer 100 having a protective layer 107 and an adhesion promoting layer 101 (e.g., Figure 2d or Figure 2e As shown), in the second etching step 14, the adhesion promoting layer 101 (eg, silane) can also be completely removed from the protective layer opening 109 by the low-power laser etcher 30 or the plasma etcher 40.

[0093] Figures 3a to 3f is a schematic diagram of manufacturing a semiconductor structure 150 using a two-step etching process 10 according to another exemplary embodiment of the present disclosure.

[0094] like Figure 3a and Figure 3bAs shown in FIG, the same steps S1 and S2 are performed in this embodiment. Therefore, the same reference numerals are used here to describe the same steps. Figure 2a and Figure 2b the same or similar features.

[0095] S3 ′: applying a mask layer 114 on the protective layer 107 .

[0096] Reference Figure 3c The mask layer 114 covers the protection layer 107 and is used to protect the protection layer 107 outside the protection layer opening 109 or not corresponding to the protection layer opening 109 so that the protection layer 107 is not etched in the two-step etching process 10 .

[0097] The mask layer 114 may be made of a metal material, such as copper (Cu), titanium (Ti), nickel (Ni), an alloy of copper, titanium and nickel, or any combination thereof. The mask layer 114 made of a metal material may be formed by a sputtering process, a plating process, or a combination thereof. Alternatively, the mask layer 114 may be made of a non-metallic material, including non-photoimagable etch resist polymers. The mask layer 114 made of a non-metallic material may be formed by a laminating process. Alternatively, the mask layer 114 may be made of any combination of a metal material and a non-metallic material. In addition, the mask layer 114 may include a single layer or a multi-layer stack, which may be made of a metal material, a non-metallic material, or any combination thereof.

[0098] Depending on the specific material of the mask layer 114, the mask layer 114 may have a uniform mask thickness MT. For example, if the mask layer 114 is made of copper (Cu), the mask thickness MT of the mask layer 114 may be in the range of 0.3-1 micrometers (μm), 0.5-1 micrometers (μm), 0.7-1 micrometers (μm), or 0.9-1 micrometers (μm). In a preferred embodiment, the mask thickness MT of the mask layer 114 is approximately 0.6 micrometers (μm).

[0099] Step S4': Perform the first etching step 12 to form a protective layer half opening 110 in the protective layer 107 and simultaneously form a patterned mask layer 116 having a mask layer opening 115. Step S4' is similar to step S3 above; the same reference numerals are used to describe the same or similar features.

[0100] Please refer to Figure 3d, the protective layer 107 is subjected to a first etching step 12 by a high-power laser etcher 20 to form a protective layer half opening 110. In addition to the protective layer 107, the laser from the high-power laser etcher 20 can also etch the mask layer 114 to form a mask layer opening 115. As a result, the mask layer 114 becomes a patterned mask layer 116 having the mask layer opening 115.

[0101] Alternatively, the first etching step 12 can be divided into two sub-steps (not shown). In the first sub-step, the laser light emitted from the high-power laser etcher 20 is strong enough to form the mask layer opening 115 in the mask layer 114; and then in the second sub-step, the high-power laser etcher 20 is adjusted to reduce the normal energy (E) for etching the top 107a of the protective layer 107, thereby forming the protective layer half opening 110.

[0102] Step S5': performing the second etching step 14 to form a protective layer opening 109 in the protective layer 107. Step S5' is similar to step S4; the same reference numerals are used to describe the same or similar features.

[0103] Reference Figure 3e The second etching step 14 is performed using a plasma etcher 40 to remove the remaining protection layer 108 exposed from the protection layer half opening 110 without damaging the contact pad 103 .

[0104] Similar to Figure 2k The plasma generated from the plasma etcher 40 completely removes the remaining protective layer 108 exposed from the mask layer opening 115 without leaving protective layer residue 112 in the protective layer opening 109. At the same time, the patterned mask layer 116 protects the protective layer 107 outside the protective layer opening 109 from being plasma etched. Figure 2k In contrast, the flat thickness T of the protection layer 107 is not etched away by the thickness PT in the second etching step 14. In addition, due to the protection provided by the patterned mask layer 116, the sharp edge 107c formed in the first etching step 12 is also retained after the second etching step 14.

[0105] The patterned mask layer 116 in step S5' provides multiple advantages. On the one hand, due to the use of the plasma etcher 40, no Figure 2i On the other hand, the protective layer 107 outside the protective layer opening 109 is not etched, thereby providing sufficient protection for the wafer active surface 1001 of the wafer 100 and the die active surface 1131 of the die 113 in the subsequent processes after dicing. In addition, the sharp edge 107c meets the product specifications of the final electronic product produced by the semiconductor structure 150. In other words, the sharp edge 107c can be better controlled. Figure 3eThe second etching step 14 is used to remove the remaining protection layer 108 without causing unnecessary damage.

[0106] Step S6 ′: removing the patterned mask layer 116 from the protection layer 107 .

[0107] Depending on the material of mask layer 114, patterned mask layer 116 can be removed from protective layer 107 by any known process, such as a mechanical process, a chemical process, or any combination thereof. For example, if mask layer 114 is made of a metal material, such as copper (Cu), titanium (Ti), nickel (Ni), a copper-titanium-nickel alloy, or any combination thereof, patterned mask layer 116 can be removed by immersing or soaking semiconductor structure 150 in a chemical etching solution. For example, semiconductor structure 150 can be immersed or soaked in a 5-10% by volume hydrogen peroxide (H2O2) solution for 1 to 5 minutes. Alternatively, the hydrogen peroxide solution (H2O2) can be sprayed onto patterned mask layer 116. Furthermore, a 5-10% by volume sulfonic acid solution (H2SO4) can be added to the hydrogen peroxide solution (H2O2) to accelerate the removal of patterned mask layer 116.

[0108] refer to Figure 3f .and Figure 2j Similarly, after removing the patterned mask layer 116, a semiconductor structure 150 is formed, comprising the wafer 100 and the protective layer 107 having the protective layer opening 109. Semiconductor structure 150 is cut along cutting lines to obtain a plurality of grain structures 152. Grain structures 152 include grains 113, each having a grain active surface 1131 and a grain back surface 1132, and a protective layer 107 formed on the grain active surface 1131 of the grain 113, the protective layer having the protective layer opening 109.

[0109] It should be understood that according to steps S3' to S6', the mask layer 114 is also suitable for Figure 2c The protective layer 107 is shown to have an arc-shaped thickness T'. Figure 3b Before forming the protective layer 107 , the adhesion promoting layer 101 may also be applied to the active surface 1001 of the wafer.

[0110] Figures 4a to 4e FIG. 1 is a schematic diagram of manufacturing a semiconductor structure 150 using a two-step etching process 10 according to another exemplary embodiment of the present disclosure.

[0111] like Figure 4a and Figure 4b As shown in FIG. 1 , this embodiment performs the same steps S1 and S2. Therefore, the same reference numerals are used to describe the same steps as those in FIG. Figure 2a and Figure 2b or Figure 3a and Figure 3b the same or similar features.

[0112] Step S3 ″: providing a patterned mask layer 116 having a mask layer opening 115 .

[0113] Reference Figure 4c , providing a mask layer sheet 118. The mask layer sheet 118 is made of a metal material, a non-metal material or any combination thereof, such as Figure 3c As shown. Mask layer openings 115 are fabricated in mask layer sheet 118 by any known process, thereby forming patterned mask layer 116. For example, mask layer openings 115 are formed by etching or mechanical stamping. Patterned mask layer 116 can have any shape to cover protective layer 107. In a preferred embodiment, patterned mask layer 116 has the same circular shape as wafer 100. Alternatively, patterned mask layer 116 can have the same or larger dimensions to completely cover protective layer 107 on wafer active surface 1001.

[0114] Step S4 ″: applying a patterned mask layer 116 on the protective layer 107 .

[0115] Reference Figure 4d A patterned mask layer 116 is applied on the protective layer 107 so that the plurality of mask layer openings 115 correspond to the plurality of contact pads 103 on the wafer active surface 1001 .

[0116] Then, a two-step etching process 10 is performed to form a semiconductor structure 150, including step S5'': performing a first etching step 12 to form a protective layer half opening 110 in the protective layer 107; and step S6'': performing a second etching step 14 to form a protective layer opening 109 in the protective layer 107. The execution methods of steps S5'' and S6'' are respectively the same as those of Figure 3d and Figure 3e same.

[0117] and Figure 3d Compared to step S4 ′ shown, the mask layer opening 115 can guide the high-power laser etcher 20 to remove the top portion 107 a of the protection layer 107 , so as to accurately form the protection layer half opening 110 at an accurate position on the wafer active surface 100 .

[0118] During the first etching step 12 and the second etching step 14, the protective layer 107 covered by the patterned mask layer 116 is not etched away, thereby providing sufficient protection for the wafer 100 in subsequent processes. The contact pads 103 are exposed through the protective layer openings 109 of the protective layer 107 and the mask layer openings 115 of the patterned mask layer 116 and are not damaged during the two-step etching process 10.

[0119] Step S7 ″: removing the patterned mask layer 116 from the protection layer 107 .

[0120] refer to Figure 4e , similar to Figure 3f The patterned mask layer 116 is removed from the protective layer 107 by any known process, such as mechanical process, chemical process or any combination thereof, depending on the specific material of the mask layer 114. The sharp edge 107c may also be retained during the removal of the patterned mask layer 116.

[0121] A semiconductor structure 150 is formed, comprising a wafer 100 and a protective layer 107 having a protective layer opening 109. Semiconductor structure 150 is cut along cutting lines to obtain a plurality of grain structures 152. Grain structure 152 includes a grain 113 having a grain active surface 1131 and a grain back surface 1132, and a protective layer 107 formed on the grain active surface 1131 of the grain 113, having a protective layer opening 109.

[0122] Although a two-step etching process 10 is described in the embodiment, it should be understood that the semiconductor structure 150 may also be formed by a multi-step etching process according to the same principles as the two-step etching process 10. In the present disclosure, in the final etching step of the multi-step etching process, in order to avoid damaging the contact pad 103, an appropriate etching device is used to etch away the remaining protective layer 108 in the protective layer half opening 110.

[0123] For example, the multi-step etching process can be a three-step etching process to form the semiconductor structure 150: first, an initial etching step is performed to remove an initial portion of the protective layer 107; then, an intermediate etching step is performed to remove a middle portion below the initial portion of the protective layer 107; and finally, a final etching step is performed to remove a final portion below the middle portion of the protective layer 107. In the final etching step, the final portion of the protective layer 107 is completely etched away by the low-power laser etcher 30 or the plasma etcher 40 without damaging the contact pads 103.

[0124] refer to Figures 5 to 9c , another semiconductor structure 155 is formed using the two-step etching process 10 described above.

[0125] Figure 5 2 is an image of a top view and a simplified cross-sectional view of a portion of an exemplary embodiment of a processed semiconductor wafer (also referred to as a processed wafer) 200. Processed semiconductor wafer 200 may include semiconductor wafer (also referred to as wafer) 201. Semiconductor wafer 201 may be a lightly doped p-type silicon wafer. Alternatively, semiconductor wafer 201 may be a lightly doped n-type silicon wafer. Other types of wafers may also be used. For example, wafer 201 may be a silicon carbide (SiC) wafer, a gallium nitride (GaN) wafer, a gallium arsenide (GaAs) wafer, or an indium phosphide (InP) wafer. Other types of wafers may also be useful.

[0126] Processed semiconductor wafer 200 includes a plurality of dies (also referred to as devices) 210. The dies 210 are arranged in rows along a first direction x and in columns along a second direction y. Saw streets or cutting lines (not shown) separate the rows and columns of dies 210 in the x and y directions. The cross-sectional view of a portion of processed semiconductor wafer 200 may be a simplified view of the dies 210.

[0127] Circuit components (not shown) of the die 210 of the processed wafer 200 are formed on the active or top wafer surface 202 of the semiconductor wafer 201. For example, the active wafer surface 202 can be the top wafer surface of the semiconductor wafer 201. The opposing wafer surface 203 can be referred to as the inactive or bottom wafer surface of the wafer 201. The circuit components can be formed using front-end-of-line (FEOL) processing.

[0128] A back-end-of-line (BEOL) dielectric stack 230 with interconnects (not shown) is formed on the active wafer side 202 of wafer 201. For example, the BEOL dielectric stack 230 may overlie the die 210. The interconnects of the BEOL dielectric stack 230 interconnect circuit components. The BEOL dielectric stack 230 may include multiple interconnect layers. For example, metal lines coupled to via contacts may be provided in different BEOL dielectric layers at the interconnect level of the BEOL dielectric stack 230. The BEOL dielectric layers may include low-k dielectric layers, ultra-low-k dielectric layers, and gallium nitride (GaN) and germanium (Ge) coating materials. Other types of dielectrics or dielectric layers may also be useful. Low-k dielectrics or low-k dielectric layers and ultra-low-k dielectrics or ultra-low-k dielectric layers may be collectively referred to as low-k dielectrics or low-k dielectric layers. Other types of BEOL dielectric layers may also be useful.

[0129] The top interconnect level of the BEOL dielectric stack 230 may be a pad level. The pad level includes a passivation layer 240 with a die bond pad 242 for providing external connections to circuit components. For example, the die bond pad 242 may be formed from aluminum (Al). Other types of conductive materials, such as copper (Cu), nickel (Ni), palladium (Pd), gold (Au), chromium (Cr), or combinations or alloys thereof, such as aluminum-copper (Al-Cu) alloys, may also be used to form the die bond pad 242.

[0130] For example, the passivation layer 240 can be a passivation stack. The passivation stack can include a combination of dielectric layers, such as silicon oxide and silicon nitride layers. Other types of dielectric layers may also be useful. In some embodiments, the passivation layer 240 can be formed from a single dielectric layer.

[0131] As shown, the passivation layer 240 includes a pad opening 248 for exposing the die bond pad 242. In one embodiment, the pad opening 248 is smaller than the die bond pad 242. For example, the passivation layer 240 has a top surface that is higher than the top surface of the die bond pad 242; the pad opening 248 is smaller than the die bond pad 242. As shown, the passivation layer 240 covers an edge portion of the die bond pad 242. In one embodiment, the pad opening 248 is patterned using conventional masking and etching processes. For example, the passivation layer 240 is etched using isotropic etching, such as reactive ion etching (RIE), which uses a patterned photoresist mask to form the pad opening 248. Other techniques for forming the pad opening 248 may also be useful.

[0132] The processed wafer 200 may be an imported processed wafer from an external supplier. For example, a packaging supplier may receive the processed wafer 200 from a wafer fab. The processed wafer 200 may be further processed by the packaging supplier to form individual semiconductor packages. In some cases, the processed wafer 200 may be further processed by a wafer fabrication facility with packaging capabilities.

[0133] Figures 6a to 6c is an embodiment of a process for forming a via opening in a capping layer 350 on a processed semiconductor wafer (also referred to as a processed wafer) 300. Figures 1 to 4e In the protective layer 107, the cover layer 350 is another type of insulating layer. In particular, Figure 6a is an image of a top view of a processed semiconductor wafer 300 with a capping layer 350 and a simplified cross-sectional view of a portion thereof with the capping layer 350. Figures 6b to 6c is a simplified cross-sectional view of a portion of a processed semiconductor wafer 300 having a capping layer 350. For example, Figures 6a to 6c Corresponding to the die (also referred to as device) 310 on the processed semiconductor wafer 300. The processed semiconductor wafer 300 may be similar to Figure 5 The processed semiconductor wafer 200 is described in detail. Common elements may not be described here or their details may not be described.

[0134] refer to Figure 6aFor example, a processed semiconductor wafer 300 includes circuit components (not shown) of a die 310 formed on an active wafer surface 302 of the wafer 301. An opposing surface 303 may be an inactive wafer surface. The circuit components may be formed using front-end-of-the-line (FEOL) processing. A back-end-of-the-line (BEOL) dielectric stack 330 having interconnects (not shown) is formed on the active wafer surface 302 of the wafer 301. The top interconnect level of the BEOL dielectric stack 330 may be a pad level including a passivation layer 340 having a pad opening 348 for exposing a die bond pad 342.

[0135] A capping layer 350 is disposed over the processed semiconductor wafer 300, covering the top of the BEOL dielectric stack 330. For example, the capping layer 350 is formed on top of the BEOL dielectric stack 330 of the processed semiconductor wafer 300. The capping layer 350 can be formed, for example, by a packaging vendor. Alternatively, the capping layer 350 can be formed by a foundry. Other arrangements for forming the capping layer 350 on the processed semiconductor wafer 300 may also be useful.

[0136] In one embodiment, cover layer 350 is a dielectric cover layer. Various types of dielectric materials, such as polyimide, epoxy resin, and polybenzoxazole (PBO), as well as other types of dielectric or insulating materials or combinations of insulating materials, can also be used to form cover layer 350.

[0137] In one embodiment, the cover layer 350 is a composite cover layer having a vibration damping composition or a vibration damping agent. The composite cover layer 350 has a base cover layer containing fillers or particles. In one embodiment, the base cover layer is an organic polymer matrix material. Various types of polymers can be used for the base cover layer. For example, the polymer can include thermosetting plastics or thermoplastics, such as polyimides, epoxies, and other types of polymers. In one embodiment, the base cover layer includes a resin, such as an epoxy resin or a cyanate ester. Preferably, the base cover layer is a low viscosity resin, such as a biphenyl epoxy resin.

[0138] The filler can be organic, inorganic, or a combination thereof. For example, the filler can include silica (SiO2) filler, amorphous alumina (α-Al2O3) filler, or a combination thereof. Other types of non-conductive fillers may also be useful. For example, the filler can be silica, glass beads, sand, or a combination thereof. For example, the filler can be spherical filler. The filler is a non-uniformly sized filler having a diameter of approximately 0.5–12 microns (μm) or 0.5–10 microns (μm). Other sized fillers may also be useful, including nano-sized fillers. Furthermore, the filler can have any shape. Providing non-uniformly sized fillers enables the cover layer to include a higher density of filler. For example, smaller sized fillers can fill gaps between larger sized fillers. In one embodiment, the filler concentration in the cover layer 350 is approximately 70–90 weight percent (wt%). In another embodiment, the filler concentration in the cover layer 350 is approximately 80–90 weight percent (wt%). Other filler concentrations in the cover layer 350 may also be useful.

[0139] In one embodiment, the capping layer 350 can be configured to prevent breakage and chipping of the BEOL dielectric stack 330 during dicing. Providing the capping layer 350 for other purposes may also be useful. In one embodiment, the capping layer 350 has a Young's modulus and a fracture strength to reduce or prevent breakage and chipping during wafer dicing. In one embodiment, the Young's modulus of the capping layer 350 is approximately 10,000-25,000 MPa, approximately 14,000-25,000 MPa, approximately 15,000-25,000 MPa, approximately 16,000-25,000 MPa, approximately 15,000-20,000 MPa, or approximately 20,000-25,000 MPa. The covering layer 350 may have a fracture strength of approximately 45-150 MPa, approximately 70-150 MPa, approximately 70-120 MPa, approximately 70-105 MPa, approximately 80-120 MPa, or approximately 90-100 MPa. In one embodiment, the covering layer 350 has a coefficient of thermal expansion of approximately 6-20 ppm / °C. The covering layer 350 may have temperature stability within a range of -65°C to +300°C.

[0140] In one embodiment, the thickness T of the cover layer 350 is approximately 10-100 micrometers (μm), 15-100 micrometers (μm), 20-100 micrometers (μm), 25-100 micrometers (μm), 45-100 micrometers (μm), or 60-100 micrometers (μm). Depending on the thickness T of the cover layer 350, the thickness tolerance of the cover layer 350 may be plus or minus (±) 1-5 micrometers (μm). Providing a cover layer 350 with other thicknesses T may also be useful.

[0141] Various techniques can be used to form the cover layer 350. For example, the technique used to form the cover layer 350 may depend on the type of cover layer 350 used. In the case of a composite cover layer 350, it can be formed by compression molding or lamination, such as vacuum or roll-to-roll lamination. Other techniques for forming the composite cover layer 350 may also be useful. For example, the composite cover layer 350 may be formed by spin coating, slot die or printing, or other types of printing techniques.

[0142] In some embodiments, an adhesion promoting layer (not shown) may be formed over the top of the BEOL dielectric stack 330 before forming the capping layer 350. The adhesion promoting layer enhances adhesion between the top of the BEOL dielectric stack 330 and the subsequently formed capping layer 350. The adhesion promoting layer may be, for example, a silane as described above. Other types of adhesion promoting layers may also be useful.

[0143] Reference Figure 6b , a process of forming a via opening in a capping layer 350 on a processed semiconductor wafer 300 begins. Shown is a cross-sectional view of a portion of the processed semiconductor wafer 300 with the capping layer 350 on top of the BEOL dielectric stack 330. The cross-sectional view of the portion of the processed semiconductor wafer 300 corresponds to, for example, a die 310.

[0144] To form the through-hole opening, an etching process is employed. In one embodiment, the etching process is a multi-step etching process. In one embodiment, the multi-step etching process includes a first and a second etching process. As shown, the first etching process etches the cover layer 350 to form a through-hole half-opening 360. For example, the first etching process etches the composite cover layer 350 to form the through-hole half-opening 360. Alternatively, the cover layer 350 may be another type of insulating layer or dielectric layer. The position of the through-hole half-opening 360 corresponds to the position of the die bond pad 342 at the top of the BEOL dielectric stack 330. Preferably, the position of the through-hole half-opening 360 is selected so that the bottom of the subsequently formed full through-hole opening is approximately centered on the die bond pad 342.

[0145] In one embodiment, the first etching process is a laser etching process, such as laser ablation using pulsed ultraviolet (UV) laser or laser drilling using a drilling tool. For example, the laser drilling is performed using a normal number of pulses (P) and a normal energy (E). In one embodiment, the normal energy (E) is approximately in the range of 1-2 joules, 1.2-2 joules, 1.4-2 joules, 1.6-2 joules, or 1.8-2 joules. In a preferred embodiment, the normal energy (E) is in the range of 1.2-1.5 joules. In one embodiment, the normal number of pulses (P) is approximately in the range of 5-20 pulses, 7-20 pulses, 9-20 pulses, 11-20 pulses, 13-20 pulses, 15-20 pulses, or 17-20 pulses. In a preferred embodiment, the normal number of pulses (P) is in the range of 7-10 pulses. By using normal levels of E and P, the via half-opening 360 can be formed more quickly.

[0146] The first etching process is controlled to etch a partial depth of the capping layer 350 without exposing the die bond pad 342. In one embodiment, the first etching process etches the capping layer 350 to a depth D. The depth D is less than the thickness T of the capping layer 350. In one embodiment, the depth D is approximately in the range of 5-60% of the thickness T of the capping layer 350, in the range of 10-60% of the thickness T of the capping layer 350, in the range of 15-60% of the thickness T of the capping layer 350, in the range of 20-60% of the thickness T of the capping layer 350, in the range of 30-60% of the thickness T of the capping layer 350, in the range of 40-60% of the thickness T of the capping layer 350, or in the range of 50-60% of the thickness T of the capping layer 350. In a preferred embodiment, the depth D is approximately in the range of 10-20% of the thickness T of the capping layer 350. A remaining portion of the capping layer 350 is left to cover the die bond pad 342. The remaining portion of the capping layer 350 covering the die bond pad 342 has a planarization thickness R that is approximately in the range of 1-8 microns (μm), 2-8 microns (μm), 3-8 microns (μm), 4-8 microns (μm), 5-8 microns (μm), 6-8 microns (μm), or 7-8 microns (μm). In a preferred embodiment, the planarization thickness R of the remaining portion of the capping layer 350 is approximately 2 μm. The capping layer 350 remaining above the die bond pad 342 forms the bottom surface 368 of the through-hole half-opening 360. The bottom surface 368 of the through-hole half-opening 360 forms the top of the remaining portion of the capping layer 350 covering the die bond pad 342. Other depths D may also be useful. Preferably, the depth D is selected so that the first etching process does not expose the die bond pad 342. For example, at least a portion of the capping layer 350 remains above the die bond pad 342.

[0147] In one embodiment, the through-hole half-opening 360 can be a circular opening. Other opening shapes are also possible. For example, the shape of the through-hole half-opening 360 can depend on design requirements. As shown, the through-hole half-opening 360 has an inclined sidewall 362 that gradually narrows inward from the top of the cover layer 350 to the bottom of the through-hole half-opening 360. In one embodiment, the first etching process produces a laser-drilled or laser-etched through-hole half-opening sidewall 362. The through-hole half-opening sidewall 362 can be referred to as the through-hole opening upper sidewall, which is formed by the first etching process.

[0148] In one embodiment, Figure 6c As shown, the second etching process removes the remaining portion of the cover layer 350 above the die bond pad 342. For example, the second etching process forms a through-hole opening 370 in the cover layer 350, exposing the die bond pad 342. In one embodiment, the second etching process is a laser etching process. The second etching process is performed using low P and E. Low P has fewer pulses than normal P (low P < normal P), and low E has lower energy than normal E (low E < normal E). The second etching process using low P and low E avoids damaging the die bond pad 342. Low E can be approximately in the range of 0.3-0.6 Joules, 0.4-0.6 Joules, or 0.3-0.5 Joules. In a preferred embodiment, low E is in the range of 0.3-0.4 Joules. In another preferred embodiment, low E is in the range of 0.5-0.6 Joules. Low P is determined by the values ​​of depth D and low E. For example, when Low is set to 0.3-0.4 Joules, a depth D of 1 micron (μm) can be removed with one pulse; and when Low E is set to 0.5-0.6 Joules, a depth D of 1.3 μm can be removed with one pulse. Other values ​​of Low P and Low E that avoid damaging the die bond pad 342 may also be useful. Preferably, Low P and Low E are selected to remove the remaining portion of the capping layer 350 as quickly as possible without damaging the die bond pad 342.

[0149] In one embodiment, the via opening lower sidewall 364 is continuous from the via opening upper sidewall 362. As shown, the via opening upper sidewall 362 and the via opening lower sidewall 364 form a tapered via opening sidewall of the via opening 370. In one embodiment, the second etching process produces laser drilling or laser etching to form the via opening lower sidewall 364.

[0150] The process may continue after forming the via openings 370 in the capping layer 350. For example, the process may continue until the processed semiconductor wafer 300 is singulated into individual dies 310 and packaged to form packaged dies.

[0151] Figures 7a and 7bFIG. 4 is a simplified cross-sectional view of a portion of a processed wafer 400 illustrating another embodiment of a process for forming a through-hole opening in a capping layer 450 on the processed wafer 400. The portion of the processed wafer 400 corresponds to one die bond pad 442. Of course, it should be understood that the processed wafer 300 includes multiple die bond pads 342 for multiple dies 310. The processed wafer 400 with the capping layer 450 and the processing process are similar to FIG. Figure 5 and Figures 6a to 6c Common elements or their details may not be described here.

[0152] refer to Figure 7a The first etching process forms a via half opening 460 in the capping layer 450 over the top of the BEOL dielectric stack 430. As shown, the top of the BEOL dielectric stack 430 includes a passivation layer 444 having a pad opening 448 to expose the die bond pad 442.

[0153] In one embodiment, the first etching process is a laser etching process using a pulsed ultraviolet (UV) laser ablation or drilling tool. The first etching process etches the capping layer 450 using normal P and normal E to form a via half-opening 460. The first etching process is a controlled etching process that etches the capping layer 450 to a depth D. The depth D is less than the thickness T of the capping layer 450. The first etching process leaves a remaining portion of the capping layer 450 having a flat thickness R above the die bond pad 342.

[0154] In one embodiment, the via half-opening 460 can be circular. Other shapes are also possible. In one embodiment, the first etching process forms the via half-opening 460 with a sloped sidewall 462. The sloped sidewall 462 of the via half-opening 460 can be referred to as the via opening upper sidewall. The remaining capping layer above the die bond pad 442 forms the bottom surface of the via half-opening 460.

[0155] exist Figure 7bIn one embodiment, a second etching process is performed. In one embodiment, the second etching process is plasma etching. The plasma etching removes the remaining portion of the cover layer 450 to expose the die bonding pad 442. For example, the second etching process completes the formation process of the through hole opening 470, exposing the die bonding pad 442 therefrom. In one embodiment, the through hole opening 470 formed by the second etching process has inclined sidewalls. For example, the through hole opening upper sidewall 462 (formed by the first etching process) and the through hole opening lower sidewall 464 (formed by the second etching process) are inclined, gradually narrowing inward from the top of the cover layer 450 to the bottom of the cover layer 450. In one embodiment, the through hole opening upper sidewall 462 is a laser etched sidewall, and the through hole opening lower sidewall 464 is a plasma etched sidewall. By adopting plasma etching as the second etching process, damage to the die bonding pad 442 is avoided.

[0156] In one embodiment, the plasma etch also removes the top surface of the capping layer 450 while removing the remaining portion above the die bonding pad 442. For example, the reduction in thickness T of the capping layer 450 is a result of the second etch. Since the remaining portion above the die bonding pad 442 has a flat thickness R, the top surface of the capping layer 450 is also reduced by a thickness approximately equal to R. Therefore, the initial thickness T of the capping layer 450 is reduced. i The loss caused by the second etching process needs to be taken into account. For example, the thickness T of the capping layer 450 can be increased by R (T = T i In addition, the plasma etch may also cause some erosion 356 at the top of the via opening 370. For example, due to the erosion 356, the interface between the top surface of the capping layer 350 and the upper sidewall 362 of the via opening may not be a sharp corner.

[0157] In other embodiments, during the plasma etching, the top surface of the capping layer 450 decreases in thickness by more than R. For example, during the plasma etching, the top surface of the capping layer 450 decreases in thickness by about 20% more than R.

[0158] The process may continue after forming the via openings 470 in the cover layer 450. For example, the process may continue until the processed wafer 400 is singulated into individual dies 410 and packaged to form packaged dies.

[0159] Figures 8a to 8d is yet another embodiment of a process for forming a via opening 570 in a capping layer 550 over a processed wafer 500. In particular, Figure 8a are images of a top view of the processed wafer 500 with a mask layer 590 overlying the capping layer 550 , and a simplified cross-sectional view of a portion of the processed wafer 500 with a mask layer 590 overlying the capping layer 550 . Figures 8b to 8dis a simplified cross-sectional view of a portion of a processed wafer 500 having a cover layer 550. For example, the cross-sectional view corresponds to a die 510 on the processed wafer 500. The process and the processed wafer 500 having the cover layer 550 are similar to Figure 5 、 Figures 6a to 6c and Figures 7a and 7b Common elements or their details may not be described here.

[0160] refer to Figure 8a For example, a processed wafer 500 includes a circuit component (not shown) formed on a die 510 on an active wafer surface 502 of the wafer 501. The opposite surface 503 may be the inactive wafer surface. A back-end-of-line (BEOL) dielectric stack 530 with interconnects (not shown) is formed on the active wafer surface 502 of the wafer 501 with the circuit components. The top interconnect layer of the BEOL dielectric stack 530 is a pad level having a passivation layer 540 with pad openings 548 for exposing die bond pads 542 to provide external connections to the circuit component.

[0161] A capping layer 550 is formed on top of the BEOL dielectric stack 530 to cover the passivation layer 540 having the pad opening 548 and the die bond pad 542. In one embodiment, the capping layer 550 is a dielectric capping layer. In one embodiment, the capping layer 550 is a composite capping layer having a base capping layer and a filler. Other types of dielectric capping layers may also be useful.

[0162] In one embodiment, the capping layer 550 can be tailored to prevent breakage and cracking in the BEOL dielectric stack 530 during dicing. In one embodiment, the Young's modulus and fracture strength are selected to reduce or prevent breakage and cracking during wafer singulation. The capping layer 550 has a Young's modulus of approximately 10,000-25,000 MPa, approximately 14,000-25,000 MPa, approximately 15,000-25,000 MPa, approximately 16,000-25,000 MPa, approximately 15,000-20,000 MPa, or approximately 20,000-25,000 MPa. The covering layer 550 may have a breaking strength of approximately 45-150 MPa, approximately 70-150 MPa, approximately 70-120 MPa, approximately 70-105 MPa, approximately 80-120 MPa, or approximately 90-100 MPa. In one embodiment, the covering layer 550 has a coefficient of thermal expansion of approximately 6-20 ppm / °C. The covering layer 550 may have a temperature stability between -65°C and +300°C.

[0163] The cover layer 550 has a thickness T. In one embodiment, the thickness T is approximately 10-100 micrometers (μm), 15-100 micrometers (μm), 20-100 micrometers (μm), 25-100 micrometers (μm), 45-100 micrometers (μm), or 60-100 micrometers (μm). The thickness tolerance of the cover layer 550 can be plus or minus (±) 1-5 micrometers (μm). Providing a cover layer 550 with other thicknesses may also be useful.

[0164] Various techniques can be used to form capping layer 550. In one embodiment, capping layer 550 is formed by compression molding or lamination, such as vacuum or roll-to-roll lamination. Other techniques, such as spin coating, slot die, or printing, may also be useful. Prior to forming capping layer 550, an adhesion-promoting layer (not shown) may be formed over the top of BEOL dielectric stack 530 to enhance bonding at the interface between BEOL dielectric stack 530 and the subsequently formed capping layer 550.

[0165] In one embodiment, a mask layer 590 is formed over the capping layer 550. For example, the mask layer 590 is formed on top of the capping layer 550. The capping layer 550 is an etch mask for forming the via opening 570 in the capping layer 550. This exposes the die bonding pad 542. Various types of layers can be used to form the capping layer 550. For example, the mask layer 590 can be a metal mask layer or a non-metal mask layer. In addition, the mask layer 590 can be a single mask layer or a mask stack having multiple mask layers. The mask stack can include metal layers, non-metal layers, or a combination thereof. Other arrangements of the mask layer 590 may also be useful. In one embodiment, the mask layer 590 is formed of copper (Cu), titanium (Ti), nickel (Ni) alloy, or a combination thereof.

[0166] The mask layer 590 can be formed using various techniques, such as sputtering, electroplating, lamination, or a combination thereof. Other techniques can also be used to form the mask layer 590. The technique used can depend on, for example, the type of mask layer being formed. The thickness of the mask layer 590 can be approximately in the range of 0.3-1 micrometers (μm), 0.5-1 micrometers (μm), 0.7-1 micrometers (μm), or 0.9-1 micrometers (μm). In a preferred embodiment, the mask layer 590 has a thickness of approximately 0.6 μm. Providing mask layers with other thicknesses may also be useful.

[0167] exist Figure 8bIn the embodiment, a first etching process forms a via half-opening 560 in the mask layer 590 and the capping layer 550. In one embodiment, the first etching process is a laser etching process using pulsed ultraviolet (UV) laser ablation or a drilling tool. The first etching process etches the mask layer 590 and the capping layer 550 using normal P and normal E to form the via half-opening 560. The first etching process is a controlled etching process that etches the capping layer 550 to a depth D. The depth D is less than the thickness T of the capping layer 550. The first etching process leaves a remaining portion of the capping layer 550 having a flat thickness R above the die bond pad 542. The via half-opening 560 extends through a portion of the mask layer 590 and the capping layer 550.

[0168] The via half-opening 560 can be circular or have other shapes. In one embodiment, the first etching process forms the via half-opening 560 with a sloped sidewall 562. The sloped sidewall 562 of the via half-opening 560 can be referred to as the via opening upper sidewall. The remaining cover layer above the die bond pad forms the bottom surface of the via half-opening 560.

[0169] like Figure 8c As shown, a second etching process is performed to remove the remaining portion of the capping layer 550, thereby exposing the die bond pad 542. For example, the second etching process completes the via opening 570 process, thereby exposing the die bond pad 542. In one embodiment, the second etching process is a plasma etching process.

[0170] In one embodiment, the second etching process forms a via opening 570 having sloped sidewalls. For example, the via opening upper sidewall 562 (formed by the first etching process) and the via opening lower sidewall 564 (formed by the second etching process) are sloped, gradually narrowing inward from the top of the mask layer 590 to the bottom of the capping layer 550. In one embodiment, the via opening upper sidewall 562 is a laser-etched sidewall, and the via opening lower sidewall 564 is a plasma-etched sidewall.

[0171] By using plasma etching for the second etching process, damage to the die bond pad 542 is avoided. In addition, the mask layer 590 protects the top surface of the capping layer 550 from being etched. This avoids the need to increase the initial thickness of the capping layer 550. In addition, the mask layer 590 preserves the sharp corner between the top surface of the capping layer 550 and the via opening upper sidewall 562 of the via opening 570.

[0172] Reference Figure 8d, the mask layer 590 is removed to expose the top surface of the capping layer 550. Various techniques can be used to remove the mask layer 590. For example, the mask layer 590 can be removed by a mechanical process, a chemical process, or a combination thereof. Other techniques for removing the mask layer 590 may also be useful.

[0173] After removing the mask layer 590 , the process may continue. For example, the process may continue until the processed wafer 500 is singulated into individual dies 510 and packaged to form packaged dies.

[0174] Figures 9a to 9c FIG. 6 is a simplified cross-sectional view of a portion of a processed wafer 600 illustrating another embodiment of a process for forming a via opening in a capping layer 650 over the processed wafer 600 using a mask layer 690. The portion of the processed wafer 600 corresponds to one die bond pad 642. Of course, it is understood that the processed wafer 600 includes multiple die bond pads 642 for multiple dies 610. The processed wafer 600 with the capping layer 650 and the process thereof are similar to FIG. Figure 5 、 Figures 6a to 6c 、 Figures 7a and 7b and Figures 8a to 8d Common elements or their details may not be described here.

[0175] exist Figure 9a In FIG. 6 , a first etching process is performed on a processed wafer 600 having a mask layer 690 on a capping layer 650 located above a BEOL dielectric stack 630 having a passivation layer 644 including a pad opening and a die bond pad 642. The first etching process forms a via half-opening 660 through the mask layer 690 and partially through the capping layer 650. In one embodiment, the first etching process is a laser etching process using pulsed ultraviolet (UV) laser ablation or a drilling tool. The first etching process etches the mask layer 690 and the capping layer 650 using normal P and normal E to form the via half-opening 660. The first etching process is a controlled etch that etches the capping layer 650 to a depth D. The depth D is less than the thickness T of the capping layer 650. The first etching process leaves a remaining portion of the capping layer 650 having a flat thickness R above the die bond pad 642.

[0176] In one embodiment, the via half-opening 660 can be circular. Other shapes are also possible. In one embodiment, the first etching process forms the via half-opening 660 with a sloped sidewall 662. The sloped sidewall 662 of the via half-opening 660 can be referred to as the via opening upper sidewall. The remaining capping layer above the die bond pad 642 forms the bottom surface of the via half-opening 660.

[0177] refer to Figure 9bA second etching process is performed to remove the remaining portion of the capping layer 650 to expose the die bonding pad 642. For example, the second etching process completes the process of forming the via opening 670, thereby exposing the die bonding pad 642. In one embodiment, the second etching process is performed using a low-P and low-E laser.

[0178] like Figure 9c As shown, mask layer 690 is removed. Mask layer 690 is removed to expose the top surface of capping layer 650. Various techniques can be used to remove mask layer 690. For example, mask layer 690 can be removed by a mechanical process, a chemical process, or a combination thereof. Other techniques for removing mask layers may also be useful.

[0179] After removing the mask layer 690 , the process may continue. For example, the process may continue until the processed wafer 600 is singulated into individual dies 610 and packaged to form packaged dies.

[0180] Figure 10 is a flow chart of another two-step etching process 11 according to an exemplary embodiment of the present disclosure. Figures 11a to 13d is in accordance with Figure 10 , a schematic diagram of a two-step etching process 11 for producing a grain structure 152 .

[0181] The two-step etching process 11 is similar to the two-step etching process 10, except that step S1 provides the die 113, for example, by dividing the wafer 100 into the die 113; and the following steps S3 to S5, S3' to S6', and S3" to S7" of the two-step etching process 11 are similar to those in the two-step etching process 10. Therefore, the same reference numerals are used herein to describe the same or similar features as those in the two-step etching process 10.

[0182] Figures 11a to 11d is used Figure 10 Schematic diagram of the two-step etching process 11 in manufacturing the grain structure 152.

[0183] Step S1: Provide a die 113. Figure 11a The wafer 100 having an active surface 1001 and an inactive surface (also referred to as a back surface of the wafer) 1002 is cut along saw lines to form a die 113. The die 113 has an active surface 1131 and a back surface 1132. In addition, the die 113 has one or more contact pads (e.g., Figure 11a The die 113 may be picked up and placed on a panel (not shown) for subsequent panel-level processing.

[0184] Step S2: applying a protective layer 107 onto the active surface 1131 of the die 113. Figure 11b A protective layer 107 having a flat thickness T is applied to the active surface 1131 of the die and covers the contact pad 103. Due to the small size of the die 113, the protective layer 107 may not have a flat thickness T. Figure 2c Therefore, compared with the two-step etching process 10 at the wafer level, the two-step etching process 11 can make the etching of the protection layer 107 simpler and more controlled.

[0185] Adhesion promoting layer 101 (not shown) may also be applied between active face 1131 of die and protective layer 107 after singulation. Figure 11a As shown, an adhesion promoting layer 101 is applied onto the active surface 1001 of the wafer before singulation and then cut together with the wafer 100 to form dies 113 with the adhesion promoting layer 101 .

[0186] Steps S3 to S5 of the two-step etching process 11 are similar to the two-step etching process 10 described above, except that the two-step etching process 10 is performed at the wafer level, while the two-step etching process 11 is performed at the die level or panel level (if placed on a panel). Figure 11c In the first etching step 12, a high power laser etcher 20 is used to remove the top portion 107a of the protective layer 107 corresponding to the contact pad 103, and form a protective layer half opening 110 in the protective layer 107. The remaining protective layer 108 remains in the protective layer half opening 110 and still covers the contact pad 103. Figure 11d , then a second etching step 14 is performed using a low-power laser etcher 30 or a plasma etching device 40 to remove the remaining protective layer 108 and form a protective layer opening 109 for exposing the contact pad 103 from the protective layer 107. In particular, the contact pad 103 is not damaged in the second etching process 14. If a low-power laser etcher 30 is used, an additional step S5 may be required to remove the protective layer residue 112 in the protective layer opening 109, similar to Figure 2i .

[0187] Figures 12a to 12d is used Figure 10 Schematic diagram of the two-step etching process 11 in manufacturing the grain structure 152.

[0188] like Figure 12a and Figure 12b As shown, steps S1 and S2 are performed in the same manner as above; and steps S3' to S6' are performed similarly to the description of the two-step etching process 10, except that the two-step etching process 11 is performed at the grain level or panel level.

[0189] Reference Figure 12b ,and Figure 3cSimilarly, a mask layer 114 having a thickness MT is applied over the protective layer 107. Figure 12c , a first etching step 12 is performed using a high power laser etcher 20 to form a protective layer half opening 110 in the protective layer 107, and the mask layer 114 is etched into a patterned mask layer 116 having a mask layer opening 115. Figure 12d , then a second etching step 14 is performed using a low-power laser etcher 30 or a plasma etcher 40 to remove the remaining protective layer 108 and form a protective layer opening 109, thereby exposing the contact pad 103 from the protective layer 107. In particular, the contact pad 103 will not be damaged in the second etching process 14. If a low-power laser etcher 30 is used, an additional step S5 may be required to remove the protective layer residue 112 in the protective layer opening 109, similar to Figure 2i .

[0190] Figures 13a to 13d is used Figure 10 Schematic diagram of the two-step etching process 11 in manufacturing the grain structure 152.

[0191] Steps S1 and S2 are Figure 12a and Figure 12b and steps S3 ' to S6 'are performed similarly to the description of the two-step etching process 10 , except that the two-step etching process 11 is performed at the grain level or panel level.

[0192] Reference Figure 13b , similar to Figure 4d , a patterned mask layer 116 having a thickness MT is applied over the protective layer 107. Figure 13c , a first etching step 12 is performed, using a high power laser etcher 20 to form a protective layer half opening 110 in the protective layer 107 through the mask layer opening 115 of the patterned mask layer 116. Figure 13d , then a second etching step 14 is performed using a low-power laser etcher 30 or a plasma etcher 40 to remove the remaining protective layer 108 and form a protective layer opening 109 to expose the contact pad 103 from the protective layer 107. In particular, the contact pad 103 will not be damaged in the second etching process 14. If a low-power laser etcher 30 is used, an additional step S5 may be required to remove the protective layer residue 112 in the protective layer opening 109, similar to Figure 2i .

[0193] The two-step etching process 10 and the two-step etching process 11 each have their own advantages. The two-step etching process 10, performed at the wafer level, can process multiple dies 113 simultaneously, thereby advantageously improving the productivity of producing the granular structure 152. The two-step etching process 11, performed on individual dies 113, provides better control in step S2, allowing for a more uniform application of the protective layer 107 on the active surfaces 1131 of the dies. Furthermore, by placing multiple dies 113 on a panel and then performing the two-step etching process 11, multiple dies 113 can be processed simultaneously using a panel-level process, thereby also improving the productivity of producing the granular structure 152.

[0194] The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics of the present disclosure. The foregoing embodiments are therefore to be considered in all respects as illustrative and not restrictive. The scope of the present invention is therefore indicated by the appended claims rather than the foregoing description, and all variations within the meaning and scope of the claims are intended to be included in the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A semiconductor wafer having an active wafer surface and an inactive wafer surface facing each other, wherein a plurality of contact pads are formed on the active wafer surface; an insulating layer, located on the active surface of the wafer, and used to cover the active surface of the wafer and the contact pads; as well as a plurality of through-hole openings formed in the insulating layer for exposing the contact pads from the insulating layer without damaging the contact pads; forming a through-hole opening by removing a top portion of the insulating layer corresponding to the contact pad through a multi-step etching process; forming a half-hole opening by leaving a residual insulating layer in the through-hole opening before the last etching step of the multi-step etching process; The through hole opening includes a lower sidewall and an upper sidewall, wherein the lower sidewall continues from the upper sidewall, whereby the sidewalls of the through hole opening gradually narrow from the top of the insulating layer to the bottom of the through hole opening.

2. The semiconductor structure according to claim 1, wherein Also includes: An adhesion promoting layer located between the active surface of the wafer and the insulating layer is used to adhere the insulating layer to the active surface of the wafer.

3. The semiconductor structure according to claim 1, wherein: Also includes: a mask layer disposed on the insulating layer, wherein the mask layer is made of metal; The mask layer forms a plurality of mask layer openings in the multi-step etching process, so as to expose the top of the insulating layer corresponding to the contact pad from the mask layer.

4. The semiconductor structure according to claim 3, wherein: The insulating layer not exposed from the mask layer opening forms a sharp edge relative to the through-hole opening.

5. The semiconductor structure according to claim 1, wherein Also includes: a patterned mask layer disposed on the insulating layer, wherein the patterned mask layer has a plurality of mask layer openings for exposing the top portion of the insulating layer corresponding to the contact pads from the mask layer; The patterned mask layer is made of metal.

6. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a semiconductor wafer having an active wafer surface and an inactive wafer surface facing each other, wherein a plurality of contact pads are formed on the active wafer surface; An insulating layer is provided on the active surface of the wafer to cover the active surface of the wafer and the contact pad; as well as forming a through-hole opening in the insulating layer for exposing the contact pad from the insulating layer without damaging the contact pad; The step of forming a through-hole opening in the insulating layer further comprises performing at least one etching step for partially removing a top portion of the insulating layer corresponding to the contact pad to form a half-hole opening, wherein a residual insulating layer is left in the half-through-hole opening; The at least one etching step adopts a high-power laser etching process; The step of forming a through-hole opening in the insulating layer further includes performing a final etching step for removing the remaining insulating layer in the half-hole opening, thereby exposing the contact pad from the insulating layer.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein: Also includes: An adhesion promoting layer is formed between the active surface of the wafer and the insulating layer for adhering the insulating layer to the active surface of the wafer.

8. The method for manufacturing a semiconductor structure according to claim 6, wherein: The final etching step is performed using a low-power laser etching process.

9. The method for manufacturing a semiconductor structure according to claim 8, wherein: Also includes: After the final etching step, a plasma process is used to remove the remaining insulation layer residues in the via openings.

10. The method for manufacturing a semiconductor structure according to claim 6, wherein: The final etching step is performed using a plasma process.

11. The method for manufacturing a semiconductor structure according to claim 6, wherein: Also includes: Before the at least one etching step, a mask layer is provided on the insulating layer to completely cover the insulating layer, wherein the mask layer is made of metal and is etched to form a plurality of mask layer openings for exposing the top of the insulating layer corresponding to the contact pads; as well as The mask layer is removed from the insulating layer after the final etching step.

12. The method for manufacturing a semiconductor structure according to claim 6, wherein: Also includes: Before the at least one etching step, a patterned mask layer is provided on the insulating layer to expose the top of the insulating layer corresponding to the contact pad; as well as removing the patterned mask layer from the insulating layer after the final etching step; The patterned mask layer is made of metal.

13. The method for manufacturing a semiconductor structure according to claim 6, wherein: Also includes: The semiconductor wafer is divided into a plurality of individual semiconductor dies, wherein the insulating layer remains on each individual semiconductor die and has at least one of the through-hole openings therein.

14. A two-step etching method, characterized in that: A two-step etching method for manufacturing a semiconductor die having an active die surface into a die structure, wherein at least one through-hole opening is formed in an insulating layer on the active die surface, and a contact pad located on the active die surface and covered by the insulating layer is exposed from the insulating layer through the at least one through-hole opening. The two-step etching method comprises: performing a first etching step for partially removing a top portion of the insulating layer corresponding to the contact pad, wherein a remaining insulating layer remains in the at least one through-hole opening; and performing a second etching step for removing the remaining insulating layer in the at least one through-hole opening to expose the contact pad from the insulating layer; The first etching step adopts a high-power laser etching process.

15. The two-step etching method according to claim 14, wherein: Also includes: An adhesion promoting layer is formed between the active surface of the die and the insulating layer for adhering the insulating layer to the active surface of the die.

16. The two-step etching method according to claim 14, wherein: Also includes: Before the first etching step, a mask layer is provided on the insulating layer to completely cover the insulating layer, wherein the mask layer is made of metal, and in the first etching step, the mask layer is etched to have at least one mask layer opening corresponding to the at least one through-hole opening; and After the second etching step, the mask layer is removed from the insulating layer.

17. The two-step etching method according to claim 14, wherein: Also includes: Before the first etching step, a patterned mask layer is provided on the insulating layer, wherein the patterned mask layer is made of metal and has at least one mask layer opening corresponding to the at least one through-hole opening; as well as After the second etching step, the patterned mask layer is removed from the insulating layer.

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