Semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a semiconductor device having a fuse structure and an antifuse structure and a method for manufacturing the same. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a first electrode disposed on the first dielectric layer. The semiconductor device also includes a fuse link disposed on the first electrode, and a second electrode disposed on the fuse link. The semiconductor device also includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer located between the first electrode and the third electrode form an antifuse structure.

Description

Technical Field

[0001] This application claims priority to and the benefit of U.S. regular application No. 16 / 950,518, filed on November 17, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same. More specifically, the present disclosure relates to a semiconductor device having a fuse structure and an antifuse structure and a related method for manufacturing the same. Background Art

[0003] Integrated circuit (IC) devices typically have all internal connections set up during the manufacturing process. However, due to the high R&D costs, long manufacturing times, and high manufacturing equipment costs of producing integrated circuits, practitioners often desire circuits that can be set or programmed. Such circuits are called programmable circuits and typically include programmable links. Programmable links are electrical connections that are disconnected or established by practitioners at selected electronic nodes after the IC device is manufactured and packaged to activate or deactivate the corresponding selected electronic nodes.

[0004] One type of programmable link is a fuse structure. A programmable link is programmed within an IC device by blowing the fuse structure at selected crosspoints to create a path. The combination of blown and unblown links represents a digital pattern of ones and zeros, representing the data the user wishes to store in the IC device. Another type of programmable link is an antifuse structure. Unlike the programming mechanism with a fuse structure, which creates a path, the programming mechanism in an antifuse structure creates a short circuit or a relatively low-resistance link.

[0005] In the fabrication of integrated circuits, fuse and antifuse structures are widely used for fault tolerance. For example, fuse and antifuse structures can be placed within circuit paths in semiconductor devices. However, the fabrication and integration of semiconductor devices involves many complex steps and operations. The integration of semiconductor devices is becoming increasingly complex. The increasing complexity of semiconductor device fabrication and integration can lead to defects. Consequently, continuous improvements in semiconductor device structures and processes are needed to address these defects and thereby improve performance.

[0006] The above description of “prior art” is merely to provide background technology, and does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0007] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a first electrode disposed on the first dielectric layer. The semiconductor device also includes a fuse link disposed on the first electrode, and a second electrode disposed on the fuse link. The semiconductor device also includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer located between the first electrode and the third electrode form an antifuse structure.

[0008] In some embodiments, the third electrode is in direct contact with the first dielectric layer. In some embodiments, the third electrode is covered by the second dielectric layer. In some embodiments, the first electrode has a circular profile in cross-section. In some embodiments, the first electrode and the fuse link are surrounded by the second dielectric layer. In some embodiments, a lower portion of the second electrode is surrounded by the second dielectric layer. In some embodiments, the first electrode has a first width, the fuse link has a second width, and the second electrode has a third width, wherein the third width is greater than the first width, and the first width is greater than the second width.

[0009] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a first conductive line and a second conductive line disposed on the first dielectric layer and extending parallel to each other. The semiconductor device includes a second dielectric layer disposed between the first conductive line and the second conductive line. The first conductive line and the second conductive line are covered by the second dielectric layer. The semiconductor device also includes a third dielectric layer disposed on the second dielectric layer. The third dielectric layer has an etching selectivity different from that of the second dielectric layer. In addition, the semiconductor device includes a first electrode disposed between the first conductive line and the second conductive line. The first electrode has a circular profile and is separated from the first dielectric layer by the second dielectric layer. The semiconductor device also includes a second electrode disposed on the first electrode. The second electrode extends from the second dielectric layer to the third dielectric layer.

[0010] In some embodiments, the first electrode, the first conductive line, and a portion of the second dielectric layer sandwiched between the first electrode and the first conductive line form an antifuse structure. In some embodiments, the semiconductor device further includes a fuse link disposed between the first electrode and the second electrode, wherein the first electrode, the second electrode, and the fuse link form a fuse structure. In some embodiments, the first electrode is in direct contact with the first conductive line, and wherein the first electrode and the first conductive line form a fuse structure. In some embodiments, the semiconductor device further includes a dielectric portion disposed between the first electrode and the second electrode, wherein the first electrode, the second electrode, and the dielectric portion form an antifuse structure. In some embodiments, the dielectric portion has a first width, the second electrode has a second width, and the second width is greater than the first width. In some embodiments, the semiconductor device further includes a third conductive line disposed above the first dielectric layer and parallel to the first conductive line, wherein the first conductive line is located between the second conductive line and the third conductive line, and an air gap is formed between the first conductive line and the third conductive line, the air gap being sealed by the third dielectric layer. In some embodiments, a sidewall of the first conductive line and a sidewall of the third conductive line are exposed through the air gap.

[0011] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a first electrode disposed within the second dielectric layer, and a dielectric portion disposed on the first electrode. The semiconductor device also includes a second electrode disposed on the dielectric portion, and a third electrode adjacent to and directly contacting the first electrode. The first electrode, the dielectric portion, and the second electrode form an antifuse structure, and the first electrode and the third electrode form a fuse structure.

[0012] In some embodiments, the first electrode is separated from the first dielectric layer by the second dielectric layer, and the third electrode is in direct contact with the first dielectric layer. In some embodiments, the dielectric portion is surrounded by the second dielectric layer, wherein the first electrode has a first width, the dielectric portion has a second width, and the first width is greater than the second width. In some embodiments, the third electrode is sandwiched by an air gap between the first electrode and the second dielectric layer, wherein the first electrode and the air gap have a circular profile in a cross-sectional view. In some embodiments, the semiconductor device further includes a third dielectric layer disposed above the second dielectric layer and surrounding the second electrode, wherein a top surface of the second dielectric layer is higher than an interface between the third dielectric layer and the air gap.

[0013] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same. In some embodiments, the semiconductor device includes a fuse link disposed on the first electrode, and a second electrode disposed on the fuse link. In some embodiments, the semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a vertical fuse structure, and the first electrode, the third electrode, and a portion of the dielectric layer located between the first electrode and the third electrode form a lateral antifuse structure. Therefore, the present disclosure integrates a vertical fuse structure and a lateral antifuse structure; thus, the integration of the semiconductor device will be improved.

[0014] The above has provided a fairly broad overview of the technical features and advantages of the present disclosure, allowing for a better understanding of the detailed description of the present disclosure below. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure pertains that the concepts and specific embodiments disclosed below can be readily utilized to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure pertains that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more complete understanding of the disclosure of this application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which like reference numerals refer to like elements.

[0016] Figure 1 Schematic diagrams illustrating semiconductor devices according to some embodiments in cross-sectional views.

[0017] Figure 2 is a schematic diagram illustrating a modified semiconductor device according to some embodiments in a cross-sectional view.

[0018] Figure 3 Schematic diagrams are provided to illustrate a method for fabricating a semiconductor device in some embodiments using a flow chart.

[0019] Figure 4 FIG2 is a schematic diagram illustrating a flow chart of a method for preparing a modified semiconductor device in some embodiments.

[0020] Figure 5 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of sequentially forming a first dielectric layer and a patterned mask on a semiconductor substrate in a process of forming a semiconductor device in some embodiments.

[0021] Figure 61 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of etching a first dielectric layer using a patterned mask as a mask in a process of forming a semiconductor device in some embodiments.

[0022] Figure 7 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a plurality of conductive lines in a first dielectric layer in a process of forming a semiconductor device in some embodiments.

[0023] Figure 8 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of removing a portion of a first dielectric layer located between conductive lines in a process for forming a semiconductor device in some embodiments.

[0024] Figure 9 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a second dielectric layer on a first dielectric layer and a conductive line in a process of forming a semiconductor device in some embodiments.

[0025] Figure 10 2 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a third dielectric layer on a second dielectric layer in a process of forming a semiconductor device in some embodiments.

[0026] Figure 11 2 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a patterned mask on a third dielectric layer in a process of forming a semiconductor device in some embodiments.

[0027] Figure 12 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of etching the second dielectric layer and the third dielectric layer using a patterned mask as a mask in a process of forming a semiconductor device in some embodiments.

[0028] Figure 13 2 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a patterned mask on a third dielectric layer in a process of forming a semiconductor device in some embodiments.

[0029] Figure 14 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of etching an upper portion of a third dielectric layer using a patterned mask as a mask in a process for forming a semiconductor device in some embodiments.

[0030] Figure 15 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a second dielectric layer on a first dielectric layer and a conductive line in a process for forming a modified semiconductor device in some embodiments.

[0031] Figure 16 FIG2 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a third dielectric layer on a second dielectric layer in a process for forming a modified semiconductor device in some embodiments.

[0032] Figure 171 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming openings in a third dielectric layer and a second dielectric layer in a process for forming a modified semiconductor device in some embodiments.

[0033] Figure 18 1 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a first electrode between two adjacent conductive lines through an opening in a third dielectric layer in a process for forming a modified semiconductor device in some embodiments.

[0034] Figure 19 FIG2 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of forming a dielectric portion on a first electrode in a process for forming a modified semiconductor device in some embodiments.

[0035] Figure 20 is a schematic diagram illustrating a cross-sectional view of an intermediate stage of enlarging an upper portion of an opening in a third dielectric layer in a process for forming a modified semiconductor device in some embodiments.

[0036] The description of the accompanying drawings is as follows:

[0037] 10: Preparation method

[0038] 30: Preparation method

[0039] 100: Semiconductor devices

[0040] 101: Semiconductor substrate

[0041] 103: Dielectric layer

[0042] 103P: protruding part

[0043] 105: Graphical Mask

[0044] 110a: Opening

[0045] 110b: Opening

[0046] 110c: Opening

[0047] 110d: Opening

[0048] 110e: Opening

[0049] 110f: Opening

[0050] 113a: Wire

[0051] 113b: Wire

[0052] 113c: Wire

[0053] 113d: Wire

[0054] 113e: Wire

[0055] 113f: Wire

[0056] 115: Graphical Mask

[0057] 120a: Opening

[0058] 120b: Opening

[0059] 120c: Open

[0060] 120d: Open

[0061] 123: Dielectric layer

[0062] 130a: Opening

[0063] 130b: Opening

[0064] 130c: Opening

[0065] 130d: Opening

[0066] 131a: Air gap

[0067] 131a: Lower part

[0068] 131b: Air Gap

[0069] 131b: Lower part

[0070] 131c: Air Gap

[0071] 131c: lower part

[0072] 131d: Air Gap

[0073] 131d: lower part

[0074] 132a: Upper part

[0075] 132b: Upper part

[0076] 132c: Upper part

[0077] 132d: Upper part

[0078] 135: Dielectric layer

[0079] 137: Graphical Mask

[0080] 140: Opening

[0081] 141: Lower part

[0082] 142: Upper part

[0083] 142': Remaining upper part

[0084] 145: Graphical Mask

[0085] 150a: Opening

[0086] 150b: Open

[0087] 153: Electrode

[0088] 155: Fuse Link

[0089] 157: Electrode

[0090] 159: Fuse structure

[0091] 161a: Wire

[0092] 161b: Wire

[0093] 169: Antifuse structure

[0094] 200: Semiconductor devices

[0095] 201: Semiconductor substrate

[0096] 203: Dielectric layer

[0097] 203P: protruding part

[0098] 213a: Wire

[0099] 213b: Wire

[0100] 213c: Wire

[0101] 213d: Wire

[0102] 213e: Wire

[0103] 213f: Wire

[0104] 223: Dielectric layer

[0105] 230a: Opening

[0106] 230b: Opening

[0107] 230c: Opening

[0108] 230d: Opening

[0109] 231a: Air gap

[0110] 231a: Lower part

[0111] 231b: Air Gap

[0112] 231b: Lower part

[0113] 231c: Air Gap

[0114] 231c: lower part

[0115] 231d: Air Gap

[0116] 231d: lower part

[0117] 232a: Upper part

[0118] 232b: Upper part

[0119] 232c: Upper part

[0120] 232d: Upper part

[0121] 235: Dielectric layer

[0122] 240: Opening

[0123] 241: Lower part

[0124] 242: Upper part

[0125] 242': Remaining upper part

[0126] 250a: Open

[0127] 250b: Open

[0128] 253: Electrode

[0129] 255: Dielectric part

[0130] 257: Electrode

[0131] 259: Antifuse structure

[0132] 261a: Wire

[0133] 261b: Wire

[0134] 269: Fuse structure

[0135] S1: Top surface

[0136] S2: bottom surface

[0137] SW1: Sidewall

[0138] SW2: Sidewall

[0139] W1: width

[0140] W2: width

[0141] W3: Width

[0142] W4: Width

[0143] W5: width

[0144] W8: Width

[0145] W9: Width

[0146] W10: Width DETAILED DESCRIPTION

[0147] The following description of the present disclosure is accompanied by the drawings incorporated in and forming a part of the specification, illustrating an embodiment of the present disclosure, but the present disclosure is not limited to the embodiment. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0148] "One embodiment," "an embodiment," "an exemplary embodiment," "another embodiment," and the like indicate that the embodiments described herein may include particular features, structures, or characteristics. However, not every embodiment is required to include such particular features, structures, or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may.

[0149] To ensure that the present disclosure is fully understood, the following description provides detailed steps and structures. Obviously, the practice of the present disclosure is not limited to the specific details known to those skilled in the art. In addition, known structures and steps are not described in detail to avoid unnecessarily limiting the present disclosure. Preferred embodiments of the present disclosure are described below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

[0150] Figure 1 FIG is a schematic diagram illustrating a semiconductor device of some embodiments in a cross-sectional view. Figure 1 As shown, the semiconductor device 100 includes a semiconductor substrate 101, a dielectric layer 103 (also referred to as a first dielectric layer) disposed on the semiconductor substrate 101, and a plurality of conductive lines 113a, 113b, 113c, 113d, 113e, and 113f. In some embodiments, the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f are parallel to each other, and the dielectric layer 103 has a protruding portion 103P disposed between the conductive lines 113d and 113e.

[0151] Furthermore, semiconductor device 100 includes a dielectric layer 123 (also referred to as a second dielectric layer) disposed over dielectric layer 103 and conductive lines 113a, 113b, 113c, 113d, 113e, and 113f, and a dielectric layer 135 (also referred to as a third dielectric layer) disposed over dielectric layer 123. In some embodiments, top surfaces and sidewalls of conductive lines 113a, 113b, 113c, 113d, 113e, and 113f are covered by dielectric layer 123. In other words, dielectric layer 123 extends into the spaces between conductive lines 113a, 113b, 113c, 113d, 113e, and 113f.

[0152] In some embodiments, the semiconductor device 100 includes a plurality of air gaps 131b, 131c, 131d enclosed by dielectric layers 123, 135. Figure 1 As shown, air gap 131b is located between conductive lines 113b and 113c, air gap 131c is located between conductive lines 113c and 113d, and air gap 131d is located between conductive lines 113e and 113f. In some embodiments, top surface S1 of dielectric layer 123 is higher than bottom surface S2 of dielectric layer 135 (bottom surface S2 of dielectric layer 135 is also considered the interface between dielectric layer 135 and air gap 131b).

[0153] Furthermore, semiconductor device 100 includes an electrode 153 disposed in dielectric layer 123 and between conductive lines 113a and 113b, a fuse link 155 disposed above electrode 153, and an electrode 157 disposed above fuse link 155. In some embodiments, the lower portions of electrode 153, fuse link 155, and electrode 157 are surrounded by dielectric layer 123, and the upper portion of electrode 157 is surrounded by dielectric layer 135. Furthermore, semiconductor device 100 includes a plurality of conductive lines 161a and 161b disposed in the upper portion of dielectric layer 135. In some embodiments, conductive line 161a is disposed above electrode 157.

[0154] It should be noted that in some embodiments, electrode 153 (also referred to as the first electrode), fuse link 155, and electrode 157 (also referred to as the second electrode) form a fuse structure 159. Furthermore, electrode 153, a conductive line adjacent to electrode 153 (e.g., conductive line 113b, also referred to as the third electrode), and a portion of dielectric layer 123 therebetween form an antifuse structure (e.g., antifuse structure 169). By integrating vertical fuse structure 159 and lateral antifuse structure 169 into semiconductor device 100, the integration of semiconductor device 100 is enhanced.

[0155] like Figure 1As shown, electrode 153 has a width W1, fuse link 155 has a width W3, and electrode 157 has a width W4. In some embodiments, width W4 is greater than width W1, and width W1 is greater than width W3. Furthermore, conductive line 161a has a width W5. In some embodiments, width W5 is greater than width W4 of electrode 157.

[0156] Figure 2 Schematic diagrams illustrate a modified semiconductor device 200 in some embodiments in a cross-sectional view. Similar to semiconductor device 100, semiconductor device 200 includes a semiconductor substrate 201, a dielectric layer 203 (also referred to as a first dielectric layer) disposed on semiconductor substrate 201, and a plurality of conductive lines 213a, 213b, 213c, 213d, 213e, and 213f. In some embodiments, conductive lines 213a, 213b, 213c, 213d, 213e, and 213f are parallel to each other, and dielectric layer 203 has a protrusion 203P disposed between conductive lines 213d and 213e.

[0157] Furthermore, the semiconductor device 200 includes a dielectric layer 223 (also referred to as a second dielectric layer) disposed on the dielectric layer 203 and the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f, and a dielectric layer 235 (also referred to as a third dielectric layer) disposed on the dielectric layer 223. In some embodiments, the semiconductor device 200 includes an air gap 231b disposed between the conductive lines 213b and 213c, and an air gap 231d disposed between the conductive lines 213e and 213f. In some embodiments, a top surface S1 of the dielectric layer 223 is higher than a bottom surface S2 of the dielectric layer 235 (the bottom surface S2 of the dielectric layer 235 is also referred to as the interface between the dielectric layer 235 and the air gap 231b). In some embodiments, the programming mechanism of the antifuse structure creates a short circuit or a relatively low resistance link therein, and Figure 2 The fuse structure 269 in the embodiment can be viewed as Figure 1 The structure of the anti-fuse structure 169 after programming.

[0158] The difference between semiconductor device 100 and semiconductor device 200 is that air gaps 231b, 231c, and 231d in semiconductor device 200 are enclosed by dielectric layer 223, dielectric layer 235, and conductive lines 213b, 213c, 213d, 213e, and 213f. In some embodiments, portions of the sidewalls of conductive lines 213b, 213c, 213d, 213e, and 213f are exposed through air gaps 231b, 231c, and 231d. For example, sidewall SW1 of conductive line 213b and sidewall SW2 of conductive line 213c are partially exposed through air gap 231b.

[0159] Furthermore, semiconductor device 200 includes an electrode 253 disposed in dielectric layer 223 and between conductive lines 213a and 213b, a dielectric portion 255 disposed above electrode 253, and an electrode 257 disposed above dielectric portion 255. In some embodiments, electrode 253 is in direct contact with conductive lines 213a and 213b. In some embodiments, lower portions of electrode 253, electrode 253, and electrode 257 are surrounded by dielectric layer 223, and an upper portion of electrode 257 is surrounded by dielectric layer 235. Furthermore, semiconductor device 200 includes a plurality of conductive lines 261a and 261b disposed in the upper portion of dielectric layer 235. In some embodiments, conductive line 261a is disposed above electrode 257.

[0160] It should be noted that in some embodiments, electrode 253 (also referred to as the first electrode), electrode 253, and electrode 257 (also referred to as the second electrode) form an antifuse structure 259, and electrode 253 and a conductive line adjacent to electrode 253 (e.g., conductive line 213b, also referred to as the third electrode) form a fuse structure (e.g., fuse structure 269). By integrating the vertical antifuse structure 259 and the lateral fuse structure 269 into the semiconductor device 200, the integration of the semiconductor device 200 is improved.

[0161] like Figure 2 As shown, electrode 253 has a width W1, dielectric portion 255 has a width W8, and electrode 257 has a width W9. In some embodiments, widths W1 and W9 are greater than width W8. Additionally, conductive line 261a has a width W10. In some embodiments, width W10 is greater than width W9 of electrode 257.

[0162] Figure 3 1 is a schematic diagram illustrating a flow chart of a method 10 for fabricating a semiconductor device 100 in some embodiments. The method 10 includes steps S11 , S13 , S15 , S17 , S19 and S21 . Figure 4 2 is a schematic diagram illustrating a flow chart of a method 30 for manufacturing a semiconductor device 200 in some embodiments. The method 30 includes S31 , S33 , S35 , S37 , S39 , S41 , S43 and S45 . Figure 3 Steps S11 to S21 and Figure 4 S31 to S45 are described in detail in the following figures.

[0163] Figures 5 to 14 is a schematic diagram illustrating an intermediate stage of forming a semiconductor device 100 in some embodiments in a cross-sectional view. Figure 5 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 is a semiconductor wafer, such as a silicon wafer.

[0164] Alternatively or additionally, the semiconductor substrate 101 includes an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0165] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 includes an epitaxial layer covering a semiconductor layer. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, comprising a substrate, a buried oxide layer located above the substrate, and a semiconductor layer located above the buried oxide layer. For example, the semiconductor substrate 101 may be a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (SOG) substrate. The semiconductor-on-insulator substrate may be fabricated using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable fabrication methods.

[0166] Also refer to Figure 5 In some embodiments, a dielectric layer 103 is formed on the semiconductor substrate 101. The respective steps are described in Figure 3 Step S11 in preparation method 10. In some embodiments, dielectric layer 103 is formed of a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) less than 4. Examples of low-k dielectric materials, but not limited to, include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), fluorinated silicate glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide.

[0167] In addition, the dielectric layer 103 is formed by a deposition process. The deposition process includes a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other feasible processes. Figure 5 As shown, in some embodiments, after the dielectric layer 103 is formed, a patterned mask 105 is formed on the dielectric layer 103 .

[0168] like Figure 6As shown, in some embodiments, the dielectric layer 103 is then etched using the patterned mask 105 as a mask to form openings 110a, 110b, 110c, 110d, 110e, and 110f in the dielectric layer 103. In some embodiments, the openings 110a, 110b, 110c, 110d, 110e, and 110f are parallel to each other.

[0169] In some embodiments, each opening 110a, 110b, 110c, 110d, 110e, and 110f has substantially the same width. In some embodiments, each adjacent pair of openings 110a, 110b, 110c, 110d, 110e, and 110f has substantially the same distance. In this disclosure, the term "substantially" means at least 90%, preferably 95%, more preferably 98%, and most preferably 99%. In some embodiments, the dielectric layer 103 is etched using a wet etch process, a dry etch process, or a combination thereof. After the etch process, the patterned mask 105 is removed.

[0170] like Figure 6 As shown, in some embodiments, conductive lines 113a, 113b, 113c, 113d, 113e, and 113f are then formed in openings 110a, 110b, 110c, 110d, 110e, and 110f. Figure 3 Step S13 of the manufacturing method 10 : At this stage, the conductive lines 113 a , 113 b , 113 c , 113 d , 113 e , and 113 f are surrounded by the dielectric layer 103 .

[0171] In some embodiments, the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable conductive materials. Forming the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f includes conformally depositing a conductive material (not shown) on the dielectric layer 103 to fill the openings 110a, 110b, 110c, 110d, 110e, and 110f; and performing a planarization process to remove excess conductive material above the top surface of the dielectric layer 103. The deposition process for forming the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f includes a CVD process, a PVD process, an ALD process, an electroplating process, a sputtering process, or a combination thereof. The planarization process for forming the conductive lines 113 a , 113 b , 113 c , 113 d , 113 e , and 113 f may include a chemical mechanical polishing (CMP) process.

[0172] like Figure 7As shown, in some embodiments, after the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f are formed, a patterned mask 115 is formed on the dielectric layer 103. In some embodiments, the patterned mask 115 is provided to protect certain areas of the dielectric layer 103 so that they remain intact during subsequent etching processes.

[0173] like Figure 8 As shown, in some embodiments, the dielectric layer 103 is then etched using the patterned mask 115 and the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f as masks to form a plurality of openings 120a, 120b, 120c, and 120d between the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f. In some embodiments, the etching process is performed until the top surface of the dielectric layer 103 between the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f is substantially flush with the bottom surface of the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f.

[0174] In some embodiments, the etching process for forming the openings 120a, 120b, 120c, and 120d is a wet etching process, a dry etching process, or a combination thereof. Furthermore, in some embodiments, after the etching process, the protruding portion 103P of the dielectric layer 103 shielded by the patterned mask 115 remains intact. The patterned mask 115 is removed to expose the protruding portion 103P.

[0175] like Figure 9 As shown, in some embodiments, after forming the openings 120a, 120b, 120c, and 120d, the dielectric layer 123 is conformally deposited on the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f. Figure 3 Step S15 in the manufacturing method 10 . In some embodiments, the top surface of the protruding portion 103P of the dielectric layer 103 is covered by the dielectric layer 123 .

[0176] In some embodiments, dielectric layer 123 extends into openings 120a, 120b, 120c, and 120d to line the sidewalls of conductive lines 113a, 113b, 113c, 113d, 113e, and 113f, forming openings 130a, 130b, 130c, and 130d between conductive lines 113a, 113b, 113c, 113d, 113e, and 113f. Furthermore, dielectric layer 123 includes a neck portion located at the top portion of openings 130a, 130b, 130c, and 130d. In some embodiments, each opening 130a, 130b, 130c, and 130d includes a bottom portion and a top portion. For example, opening 130a includes a lower portion 131a and an upper portion 132a; opening 130b includes a lower portion 131b and an upper portion 132b; opening 130c includes a lower portion 131c and an upper portion 132c; and opening 130d includes a lower portion 131d and an upper portion 132d.

[0177] Also refer to Figure 9 In some embodiments, the width of the lower portion of each opening 130a, 130b, 130c, and 130d is greater than the width of the corresponding upper portion. For example, the lower portion 131a of the opening 130a has a width W1, and the upper portion 132a of the opening 130a has a width W2, where the width W1 is greater than the width W2. Furthermore, the dielectric layer 123 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials, and is formed by a CVD process, a plasma-enhanced chemical vapor deposition (PECVD) process, or other suitable processes.

[0178] like Figure 10 As shown, in some embodiments, a dielectric layer 135 is then formed on the dielectric layer 123. In some embodiments, the openings 130a, 130b, 130c, 130d are not completely filled with the dielectric layer 135 to form air gaps 131b, 131c, 131d. Figure 3 Step S17 in preparation method 10.

[0179] In some embodiments, dielectric layer 135 extends to fill upper portions 132a, 132b, 132c, 132d of openings 130a, 130b, 130c, 130d, while the remaining portions of openings 130a, 130b, 130c, 130d (i.e., lower portions 131a, 131b, 131c, 131d) are sealed by dielectric layer 135 and dielectric layer 123 to form air gaps 131a, 131b, 131c, 131d. Certain materials and processes for forming dielectric layer 135 are similar or identical to those used to form dielectric layer 123, and the details are not repeated here. In some embodiments, dielectric layer 135 is formed of a material having a high etch selectivity relative to the material of dielectric layer 123.

[0180] like Figure 11 As shown, in some embodiments, after forming the air gaps 131a, 131b, 131c, and 131d, a patterned mask 137 is formed on the dielectric layer 135. Figure 12 As shown, in some embodiments, the dielectric layer 135 is then etched using the patterned mask 137 as a mask to form an opening 140 penetrating the dielectric layer 135. The etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0181] In some embodiments, the opening 140 extends from the dielectric layer 135 to the dielectric layer 123 to connect the air gap 131a. Figure 3 Step S19 in the preparation method 10. As described above, since the dielectric layer 135 is formed of a material having a high etching selectivity compared to the material of the dielectric layer 123, the dielectric layer 123 is only slightly removed when the dielectric layer 135 is etched through. The etching process is performed until the closed air gap 131a is opened.

[0182] Specifically, the opening 140 includes a lower portion 141 and an upper portion 142. In some embodiments, the lower portion 141 of the opening 140 has a width W3, and the upper portion 142 of the opening 140 has a width W4, and the width W4 is greater than the width W3. After the opening 140 is obtained, the patterned mask 137 is removed.

[0183] like Figure 13 As shown, in some embodiments, a patterned mask 145 is then formed on the dielectric layer 135. Figure 14 As shown, in some embodiments, the dielectric layer 135 is then etched using the patterned mask 145 as a mask to form openings 150b, 150b in the upper portion of the dielectric layer 135. The etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0184] In some embodiments, opening 150a is formed by enlarging the upper portion of opening 140. After the etching process that forms openings 150a and 150b, opening 150a is connected to the remaining upper portion 142' of opening 140. Specifically, opening 150a has a width W5 that is greater than the width W4 of the remaining upper portion 142' of opening 140. After openings 150a and 150b are formed, patterned mask 145 is removed.

[0185] Reference Figure 1 In some embodiments, a conductive material is deposited to form the electrode 153 at the exposed air gap 131a, the fuse link 15 at the lower portion 141 of the opening 140, the electrode 157 at the remaining upper portion 142' of the opening 140, and the conductive lines 161a, 161b at the openings 150a, 150b. The respective steps are described in Figure 3 Step S21 of the fabrication method 10. In some embodiments, the electrodes 153, 157, the fuse link 155, and the conductive lines 161a, 161b are formed by a deposition process and a subsequent planarization process. In other words, the electrodes 153, 157, the fuse link 155, and the conductive lines 161a, 161b are formed simultaneously.

[0186] In some embodiments, electrodes 153, 157, fuse link 155, and conductive lines 161a, 161b include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable conductive materials. Forming electrodes 153, 157, fuse link 155, and conductive lines 161a, 161b includes conformally depositing a conductive material (not shown) on dielectric layer 135 to fill air gap 131a, opening 140, and openings 150a, 150b. A planarization process is then performed to remove excess conductive material from the top surface of dielectric layer 135.

[0187] The deposition process for forming electrodes 153, 157, fuse link 155, and conductive lines 161a, 161b may include a CVD process, a PVD process, an ALD process, an electroplating process, a sputtering process, or a combination thereof. The planarization process for forming electrodes 153, 157, fuse link 155, and conductive lines 161a, 161b may include a CMP process. After the planarization process, semiconductor device 100 is obtained.

[0188] Figures 15 to 20 is a schematic diagram illustrating an intermediate stage of forming a modified semiconductor device 200 in some embodiments in a cross-sectional view. Figure 15 As shown, a semiconductor substrate 201 is provided. Some materials used to form the semiconductor substrate 201 are similar or identical to the materials or processes used to form the semiconductor substrate 101 of the semiconductor device 100, and the details thereof are not repeated here.

[0189] like Figure 15 As shown, in some embodiments, in addition, a dielectric layer 203 having a protruding portion 203P is formed on the semiconductor substrate 201, and conductive lines 213a, 213b, 213c, 213d, 213e, and 213f are formed on the dielectric layer 203. Figure 4 Steps S31 and S33 in the preparation method 30 include the following: certain materials and processes for forming the dielectric layer 203 and the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f are similar or identical to the materials or processes for forming the dielectric layer 103 and the conductive lines 113a, 113b, 113c, 113d, 113e, and 113f of the semiconductor device 100, and the details thereof are not repeated here.

[0190] In some embodiments, a dielectric layer 223 is then conformally formed on the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f. Figure 4 Step S35 in the manufacturing method 30 . In some embodiments, the top surface of the protruding portion 203P of the dielectric layer 203 is covered by the dielectric layer 223 .

[0191] In some embodiments, the dielectric layer 223 extends to the spaces between the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f and lines the sidewalls of the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f to form openings 230a, 230b, 230c, and 230d between the conductive lines 213a, 213b, 213c, 213d, 213e, and 213f. Furthermore, each opening 230a, 230b, 230c, and 230d includes a bottom portion and a top portion. For example, opening 230a includes a lower portion 231a and an upper portion 232a; opening 230b includes a lower portion 231b and an upper portion 232b; opening 230c includes a lower portion 231c and an upper portion 232c; and opening 230d includes a lower portion 231d and an upper portion 232d.

[0192] In some embodiments, the width of the lower portion of each opening 230a, 230b, 230c, 230d is greater than the width of the corresponding upper portion. For example, the lower portion 231a of the opening 230a has a width W6, and the upper portion 232a of the opening 230a has a width W7, and the width W6 is greater than the width W7. In some embodiments, Figure 15 The width W7 is greater than Figure 9 The width W1 in .

[0193] Certain materials and processes used to form dielectric layer 223 are similar or identical to those used to form dielectric layer 123 of semiconductor device 100, and the details are not repeated here. It should be noted that the deposition process for forming dielectric layer 223 is controlled to partially expose the sidewalls of conductive lines 213a, 213b, 213c, 213d, 213e, and 213f. For example, sidewall SW1 of conductive line 213b and sidewall SW2 of conductive line 213c are partially exposed through lower portion 231b of opening 230b.

[0194] like Figure 16 As shown, in some embodiments, a dielectric layer 235 is formed on the dielectric layer 223. In some embodiments, the openings 230a, 230b, 230c, 230d are not completely filled with the dielectric layer 235 to form air gaps 231a, 231b, 231c, 231d. Figure 4 Step S37 in preparation method 30.

[0195] In some embodiments, dielectric layer 235 extends to fill upper portions 232a, 232b, 232c, 232d of openings 230a, 230b, 230c, 230d, while the remaining portions of openings 230a, 230b, 230c, 230d (i.e., lower portions 231a, 231b, 231c, 231d) are sealed by dielectric layer 235 and dielectric layer 223 to form air gaps 231a, 231b, 231c, 231d. Certain materials and processes for forming dielectric layer 235 are similar or identical to those used to form dielectric layer 135 of semiconductor device 100, and the details are not repeated here. In some embodiments, dielectric layer 235 is formed of a material having a high etch selectivity relative to the material of dielectric layer 223.

[0196] like Figure 17 As shown, in some embodiments, after obtaining the air gaps 231a, 231b, 231c, and 231d, the dielectric layer 235 is etched to form an opening 240 penetrating the dielectric layer 235 and exposing the air gap 231a. Figure 4 Step S39 in the preparation method 30. The etching process includes a wet etching process, a dry etching process, or a combination thereof, and a patterned mask (not shown) may be used to perform the etching process.

[0197] In some embodiments, opening 240 extends from dielectric layer 235 to dielectric layer 223 to connect air gap 231a. As previously described, because dielectric layer 223 is formed of a material having a high etch selectivity relative to the material of dielectric layer 223, dielectric layer 223 is only slightly removed when dielectric layer 235 is etched through. The etching process is performed until the enclosed air gap 231a is opened. Specifically, opening 240 includes a lower portion 241 and an upper portion 242. In some embodiments, lower portion 241 of opening 240 has a width W8, and upper portion 242 of opening 240 has a width W9, where width W9 is greater than width W8.

[0198] like Figure 18 As shown, in some embodiments, the air gap 231a is then filled with the electrode 253. The respective steps are described in Figure 4 Step S41 in the preparation method 30. In some embodiments, the electrode 253 is in direct contact with the wires 213a and 213b.

[0199] In some embodiments, electrode 253 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable conductive materials. Forming electrode 253 includes conformally depositing a conductive material (not shown) on dielectric layer 235 to fill air gap 231a and opening 240, and performing an etch-back process to recess the conductive material so that opening 240 is not completely filled. The deposition process for forming electrode 253 includes a CVD process, a PVD process, an ALD process, an electroplating process, a sputtering process, or a combination thereof.

[0200] like Figure 19 As shown, in some embodiments, the lower portion 241 of the opening 240 is then filled with the dielectric portion 255. The respective steps are described in Figure 4 Step S43 in the preparation method 30 . In some embodiments, the dielectric portion 255 is formed on the electrode 253 .

[0201] In some embodiments, dielectric portion 255 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. Forming dielectric portion 255 includes conformally depositing a dielectric material (not shown) over dielectric layer 235 and filling opening 240, and performing an etch-back process to recess the dielectric material so that upper portion 242 of opening 240 is not filled. The deposition process for forming dielectric portion 255 includes a CVD process, a PVD process, an ALD process, or a combination thereof.

[0202] like Figure 20 As shown, in some embodiments, the dielectric layer 235 is then etched to form openings 250a, 250b in the upper portion of the dielectric layer 235. The respective steps are described in Figure 4Step S39 in the preparation method 30. The etching process includes a wet etching process, a dry etching process, or a combination thereof, and a patterned mask (not shown) may be used to perform the etching process.

[0203] In some embodiments, opening 250a is formed by enlarging the upper portion of opening 240. After the etching process forming openings 250a and 250b, opening 250a is connected to the remaining upper portion 242' of opening 240. Specifically, opening 250a has a width W10 that is greater than the width W9 of the remaining upper portion 242' of opening 240.

[0204] Reference Figure 2 In some embodiments, a conductive material is deposited to form the electrode 257 on the remaining upper portion 242' of the opening 240 and the conductive lines 261a, 261b on the openings 250a, 250b. Figure 4 Step S45 in the preparation method 30. In some embodiments, the electrode 257 and the conductive lines 261a, 261b are formed by a deposition process and a subsequent planarization process. In other words, the electrode 257 and the conductive lines 261a, 261b are formed simultaneously.

[0205] In some embodiments, the electrode 257 and the conductive lines 261 a and 261 b include aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable conductive materials. Forming the electrode 257 and the conductive lines 261 a and 261 b includes conformally depositing a conductive material (not shown) on the dielectric layer 235 to fill the remaining upper portion 242 ′ of the opening 240 and the openings 250 a and 250 b. A planarization process is then performed to remove excess conductive material above the top surface of the dielectric layer 235.

[0206] The deposition process for forming the electrode 257 and the conductive lines 261a and 261b includes a CVD process, a PVD process, an ALD process, an electroplating process, a sputtering process, or a combination thereof. The planarization process for forming the electrode 257 and the conductive lines 261a and 261b includes a CMP process. After the planarization process, the semiconductor device 200 is obtained.

[0207] Embodiments of the present disclosure provide semiconductor devices 100 and 200. In some embodiments, semiconductor device 100 includes a fuse link 155 disposed on electrode 153, an electrode 157 disposed on fuse link 155, a conductive line 113b disposed adjacent to electrode 153, and a dielectric layer 123 separating electrode 153 from conductive line 113b. Electrode 153, fuse link 155, and electrode 157 form a vertical fuse structure 159, while electrode 153, conductive line 113b, and a portion of dielectric layer 123 located between electrode 153 and conductive line 113b form a lateral antifuse structure 169. Thus, vertical fuse structure 159 and lateral antifuse structure 169 are integrated. In some embodiments, semiconductor device 200 includes a dielectric portion 255 disposed on electrode 253, an electrode 257 disposed on dielectric portion 255, and conductive line 213b adjacent to and directly contacting electrode 253. Electrode 253, dielectric portion 255, and electrode 257 form a vertical antifuse structure 259, while electrode 253 and conductive line 213b form a lateral fuse structure 269. Thus, the vertical antifuse structure 259 and the lateral fuse structure 269 are integrated, thereby improving the integration of the semiconductor device.

[0208] One embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a first electrode disposed on the first dielectric layer. The semiconductor device also includes a fuse link disposed on the first electrode, and a second electrode disposed on the fuse link. The semiconductor device also includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer located between the first electrode and the third electrode form an antifuse structure.

[0209] Another embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a first conductive line and a second conductive line disposed on the first dielectric layer and extending parallel to each other. The semiconductor device includes a second dielectric layer disposed between the first conductive line and the second conductive line. The first conductive line and the second conductive line are covered by the second dielectric layer. The semiconductor device also includes a third dielectric layer disposed on the second dielectric layer. The third dielectric layer has an etching selectivity different from that of the second dielectric layer. In addition, the semiconductor device includes a first electrode disposed between the first conductive line and the second conductive line. The first electrode has a circular profile, and the first electrode is separated from the first dielectric layer by a second dielectric layer. The semiconductor device also includes a second electrode disposed on the first electrode. The second electrode extends from the second dielectric layer to the third dielectric layer.

[0210] In another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first dielectric layer disposed on a semiconductor substrate, and a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a first electrode disposed within the second dielectric layer, and a dielectric portion disposed on the first electrode. The semiconductor device also includes a second electrode disposed on the dielectric portion, and a third electrode adjacent to and directly contacting the first electrode. The first electrode, the dielectric portion, and the second electrode form an antifuse structure, and the first electrode and the third electrode form a fuse structure.

[0211] The embodiments of the present disclosure have certain advantageous features; for example, by integrating a fuse structure and an antifuse structure into a semiconductor device, the integration of the semiconductor device is improved.

[0212] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0213] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor device comprising: a first dielectric layer disposed on a semiconductor substrate; A first conductive line and a second conductive line are disposed on the first dielectric layer and extend parallel to each other; a second dielectric layer disposed between the first conductive line and the second conductive line, wherein the first conductive line and the second conductive line are covered by the second conductive line; a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has an etching selectivity different from that of the second dielectric layer; a first electrode disposed between the first conductive line and the second conductive line, wherein the first electrode has a circular profile and is separated from the first dielectric layer by the second dielectric layer; a second electrode disposed on the first electrode, wherein the second electrode extends from the second dielectric layer to the third dielectric layer; and a dielectric portion disposed between the first electrode and the second electrode, wherein the first electrode, the second electrode, and the dielectric portion form an antifuse structure; The first electrode is in direct contact with the first conductive line, and the first electrode and the first conductive line form a fuse structure. 2 . The semiconductor device of claim 1 , wherein the dielectric portion has a first width, the second electrode has a second width, and the second width is greater than the first width.

3. The semiconductor device according to claim 1 , further comprising: A third conductive line is disposed on the first dielectric layer and parallel to the first conductive line, wherein the first conductive line is located between the second conductive line and the third conductive line, and wherein an air gap exists between the first conductive line and the third conductive line, and the air gap is sealed by the third dielectric layer. 4 . The semiconductor device as claimed in claim 3 , wherein a sidewall of the first conductive line and a sidewall of the third conductive line are exposed through the air gap.

5. A semiconductor device comprising: a first dielectric layer disposed on a semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a first electrode disposed in the second dielectric layer; a dielectric portion disposed on the first electrode; a second electrode disposed on the dielectric portion; and a third electrode adjacent to and in direct contact with the first electrode, wherein the first electrode, the dielectric portion, and the second electrode form an antifuse structure, and wherein the first electrode and the third electrode form a fuse structure, The dielectric portion is surrounded by the second dielectric layer, the first electrode has a first width, the dielectric portion has a second width, and the first width is greater than the second width. 6 . The semiconductor device of claim 5 , wherein the first electrode is separated from the first dielectric layer by the second dielectric layer, and the third electrode is in direct contact with the first dielectric layer. 7 . The semiconductor device of claim 5 , wherein the third electrode is sandwiched between the first electrode and an air gap in the second dielectric layer, and wherein the first electrode and the air gap have circular profiles in a cross-sectional view.

8. The semiconductor device according to claim 7, further comprising: A third dielectric layer is disposed on the second dielectric layer and surrounds the second electrode, wherein a top surface of the second dielectric layer is higher than an interface between the third dielectric layer and the air gap.

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