Packaging structure

Abstract

This application provides a packaging structure, including: a substrate; an interposer layer disposed on the substrate via solder bumps; the interposer layer including a connection structure; a first semiconductor chip and a second semiconductor chip disposed on the interposer layer via solder bumps; and at least one controllable switching device disposed in the interposer layer; wherein, the same solder bump of the first semiconductor chip is connected to any one of the different solder bumps of the second semiconductor chip or the interposer layer via the controllable switching device and the connection structure; or, any one of the different solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip or the interposer layer via the controllable switching device and the connection structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a packaging structure. BACKGROUND

[0002] With the trend of small size and high performance of semiconductor chips, when packaging semiconductor chips, a System In a Package (SIP) technology is needed for embedding multiple semiconductor chips into a single packaging structure; a technology for connecting the solder bumps (hereinafter also referred to as microbumps) of semiconductor chips of different processes through an interposer, and connecting the solder bumps of semiconductor chips and the solder bumps of a packaging structure substrate through an interposer.

[0003] However, the connection mode between different semiconductor chips and between the semiconductor chip and the substrate in the related art is relatively fixed, and when the connection relationship changes, it is necessary to re-design the flow sheet, resulting in a long cycle and high cost. SUMMARY

[0004] To solve the problems in the related art, an embodiment of the present application provides a packaging structure, comprising:

[0005] a substrate;

[0006] an interposer disposed on the substrate through solder bumps; the interposer comprises a connection structure;

[0007] a first semiconductor chip and a second semiconductor chip disposed on the interposer through solder bumps;

[0008] at least one controllable switching device disposed in the interposer; wherein,

[0009] the same solder bump of the first semiconductor chip is connected to any one of different solder bumps of the second semiconductor chip or the interposer through the controllable switching device and the connection structure;

[0010] Alternatively,

[0011] any one of different solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip or the interposer through the controllable switching device and the connection structure.

[0012] In the above scheme, the interposer comprises a conductive wire; wherein,

[0013] the same solder bump of the first semiconductor chip is connected to any one of different solder bumps of the second semiconductor chip through the controllable switching device and the conductive wire;

[0014] or,

[0015] Any one of the plurality of solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip through a controllable switching device and a conductive wire.

[0016] In the above solution, the controllable switching device is arranged between two physically connected conductive wires.

[0017] In the above solution, the first solder bump of the first semiconductor chip is connected to the first solder bump of the second semiconductor chip through a first conductive wire, a first controllable switching device and a second conductive wire, and the first solder bump of the first semiconductor chip is connected to the second solder bump of the second semiconductor chip through a third conductive wire, a second controllable switching device and a fourth conductive wire; wherein, by controlling the connection state or the open state of the first controllable switching device and the second controllable switching device, the first solder bump of the first semiconductor chip is connected to the first solder bump or the second solder bump of the second semiconductor chip.

[0018] or,

[0019] The second solder bump of the first semiconductor chip is connected to the third solder bump of the second semiconductor chip through a fifth conductive wire, a third controllable switching device and a sixth conductive wire, and the third solder bump of the first semiconductor chip is connected to the third solder bump of the second semiconductor chip through a seventh conductive wire, a fourth controllable switching device and an eighth conductive wire; wherein, by controlling the connection state or the open state of the third controllable switching device and the fourth controllable switching device, the second solder bump or the third solder bump of the first semiconductor chip is connected to the third solder bump of the second semiconductor chip.

[0020] In the above solution, the interposer includes: a conductive wire and a conductive pillar; wherein,

[0021] Any one of the different solder bumps of the first semiconductor chip is connected to the same solder bump of the interposer through the controllable switching device, the conductive wire and the conductive pillar;

[0022] or,

[0023] The same solder bump of the first semiconductor chip is connected to any one of the different solder bumps of the interposer through the controllable switching device, the conductive wire and the conductive pillar.

[0024] In the above solution, the controllable switching device is arranged between two physically connected solder bumps of the first semiconductor chip and a conductive wire.

[0025] In the scheme, the fourth solder bump of the first semiconductor chip is connected with the first solder bump of the interposer through the fifth controllable switching device, the ninth conductive wire and the first conductive column, and the fourth solder bump of the first semiconductor chip is connected with the second solder bump of the interposer through the sixth controllable switching device, the tenth conductive wire and the second conductive column; wherein, by controlling the connection state or the open state of the fifth controllable switching device and the sixth controllable switching device, the fourth solder bump of the first semiconductor chip is connected with the first solder bump or the second solder bump of the interposer.

[0026] Or,

[0027] The fifth solder bump of the first semiconductor chip is connected with the third solder bump of the interposer through the seventh controllable switching device, the eleventh conductive wire and the third conductive column, and the sixth solder bump of the first semiconductor chip is connected with the third solder bump of the interposer through the eighth controllable switching device, the twelfth conductive wire and the third conductive column; wherein, by controlling the connection state or the open state of the seventh controllable switching device and the eighth controllable switching device, the fifth solder bump or the sixth solder bump of the first semiconductor chip is connected with the third solder bump of the interposer.

[0028] In the scheme, the first semiconductor chip includes a control chip, and the first semiconductor chip is electrically connected with the controllable switching device, and is used for controlling the controllable switching device to be in the connection state or the open state.

[0029] In the scheme, the controllable switching device includes a transistor.

[0030] In the scheme, the interposer includes one wiring layer or a plurality of stacked wiring layers.

[0031] The controllable switching device includes a plurality of controllable switching devices, and the plurality of controllable switching devices are arranged in the same wiring layer or different wiring layers of the interposer.

[0032] In the scheme, the controllable switching device includes a plurality of controllable switching devices, and the distance between two adjacent controllable switching devices in the plurality of controllable switching devices is 50-5000 μm.

[0033] The application also provides another packaging structure, which includes:

[0034] A substrate, wherein a wiring layer and a plurality of bonding pads are arranged on the surface of the substrate.

[0035] One or more first semiconductor chips are arranged on the substrate, and a wiring layer and a plurality of bonding pads are arranged on the surface of the first semiconductor chip.

[0036] a bonding wire disposed between a bonding pad of the substrate and a bonding pad of the first semiconductor chip for connecting one bonding pad of the substrate and one bonding pad of the first semiconductor chip;

[0037] at least one controllable switching device disposed in a wiring layer of the substrate or the first semiconductor chip; wherein,

[0038] any one of different bonding pads of the first semiconductor chip is connected to the same bonding pad of the substrate through the controllable switching device and the bonding wire;

[0039] or,

[0040] any one of different bonding pads of the first semiconductor chip is connected to the same bonding pad of the substrate through the controllable switching device and the bonding wire.

[0041] Embodiments of the present application provide a packaging structure, comprising: a substrate; an interposer disposed on the substrate through a solder bump; the interposer comprising a connection structure; a first semiconductor chip and a second semiconductor chip disposed on the interposer through a solder bump; at least one controllable switching device disposed in the interposer; wherein, the same solder bump of the first semiconductor chip is connected to any one of different solder bumps of the second semiconductor chip or the interposer through the controllable switching device and the connection structure; or, any one of different solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip or the interposer through the controllable switching device and the connection structure. The packaging structure provided by embodiments of the present application connects different process semiconductor chips (i.e. the first semiconductor chip and the second semiconductor chip) or the semiconductor chip and the substrate, and if the connection relationship needs to be adjusted, only one or more states of the controllable switching device need to be modified through a control instruction to adaptively complete the required connection relationship change. Thus, the packaging structure provided by embodiments of the present application supports adjustable connection relationship between devices, is flexible in application, and can improve the long process cycle and high repeated manufacturing cost caused by design errors in the semiconductor chip manufacturing process. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 a schematic diagram of a packaging structure provided by embodiments of the present application;

[0043] Figure 2 a schematic diagram of another packaging structure provided by embodiments of the present application;

[0044] Figures 3a to 3d schematic diagrams of other packaging structures provided by embodiments of the present application;

[0045] Figure 4 A projection plane layout of a controllable switching device in a packaging structure according to an embodiment of the present application is shown in the following figure;

[0046] Figures 5a to 5b Some schematic diagrams of packaging structures according to embodiments of the present application are shown in the following figures.

[0047] Explanation of reference numerals

[0048] 1 - substrate; 2 - interposer; 21 - conductive line; 23 - conductive pillar; 3 - first semiconductor chip; 4 - second semiconductor chip; 5 - solder bump;

[0049] 10 - substrate; 20 - interposer; 21 - conductive line; 201-212 - first to twelfth conductive lines; 22 - controllable switching device; 22a - controllable switching device in a connected state; 22b - controllable switching device in a disconnected state; 221-228 - first to eighth controllable switching devices; 23 - conductive pillar; 231-233 - first to third conductive pillars; 30 - first semiconductor chip; 40 - second semiconductor chip; 50 - solder bump; 501 - first solder bump of the first semiconductor chip; 502 - first solder bump of the second semiconductor chip; 503 - second solder bump of the second semiconductor chip; 504 - second solder bump of the first semiconductor chip; 505 - third solder bump of the first semiconductor chip; 506 - third solder bump of the second semiconductor chip; 507 - fourth solder bump of the first semiconductor chip; 508 - first solder bump of the interposer; 509 - second solder bump of the interposer; 510 - fifth solder bump of the first semiconductor chip; 511 - sixth solder bump of the first semiconductor chip; 512 - third solder bump of the interposer; S - spacing;

[0050] 100 - substrate; 101 - wiring layer of the substrate; 102 - bonding pad of the substrate; 300 - first semiconductor chip; 301 - wiring layer of the first semiconductor chip; 302 - bonding pad of the first semiconductor chip; 201-205 - bonding wire; 201-224 - controllable switching device. DETAILED DESCRIPTION

[0051] The technical solutions of the present application will be further described in detail below in combination with the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0052] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0053] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0054] In embodiments of this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal planes at the top and bottom surfaces of the continuous structure. Layers may extend horizontally, vertically, and / or along inclined surfaces.

[0055] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0056] For ease of description, in this embodiment and hereinafter, the first direction and the second direction are represented as two directions that are parallel to and orthogonal to the substrate surface; the third direction is represented as a direction perpendicular to the substrate surface. In practical applications, the first direction can be represented as the X direction in the figures; the second direction can be represented as the Y direction in the figures; and the third direction can be represented as the Z direction in the figures.

[0057] The packaging structure provided in this application embodiment is applicable to 2.5D heterogeneous packaging. For 2.5D packaging design, it is necessary to introduce the design of an intermediary layer during the packaging design process.

[0058] Figure 1 This is a schematic diagram of a packaging structure provided in an embodiment of this application; as shown. Figure 1 As shown, the first semiconductor chip 3 and the second semiconductor chip 4, which are manufactured using different processes, are connected in the interposer layer 2 via conductive lines 21 through solder bumps 5. At the same time, the first semiconductor chip 3 is also connected to the solder bumps 5 through through silicon vias (TSVs; also referred to as conductive pillars below) 23, thereby entering the substrate 1.

[0059] Understandable Figure 1The connection methods between different semiconductor chips and between semiconductor chips and the substrate are relatively fixed. In other words, once the package structure is manufactured, the connection relationships between different semiconductor chips and between semiconductor chips and the substrate cannot be changed or adjusted. This packaging structure has several disadvantages: 1. When interconnecting multiple semiconductor chips using different processes, if the design changes, the interposers all need to be redesigned; 2. The designed interposers cannot be reused in other design schemes; 3. If connection errors in the interposers are found during the testing process after semiconductor chip packaging, the interposers need to be redesigned and the wafer fabrication process needs to be repeated. These disadvantages may lead to extended delivery times and increased manufacturing costs for the final package structure.

[0060] Based on at least one of the problems existing in the above embodiments, this application provides another packaging structure.

[0061] Figure 2 A schematic diagram of another packaging structure provided in the embodiments of this application; as shown Figure 2 As shown in the embodiment of this application, another packaging structure includes:

[0062] substrate 10;

[0063] An intermediate layer 20 is disposed on the substrate via solder bumps 50; the intermediate layer includes a connection structure.

[0064] The first semiconductor chip 30 and the second semiconductor chip 40 are disposed on the interposer layer by solder bumps 50;

[0065] At least one controllable switching device is disposed in the intermediate layer; wherein...

[0066] The same solder bump 50 of the first semiconductor chip is connected to any solder bump 50 of different solder bumps of the second semiconductor chip or the interposer layer through the controllable switching device and the connection structure.

[0067] or,

[0068] Any of the different solder bumps 50 of the first semiconductor chip is connected to the same solder bump 50 of the second semiconductor chip or the interposer layer through the controllable switching device and the connection structure.

[0069] Substrate 10 can be configured as a substrate for the package structure, and substrate 10 may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, and a wiring board. In practical applications, substrate 10 may include a copper-clad laminate and a wiring layer on the surface of the copper-clad laminate. The wiring layer on the surface of the substrate near the interposer 20 ( Figure 2(Not shown in the image) is interconnected with the intermediate layer 20 via solder bumps 50.

[0070] In some embodiments, solder bumps of the substrate are provided on the surface of the substrate away from the interposer layer 20. Figure 2 (Not shown in the image), the solder bumps on the substrate are used to connect the pins in the package structure that are to be connected to external devices to the external devices.

[0071] The solder bumps 50 include solder bumps of the first semiconductor chip, solder bumps of the second semiconductor chip, solder bumps of the interposer layer, and solder bumps of the substrate; the material of the solder bumps 50 may include at least one or more of the following metals in alloy with carbon (C): copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and zinc (Zn).

[0072] Understandably, considering the magnitude of the current, the size of the solder bumps on the substrate can be larger than the size of the solder bumps on the interposer; the size of the solder bumps on the interposer can be larger than the size of the solder bumps on the first semiconductor chip or the second semiconductor chip.

[0073] Here, the interposer 20 is disposed on the substrate 10 via solder bumps; the interposer 10 includes a connection structure. The connection structure can be used to connect a first semiconductor chip to a second semiconductor chip, connect the first semiconductor chip to the substrate, or connect the second semiconductor chip to the substrate.

[0074] In some embodiments, the connection structure includes controllable switching devices 221, 222, 227, and 228, conductive lines 201-204 and 211-212, and conductive posts 233.

[0075] In practical applications, the interposer 20 may have: one or more insulating layers ( Figure 2 (not shown) and one or more wiring layers respectively disposed on one or more insulating layers. Figure 2(Not shown in the image); and one or more through-silicon vias (TSVs) that penetrate each of one or more insulating layers and electrically connect one or more wiring layers to solder bumps on a substrate or to solder bumps on a first semiconductor chip and a second semiconductor chip, or electrically connect wiring layers disposed at different levels to each other. It is understood that the multiple TSVs and multiple wiring layers constitute the basic carrier components for the electrical connection of the interposer, directly forming the connection structure; wherein the controllable switching device is arranged in the wiring layer lines, and the conductive lines are arranged as lines electrically connecting the multiple TSVs and multiple wiring layers to each other, the TSVs being used to electrically connect the multiple wiring layers to each other. It should be noted that the TSVs may be referred to as conductive posts in the following text.

[0076] The wiring layer may include metallic materials or alloys thereof containing the following metals: copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). The wiring layer can perform various functions according to the design.

[0077] Through-silicon vias (TSVs) can include metallic materials or alloys thereof comprising the following metals: copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). TSVs can be configured such that a metallic material fills the via or that a conformal TSV is formed along the inner wall of the via.

[0078] The insulating layer material includes, but is not limited to, at least one of thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or inorganic fillers and / or glass fibers (glass cloth or glass fabric).

[0079] In some embodiments, the controllable switching device 221, 222, 227, or 228 includes a transistor. Specifically, the controllable switching device includes at least one of a gate-turn-off thyristor (GTO), a giant transistor (GTR), a metal MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), and an insulated-gate bipolar transistor (IGBT).

[0080] In some embodiments, the intermediary layer 20 includes a wiring layer or a plurality of stacked wiring layers;

[0081] The controllable switching device includes multiple controllable switching devices 221, 222, 227, or 228, which are disposed in the same wiring layer (not shown) or different wiring layers (not shown) of the intermediate layer 20.

[0082] In some embodiments, such as Figure 2 As shown, a first semiconductor chip 30 and a second semiconductor chip 40 are disposed on the interposer layer 20 via solder bumps 50; at least one controllable switching device 221, 222, 227, or 228 is disposed in the interposer layer 20; wherein,

[0083] The same solder bump 501 of the first semiconductor chip is connected to any solder bump 502 or 503 of the different solder bumps of the second semiconductor chip through the controllable switching device 221 or 222 and the connection structure (e.g., conductive lines 201-204); and any solder bump 510 or 511 of the different solder bumps of the first semiconductor chip is connected to the same solder bump 512 of the interposer layer through the controllable switching device 227 or 228 and the connection structure (e.g., conductive lines 211-212).

[0084] In some embodiments, the first semiconductor chip includes a control chip, which is electrically connected to the controllable switching device and is used to control the controllable switching device to be in a connected or disconnected state. In practical applications, the first semiconductor chip may include a control chip (e.g., a central processing unit (CPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC)).

[0085] In some embodiments, the second semiconductor chip includes a memory chip, such as volatile memory (e.g., Dynamic Random Access Memory (DRAM)) or non-volatile memory (e.g., NAND flash memory).

[0086] In some embodiments, the first semiconductor chip and the second semiconductor chip may comprise semiconductor chips of different types. Alternatively, the first semiconductor chip and the second semiconductor chip may comprise semiconductor chips of the same type. For example, both the first semiconductor chip and the second semiconductor chip may comprise a central processing unit. Of course, the package structure may also include multiple other semiconductor chips in this case.

[0087] The following will combine Figures 3a to 3d The specific method described herein is to connect a solder bump of one device to any one of the multiple solder bumps of other devices, or to connect any one of the multiple solder bumps of one device to a solder bump of other devices, through the controllable switching device.

[0088] In some embodiments, the interposer layer 20 includes: conductive lines 201-204; wherein,

[0089] like Figure 3a As shown, the same solder bump 501 of the first semiconductor chip 30 is connected to any solder bump 502 or 503 of different solder bumps of the second semiconductor chip 40 through a controllable switch device 221 (or 222) and the conductive lines 201 to 204.

[0090] or,

[0091] like Figure 3b As shown, any one of the multiple solder bumps 504 or 505 of the first semiconductor chip 30 is connected to the same solder bump 506 of the second semiconductor chip 40 through controllable switching devices 223-224 and conductive lines 205-208.

[0092] In some embodiments, the controllable switching device is disposed between two physically connected conductive lines. Specifically, such as Figure 3a In this configuration, the controllable switching device 221 is disposed between two physically connected conductive lines 201 and 202. For example... Figure 3b In this configuration, the controllable switching device 223 is disposed between two physically connected conductive lines 205 and 206.

[0093] In some embodiments, such as Figure 3aAs shown, the first solder bump 501 of the first semiconductor chip is connected to the first solder bump 502 of the second semiconductor chip via a first conductive line 201, a first controllable switch device 221, and a second conductive line 202. The first solder bump 501 of the first semiconductor chip is connected to the second solder bump 503 of the second semiconductor chip via a third conductive line 203, a second controllable switch device 222, and a fourth conductive line 204. The connection or disconnection of the first controllable switch device 221 and the second controllable switch device 222 can be controlled to connect the first solder bump 501 of the first semiconductor chip to either the first solder bump 502 or the second solder bump 503 of the second semiconductor chip.

[0094] Or, such as Figure 3b As shown, the second solder bump 504 of the first semiconductor chip is connected to the third solder bump 506 of the second semiconductor chip via a fifth conductive line 205, a third controllable switch device 223, and a sixth conductive line 206. The third solder bump 504 of the first semiconductor chip is connected to the third solder bump 506 of the second semiconductor chip via a seventh conductive line 207, a fourth controllable switch device 224, and an eighth conductive line 208. The connection or disconnection of the third controllable switch device 223 and the fourth controllable switch device 224 can be controlled to connect either the second solder bump 504 or the third solder bump 505 of the first semiconductor chip to the third solder bump 506 of the second semiconductor chip.

[0095] In practical applications, the above-mentioned "or" relationship can actually be either "and" or "or," meaning that the same solder bump of the first semiconductor chip is connected to any one of the different solder bumps of the second semiconductor chip; and / or, any one of the multiple solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip. Specifically, the packaging structure provided in the embodiments of this application can exist as follows: Figure 3a The connection relationship between the first semiconductor chip and the second semiconductor chip is shown; and / or, as shown in the diagram. Figure 3b The diagram illustrates the connection relationship between the first semiconductor chip and the second semiconductor chip. Furthermore, the same solder bump on the first semiconductor chip can be connected to all solder bumps on different solder bumps of the second semiconductor chip; all solder bumps on multiple solder bumps of the first semiconductor chip can be connected to the same solder bump on the second semiconductor chip.

[0096] In the above embodiments of this application, the intermediary layer includes a controllable switching device and conductive lines. The controllable switching device can be configured on each of the conductive lines, and each conductive line with the controllable switching device (hereinafter referred to as a "connection relationship") can be understood as a connection relationship that electrically connects the solder bumps of the first semiconductor chip and the second semiconductor chip. Furthermore, the controllable switching device can control the connection relationship between the first semiconductor chip and the second semiconductor chip to be in a connected state or a disconnected state.

[0097] Since there are multiple optional connection relationships between the solder bumps of the first semiconductor chip and the second semiconductor chip, the controllable switching device can be controlled to be in a connected or disconnected state, selectively connecting or disconnecting the multiple connection relationships between the solder bumps of the first semiconductor chip and the second semiconductor chip. The multiple optional connection relationships mentioned here can be understood as the variable and adjustable part of the interposer layer.

[0098] In some embodiments, the interposer layer includes: conductive wires and conductive posts; wherein,

[0099] like Figure 3c As shown, any of the different solder bumps 510 or 511 of the first semiconductor chip is connected to the same solder bump 512 of the interposer layer through the controllable switches 227-228, conductive lines 211-212 and conductive posts 233.

[0100] or,

[0101] like Figure 3d As shown, the same solder bump 507 of the first semiconductor chip is connected to any solder bump 508 or 509 of different solder bumps in the interposer layer through the controllable switching devices 225-226, conductive lines 209-210 and conductive posts 231-232.

[0102] In some embodiments, the controllable switching device is disposed between the solder bumps and conductive lines of two physically connected first semiconductor chips. Specifically, as shown... Figure 3c In this configuration, the controllable switching device 227 is disposed between the solder bumps 510 and the conductive lines 211 of the two physically connected first semiconductor chips. For example... Figure 3d In this configuration, the controllable switching device 225 is disposed between the solder bumps 507 and the conductive lines 209 of the two physically connected first semiconductor chips.

[0103] In some embodiments, such as Figure 3dAs shown, the fourth solder bump 507 of the first semiconductor chip is connected to the first solder bump 508 of the interposer layer via a fifth controllable switch device 225, a ninth conductive line 209, and a first conductive post 231. The fourth solder bump 507 of the first semiconductor chip is connected to the second solder bump 509 of the interposer layer via a sixth controllable switch device 226, a tenth conductive line 210, and a second conductive post 232. The fourth solder bump 507 of the first semiconductor chip is connected to either the first solder bump 508 or the second solder bump 509 of the interposer layer by controlling the connection or disconnection states of the fifth controllable switch device 225 and the sixth controllable switch device 226.

[0104] Or, such as Figure 3c As shown, the fifth solder bump 510 of the first semiconductor chip is connected to the third solder bump 512 of the interposer layer via the seventh controllable switch device 227, the eleventh conductive line 211, and the third conductive post 233. The sixth solder bump 511 of the first semiconductor chip is connected to the third solder bump 512 of the interposer layer via the eighth controllable switch device 228, the twelfth conductive line 212, and the third conductive post 233. The fifth solder bump 510 or the sixth solder bump 511 of the first semiconductor chip is connected to the third solder bump 512 of the interposer layer by controlling the connection or disconnection state of the seventh controllable switch device 227 and the eighth controllable switch device 228.

[0105] In practical applications, the above-mentioned "or" relationship can actually be either "and" or "or," meaning that the same solder bump of the first semiconductor chip is connected to any one of the different solder bumps of the interposer layer; and / or, any one of the multiple solder bumps of the first semiconductor chip is connected to the same solder bump of the interposer layer. Specifically, the packaging structure provided in the embodiments of this application can exist as follows: Figure 3d The connection relationship between the first semiconductor chip and the interposer layer is shown; and / or, as shown in the figure. Figure 3c The connection relationship between the first semiconductor chip and the interposer layer is shown.

[0106] In some embodiments, the conductive post can be fixed in the interposer layer, and the connection relationship between the conductive post and the solder bumps of the interposer layer can remain unchanged. Specifically, as shown... Figure 3c and Figure 3d As shown, the solder bumps 50 of the interposer layer disposed between the substrate 10 and the interposer layer 20 can be electrically connected to the conductive pillars 231, 232, and 233 by providing a wiring layer; and is not limited to such... Figure 3c and Figure 3d The diagram illustrates the correspondence between the conductive pillars and the solder bumps in the interposer layer. It is understood that, for example...Figure 3d In the middle, the conductive post 232 can be electrically connected to the welding bump 508 of the intermediate layer by setting the wiring layer.

[0107] In the above embodiments of this application, the intermediary layer includes a controllable switching device, conductive lines, and conductive pillars. The controllable switching device can be configured on each of the conductive lines, and each conductive line with the controllable switching device (hereinafter referred to as a "connection relationship") can be understood as a connection relationship that electrically connects the first semiconductor chip to the conductive pillars of the intermediary layer. Furthermore, the controllable switching device can control the connection relationship to be in a connected or disconnected state.

[0108] Since there are multiple optional connection relationships between the first semiconductor chip and the conductive pillars of the interposer layer, the controllable switching device can be controlled to be in a connected or disconnected state, selectively connecting or disconnecting the multiple connection relationships between the first semiconductor chip and the conductive pillars of the interposer layer. The multiple optional connection relationships mentioned here can be understood as the variable and adjustable part of the interposer layer.

[0109] The packaging structure provided in this application allows for changes and adjustments to the connection relationships between different semiconductor chips and between the semiconductor chips and the substrate after the packaging structure is manufactured, resulting in the following positive effects: 1. When multiple semiconductor chips with different processes are interconnected, if the design changes, only the connection or disconnection state of one or more of the controllable switching devices needs to be modified to adapt to the required connection relationship changes; 2. The fixed connection relationships in the designed interposer layer can be reused in other design schemes; 3. If connection errors in the interposer layer are found during the testing process after semiconductor chip packaging, only the adjustable connection relationships in the interposer layer need to be modified, without the need to redesign the entire interposer layer.

[0110] It should be noted that the connection relationship between the solder bumps of the first semiconductor chip and the solder bumps of the second semiconductor chip, as well as the connection relationship between the solder bumps of the first semiconductor chip and the solder bumps of the interposer layer, is not limited to... Figure 2 , Figures 3a to 3d The connection method is shown in the diagram. Specifically, as shown in the diagram... Figure 2 The packaging structure shown can be understood as follows: Figure 3a and Figure 3c A combination of the two schemes; the packaging structure provided in the embodiments of this application can also be understood as... Figure 3a and Figure 3d The combination of the two schemes Figure 3b and Figure 3c The combination of the two schemes (described below) and Figure 3band Figure 3d A combination of the two solutions. Those skilled in the art can implement this application in various forms and should not be construed as... Figure 2 , Figures 3a to 3d The implementation methods described in the relevant section are limited.

[0111] Figure 4 This is a schematic planar layout diagram of a controllable switching device in a packaging structure provided in an embodiment of this application. It should be noted that the planar layout of the controllable switching device is a projection view; wherein, the controllable switching device 22 can be in a connected state or a disconnected state (e.g., ...). Figure 4 The controllable switching device 22a is shown in the connected state and the controllable switching device 22b is shown in the disconnected state.

[0112] Specifically, referring to the foregoing description, it can be understood that multiple controllable switching devices are disposed within the same wiring layer or different wiring layers of the intermediate layer; furthermore, as Figure 4 As shown, a projection diagram of multiple controllable switching devices 22 can be projected onto a plane (i.e., the XY plane) parallel to the substrate surface along a direction perpendicular to the substrate surface (i.e., the third direction). Each of the multiple controllable switching devices 22 has a certain distance S between itself and its adjacent controllable switching devices in the projection plane.

[0113] In some embodiments, the controllable switching device 22 includes a plurality of devices, and the spacing S between two adjacent controllable switching devices in the plurality of controllable switching devices 22 is 50 μm to 5000 μm.

[0114] The packaging structure provided in this application supports adjustable interconnection relationships between devices, making it flexible in application and able to improve the problems of long process cycles and high repetitive manufacturing costs caused by incorrect interconnection design in the semiconductor chip manufacturing process.

[0115] The packaging structure provided in this application embodiment can also be applied to three-dimensional heterogeneous packaging. Based on this, as... Figures 5a to 5b As shown in the embodiments of this application, some packaging structures are also provided, including:

[0116] Substrate 100; the surface of the substrate is provided with a wiring layer 101 and a plurality of bonding pads 102;

[0117] One or more first semiconductor chips 300 are disposed on the substrate 100; the surface of the first semiconductor chip 300 is provided with a wiring layer 301 and a plurality of bonding pads 302.

[0118] Bonding wires 201 to 205 are disposed between the bonding pads 102 of the substrate and the bonding pads 302 of the first semiconductor chip, for connecting one bonding pad 102 of the substrate and one bonding pad 302 of the first semiconductor chip.

[0119] At least one controllable switching device 201-224 is disposed in the wiring layer 301 of the substrate or the first semiconductor chip; wherein,

[0120] like Figure 5a As shown, the same bonding pad 302 of the first semiconductor chip is connected to any one of the different bonding pads 102 of the substrate through the controllable switching device 223 or 224 and the bonding lines 201 to 205.

[0121] or,

[0122] like Figure 5b As shown, any bonding pad 302 of the different bonding pads of the first semiconductor chip is connected to the same bonding pad 102 of the substrate through the controllable switching device 221 or 222 and the bonding wire.

[0123] In some embodiments, the controllable switching device 221, 222, 223, or 224 includes a transistor. Specifically, the controllable switching device includes at least one of a gate-turn-off thyristor (GTO), a giant transistor (GTR), a metal MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), and an insulated-gate bipolar transistor (IGBT).

[0124] In some embodiments, the first semiconductor chip includes a control chip, which is electrically connected to the controllable switching device and is used to control the controllable switching device to be in a connected or disconnected state. In practical applications, the first semiconductor chip may include a control chip (e.g., a central processing unit (CPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), a microcontroller unit (MCU), or an application-specific integrated circuit (ASIC)).

[0125] In some embodiments, the first semiconductor chip includes a memory chip, such as volatile memory (e.g., Dynamic Random Access Memory (DRAM)) or non-volatile memory (e.g., NAND flash memory).

[0126] For some packaging structures not disclosed in detail in the embodiments of this application, please refer to another packaging structure and some other packaging structures provided in the above embodiments for understanding. Here, they will not be described in detail again.

[0127] It should be understood that the phrases "an embodiment" or "some embodiments" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0128] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A package structure, characterized by, Comprising: a substrate; an interposer disposed on the substrate by solder bumps; the interposer comprising a connection structure therein; a first semiconductor chip and a second semiconductor chip disposed on the interposer by solder bumps; at least one controllable switching device disposed in the interposer; wherein, the same solder bump of the first semiconductor chip is connected to either of a different solder bump of the second semiconductor chip or the interposer through the controllable switching device and the connection structure; or, any of different solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip or the interposer through the controllable switching device and the connection structure; wherein the interposer comprises: a conductive line and a conductive pillar; wherein, any of different solder bumps of the first semiconductor chip is connected to the same solder bump of the interposer through the controllable switching device, the conductive line and the conductive pillar; or, the same solder bump of the first semiconductor chip is connected to either of different solder bumps of the interposer through the controllable switching device, the conductive line and the conductive pillar; wherein the controllable switching device for connecting the solder bump of the first semiconductor chip and the solder bump of the interposer is disposed between the solder bump of the first semiconductor chip and the conductive line which are physically connected; wherein the fourth solder bump of the first semiconductor chip is connected to the first solder bump of the interposer through the fifth controllable switching device, the ninth conductive line and the first conductive pillar, and the fourth solder bump of the first semiconductor chip is connected to the second solder bump of the interposer through the sixth controllable switching device, the tenth conductive line and the second conductive pillar; wherein by controlling the connection state or the open state of the fifth controllable switching device and the sixth controllable switching device, the fourth solder bump of the first semiconductor chip is connected to the first solder bump or the second solder bump of the interposer; or, the fifth solder bump of the first semiconductor chip is connected to the third solder bump of the interposer through the seventh controllable switching device, the eleventh conductive line and the third conductive pillar, and the sixth solder bump of the first semiconductor chip is connected to the third solder bump of the interposer through the eighth controllable switching device, the twelfth conductive line and the third conductive pillar; wherein by controlling the connection state or the open state of the seventh controllable switching device and the eighth controllable switching device, the fifth solder bump or the sixth solder bump of the first semiconductor chip is connected to the third solder bump of the interposer.

2. The package structure of claim 1, wherein, the interposer comprises: a conductive line; wherein, the same solder bump of the first semiconductor chip is connected to either of different solder bumps of the second semiconductor chip through the controllable switching device and the conductive line; or, any of multiple solder bumps of the first semiconductor chip is connected to the same solder bump of the second semiconductor chip through the controllable switching device and the conductive line.

3. The package structure of claim 2, wherein, The controllable switching device for connecting the solder bump of the first semiconductor chip and the solder bump of the second semiconductor chip is arranged between two physically connected conductive lines.

4. The package structure of claim 3, wherein, The first solder bump of the first semiconductor chip is connected with the first solder bump of the second semiconductor chip through a first conductive line, a first controllable switching device and a second conductive line, and the first solder bump of the first semiconductor chip is connected with the second solder bump of the second semiconductor chip through a third conductive line, a second controllable switching device and a fourth conductive line; wherein, by controlling the connection state or the disconnection state of the first controllable switching device and the second controllable switching device, the first solder bump of the first semiconductor chip is connected with the first solder bump or the second solder bump of the second semiconductor chip. Or, The second solder bump of the first semiconductor chip is connected with the third solder bump of the second semiconductor chip through a fifth conductive line, a third controllable switching device and a sixth conductive line, and the third solder bump of the first semiconductor chip is connected with the third solder bump of the second semiconductor chip through a seventh conductive line, a fourth controllable switching device and an eighth conductive line; wherein, by controlling the connection state or the disconnection state of the third controllable switching device and the fourth controllable switching device, the second solder bump or the third solder bump of the first semiconductor chip is connected with the third solder bump of the second semiconductor chip.

5. The package structure of claim 1, wherein, The first semiconductor chip comprises a control chip, and the first semiconductor chip is electrically connected with the controllable switching device, for controlling the controllable switching device to be in the connection state or the disconnection state.

6. The package structure of claim 1, wherein, The controllable switching device comprises a transistor.

7. The package structure of claim 1, wherein, The interposer comprises one wiring layer or a plurality of stacked wiring layers. The controllable switching device comprises a plurality of controllable switching devices, and the plurality of controllable switching devices are arranged in the same wiring layer or different wiring layers of the interposer.

8. The package structure of claim 1, wherein, The controllable switching device comprises a plurality of controllable switching devices, and the distance between two adjacent controllable switching devices in the plurality of controllable switching devices is 50 μm to 5000 μm.

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