Superconducting quantum bit and preparation method thereof, quantum storage device and quantum computer

Abstract

The present invention discloses a superconducting qubit, a method for preparing the same, a quantum storage device, and a quantum computer. The superconducting qubit comprises a Josephson junction and a non-Josephson junction portion, wherein the non-Josephson junction portion comprises a zero-layer superconducting material layer. The zero-layer superconducting material layer is a superconducting material deposited on the non-Josephson junction portion before ion milling the Josephson junction and non-Josephson junction portions during the preparation of the superconducting qubit carrier. The present invention addresses the technical problem in related art where, in superconducting qubit preparation methods, the use of ion milling to treat the substrate surface results in significant dielectric loss, which reduces the lifespan of the superconducting qubit.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing, and in particular to a superconducting quantum bit and a preparation method thereof, a quantum storage device and a quantum computer. Background Art

[0002] Reducing the loss of superconducting qubits is one of the keys to achieving reliable superconducting quantum computing. During the fabrication of superconducting qubits, the key component, the Josephson junction, requires in-situ surface treatment of the substrate using ion milling to improve the performance and controllability of the Josephson junction. However, ion milling can damage the substrate surface of other components of the superconducting qubit, such as the capacitor electrodes.

[0003] Under the existing preparation method of superconducting quantum bits, the ion milling process is used to treat the substrate surface, which will result in considerable dielectric loss and reduce the lifespan of the superconducting quantum bits.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] Embodiments of the present invention provide a superconducting quantum bit and a method for preparing the same, a quantum storage device, and a quantum computer, to at least address the technical problem in related technologies that, in the method for preparing superconducting quantum bits, an ion milling process is used to treat the substrate surface, resulting in considerable dielectric loss and reducing the lifespan of the superconducting quantum bits.

[0006] According to one aspect of an embodiment of the present invention, a superconducting quantum bit is provided, comprising: a Josephson junction and a non-Josephson junction portion, wherein the non-Josephson junction portion comprises: a 0th layer of superconducting material, wherein the 0th layer of superconducting material is a superconducting material deposited on the non-Josephson junction portion before ion milling of the Josephson junction and the non-Josephson junction portion when preparing the superconducting quantum bit carrier.

[0007] Optionally, the superconducting material of the 0th superconducting material layer includes at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0008] Optionally, the Josephson junction includes: a Josephson junction first layer electrode deposited from a first layer of superconducting material after ion milling of the Josephson junction and non-Josephson junction parts, a Josephson junction insulating layer, and a Josephson junction second layer electrode deposited from a second layer of superconducting material.

[0009] Optionally, the first layer of superconducting material and the second layer of superconducting material each include at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0010] Optionally, the Josephson junction insulating layer includes at least one of the following: an oxide produced by oxidation, a PVD coating formed by physical vapor deposition (PVD), a CVD coating synthesized by chemical vapor deposition (CVD), and an ALD deposited film formed by atomic layer deposition (ALD).

[0011] According to another aspect of an embodiment of the present invention, a method for preparing a superconducting quantum bit is also provided, comprising: preparing a mask structure, wherein the mask structure is used to determine a Josephson junction and a non-Josephson junction portion; depositing a zero-layer superconducting material layer in the non-Josephson junction portion; performing ion milling on the Josephson junction and the non-Josephson junction portion; preparing a Josephson junction first-layer electrode, a Josephson junction insulating layer, and a Josephson junction second-layer electrode; and removing the mask structure to obtain the superconducting quantum bit.

[0012] Optionally, the material of the mask structure includes at least one of the following: optical photoresist, electron beam lithography (EBL) photoresist, and inorganic material.

[0013] Optionally, depositing the 0th layer of superconducting material in the non-Josephson junction part includes: in the xyz coordinate space where the superconducting quantum bit is located, at a first angle to the x-axis and a second angle to the z-axis in the xy plane, depositing the 0th layer of superconducting material, so that the Josephson junction is blocked by the mask shadow effect and no superconducting material is deposited, while superconducting material is deposited in the non-Josephson junction part.

[0014] Optionally, preparing the first layer electrode of the Josephson junction includes: depositing a first layer of superconducting material in an xy plane parallel to the x axis and at a third angle to the z axis to prepare the first layer electrode of the Josephson junction.

[0015] Optionally, the Josephson junction insulating layer is prepared by at least one of the following methods: preparing the Josephson junction insulating layer by generating oxide through an oxidation reaction; preparing the Josephson junction insulating layer by forming a PVD coating through physical vapor deposition (PVD); preparing the Josephson junction insulating layer by synthesizing a CVD coating through chemical vapor deposition (CVD); preparing the Josephson junction insulating layer by forming an ALD deposited film through atomic layer deposition (ALD).

[0016] Optionally, preparing the second layer electrode of the Josephson junction includes: depositing a second layer of superconducting material in the xy plane, parallel to the y axis and at a fourth angle to the z axis, to prepare the second layer electrode of the Josephson junction.

[0017] Optionally, the superconducting materials used in the 0th superconducting material layer, the 1st electrode layer and the 2nd electrode layer all include at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0018] According to one aspect of an embodiment of the present invention, a quantum storage is provided, comprising: using superconducting qubits to store quantum computing information, wherein the superconducting qubits are prepared using any of the superconducting qubit preparation methods described above.

[0019] According to another aspect of an embodiment of the present invention, a quantum computer is provided, comprising: a quantum storage device and a quantum effector device, wherein both the quantum storage device and the quantum effector device perform quantum manipulation through the quantum state constituted by the superconducting quantum bit described in any one of the above items.

[0020] According to another aspect of the embodiments of the present invention, a quantum computer is provided, comprising: a quantum transistor, a quantum storage, and a quantum effector, wherein the quantum transistor is used to realize the switching function of the transistor, the quantum storage is used to store quantum computing information, and the quantum effector is used to control quantum algorithms and quantum coding, wherein the quantum transistor, the quantum storage, and the quantum effector all perform quantum manipulation through the quantum state composed of a superconducting quantum bit, wherein the superconducting quantum bit comprises: a Josephson junction and a non-Josephson junction portion, wherein the non-Josephson junction portion comprises: a 0th layer of superconducting material layer, wherein the 0th layer of superconducting material layer is a superconducting material deposited on the non-Josephson junction portion before ion milling of the Josephson junction and the non-Josephson junction portion when preparing the superconducting quantum bit carrier.

[0021] In an embodiment of the present invention, a superconducting material is deposited on the non-Josephson junction portion before ion milling the Josephson junction and the non-Josephson junction portion, and a zero-layer superconducting material layer is prepared on the non-Josephson junction portion, thereby achieving the purpose of protecting the substrate surface of the non-Josephson junction portion, thereby avoiding damage to the substrate surface of the non-Josephson junction portion, reducing the dielectric loss of the substrate surface of the non-Josephson junction portion, and achieving the technical effect of improving the lifespan of the superconducting quantum bit. This solves the technical problem in the related art that, under the method for preparing superconducting quantum bits, considerable dielectric loss will occur when the substrate surface is treated by ion milling process, resulting in a reduction in the lifespan of the superconducting quantum bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 1 is a schematic structural diagram of a superconducting quantum bit provided according to an embodiment of the present invention;

[0024] Figure 2 is a flow chart of a method for preparing a superconducting quantum bit according to an embodiment of the present invention;

[0025] Figure 3a Schematic diagram of steps a and b in a method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention;

[0026] Figure 3b Schematic diagram of steps c and d in the method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention;

[0027] Figure 3c Schematic diagram of steps e and f in the method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention;

[0028] Figure 4 Schematic diagram of the structure of a quantum computer provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0032] Mask: In semiconductor manufacturing, many chip process steps use photolithography technology. The graphic "negative" used in these steps is called a mask (also called "mask"). Its function is to cover an opaque graphic template in a selected area on the silicon wafer, and then the following corrosion or diffusion will only affect the area outside the selected area.

[0033] Image masking is similar to it, using selected images, graphics or objects to block the processed image (all or part) to control the image processing area or processing process.

[0034] Photoresist: An organic compound that changes its solubility in a developer solution when exposed to ultraviolet light. The photoresist used in silicon wafer manufacturing is applied to the surface of the silicon wafer as a liquid and then dried into a film.

[0035] Ion milling: Ion milling is a technique for milling solid surfaces using an ion beam. For example, ion beam bombardment can be used to thin materials or clean surfaces at the micro- or nanoscale. The advantages of ion milling are very high surface accuracy and minimal surface damage.

[0036] PR: photoresist optical photoresist.

[0037] Lift off: A pattern transfer method used in micro-nano processing.

[0038] Al: Aluminum.

[0039] EBL:e-beam lithography electron beam lithography.

[0040] Ta: Tantalum.

[0041] Nb: Niobium.

[0042] TiN: Titanium nitride.

[0043] Example 1

[0044] According to an embodiment of the present invention, a superconducting quantum bit is further provided. Figure 1 Schematic diagram of the structure of a superconducting quantum bit according to an embodiment of the present invention. Figure 1 As shown, the superconducting quantum bit 10 includes: a Josephson junction 12 and a non-Josephson junction portion 14, wherein the non-Josephson junction portion 14 includes: a 0th layer of superconducting material layer (the bottom of the shaded portion in the figure), wherein the 0th layer of superconducting material layer is a superconducting material deposited on the non-Josephson junction portion before ion milling of the Josephson junction and the non-Josephson junction portion when preparing the superconducting quantum bit carrier.

[0045] In an embodiment of the present invention, a superconducting material is deposited on the non-Josephson junction portion before ion milling the Josephson junction and the non-Josephson junction portion. By preparing a zero-layer superconducting material layer on the non-Josephson junction portion, the purpose of protecting the substrate surface of the non-Josephson junction portion is achieved, thereby avoiding damage to the substrate surface of the non-Josephson junction portion, reducing the dielectric loss of the substrate surface of the non-Josephson junction portion, and achieving the technical effect of improving the lifespan of the superconducting quantum bit. This solves the technical problem in the related art that, under the preparation method of the superconducting quantum bit, the ion milling process is used to treat the substrate surface, resulting in considerable dielectric loss, which leads to a reduction in the lifespan of the superconducting quantum bit.

[0046] As an optional embodiment, the superconducting material of the zeroth superconducting material layer may include multiple materials, for example, at least one of the following: aluminum, tantalum, niobium, and titanium nitride. It should be noted that the above-listed superconducting materials are not exhaustive, and other superconducting materials that can be used by those skilled in the art based on their knowledge in the art to avoid damaging the non-Josephson junction portion of the substrate surface also belong to this application.

[0047] As an optional embodiment, the Josephson junction includes: a first-layer Josephson junction electrode deposited from a first layer of superconducting material after ion milling of the Josephson junction and non-Josephson junction portions, a Josephson junction insulating layer, and a second-layer Josephson junction electrode deposited from a second layer of superconducting material. Therefore, after preparing a mask structure and depositing superconducting material on the non-Josephson junction portion, ion milling is performed on the Josephson junction and non-Josephson junction portions. The Josephson junction substrate surface is cleaned because it is not protected by the superconducting material, while the non-Josephson junction portion is protected by the zeroth layer of superconducting material. Thus, the non-Josephson junction substrate surface is protected, thereby effectively avoiding damage to the non-Josephson junction substrate surface and reducing dielectric loss on the non-Josephson junction substrate surface.

[0048] As an optional embodiment, the thickness of the zero-layer superconducting material layer prepared in the non-Josephson junction portion can be different. For example, according to design requirements, by adjusting the thickness of the zero-layer superconducting material protective layer, the non-Josephson junction portion of the substrate surface can be partially ion milled during the time it takes for ion milling to etch away the zero-layer protective layer, thereby applying controllable, varying degrees of ion milling intensity to different areas. Alternatively, by depositing the zero-layer superconducting material in steps at different angles, the thickness of the zero-layer superconducting material protective layer can be greater at locations where components are present in the non-Josephson junction portion, and less at locations where components are not present in the non-Josephson junction portion.

[0049] As an optional embodiment, the first layer of superconducting material and the second layer of superconducting material may be similar to the superconducting material of the zeroth layer of superconducting material, that is, both may include at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0050] As an optional embodiment, the Josephson junction insulating layer can also be obtained by various methods, for example, it can include at least one of the following: an oxide produced by oxidation, a PVD coating formed by physical vapor deposition (PVD), a CVD coating synthesized by chemical vapor deposition (CVD), and an atomic layer deposition (ALD) film formed by atomic layer deposition (ALD). It should be noted that the above-listed methods are not exhaustive, and other materials that can achieve the function of the Josephson junction insulating layer can be used as part of this application.

[0051] Figure 2 is a flow chart of a method for preparing a superconducting quantum bit according to an embodiment of the present invention, such as Figure 2 As shown, the process includes the following steps:

[0052] Step S202, preparing a mask structure, wherein the mask structure is used to determine the Josephson junction and the non-Josephson junction part;

[0053] Step S204, depositing a zeroth superconducting material layer in the non-Josephson junction portion;

[0054] Step S206, performing ion milling on the Josephson junction and the non-Josephson junction portion, wherein the substrate surface of the Josephson junction is cleaned because it is not protected by the superconducting material, and the non-Josephson junction portion is protected by the zeroth layer of superconducting material;

[0055] Step S208, preparing a Josephson junction first layer electrode, a Josephson junction insulating layer and a Josephson junction second layer electrode;

[0056] Step S210: remove the mask structure to obtain a superconducting quantum bit.

[0057] In an embodiment of the present invention, a method of depositing a superconducting material on the non-Josephson junction portion before ion milling the Josephson junction and the non-Josephson junction portion is adopted, that is, preparing a zero-layer superconducting material layer on the non-Josephson junction portion, thereby achieving the purpose of protecting the substrate surface of the non-Josephson junction portion, thereby avoiding damage to the substrate surface of the non-Josephson junction portion, reducing the dielectric loss of the substrate surface of the non-Josephson junction portion, and achieving the technical effect of improving the lifespan of the superconducting quantum bit, thereby solving the technical problem in the related art that, under the preparation method of the superconducting quantum bit, the ion milling process is used to treat the substrate surface, resulting in considerable dielectric loss, which leads to a reduction in the lifespan of the superconducting quantum bit.

[0058] As an optional embodiment, when ion milling is performed on the Josephson junction and non-Josephson junction portions, controllable and varying degrees of ion milling intensity can be applied to different regions during the ion milling process on the non-Josephson junction portion. That is, the thickness of the zero-layer superconducting material layer prepared in the non-Josephson junction portion can be different. For example, according to design requirements, by adjusting the thickness of the zero-layer superconducting material protective layer, ion milling can be performed on a portion of the non-Josephson junction portion of the substrate surface during the time it takes for the ion milling process to etch away the zero-layer protective layer, thereby achieving controllable and varying degrees of ion milling intensity applied to different regions. Alternatively, by depositing the zero-layer superconducting material in stages at different angles, the thickness of the zero-layer superconducting material protective layer can be greater at locations where components are present in the non-Josephson junction portion, and less at locations where components are not present in the non-Josephson junction portion. Alternatively, if the thickness of the 0th superconducting material layer of the entire non-Josephson junction portion is the same, when the non-Josephson junction portion is ion milled, the ion milling intensity is smaller at the location where the components exist, and the ion milling intensity can be larger at the location where the components do not exist.

[0059] As an optional embodiment, the mask structure can be made of a variety of materials, for example, at least the following: optical photoresist, electron beam lithography (EBL) photoresist, and inorganic materials. The materials listed here for the mask structure are not exhaustive, and those skilled in the art can select other materials as needed.

[0060] As an optional embodiment, when depositing the zeroth layer of superconducting material in the non-Josephson junction portion, a variety of methods can be used. For example, the following method can be used: in the xyz coordinate space where the superconducting qubit is located, the zeroth layer of superconducting material is deposited at a first angle with the x-axis and a second angle with the z-axis in the xy plane. This causes the Josephson junction to be blocked by the mask shadow effect and no superconducting material is deposited, while superconducting material is deposited in the non-Josephson junction portion. Through the above process, based on the selection of the first and second angles, when depositing the zeroth layer of superconducting material, no superconducting material is deposited in the Josephson junction, while superconducting material is deposited in the non-Josephson junction portion. This allows the non-Josephson junction portion to be protected by the deposited superconducting material during subsequent ion milling, thereby avoiding dielectric loss in the non-Josephson junction portion.

[0061] As an optional embodiment, various methods can be used to prepare the first layer of the Josephson junction electrode. For example, the following method can be used: Similarly, in the xyz coordinate space where the superconducting qubit is located, the first layer of superconducting material is deposited parallel to the x-axis in the xy plane and at a third angle to the z-axis to prepare the first layer of the Josephson junction electrode. That is, by selecting the third angle described above, the first layer of superconducting material is deposited to prepare the first layer of the Josephson junction electrode.

[0062] As an optional embodiment, a Josephson junction insulating layer can be prepared in a variety of ways. For example, the Josephson junction insulating layer can be prepared by at least one of the following ways: preparing the Josephson junction insulating layer by generating oxides through an oxidation reaction; preparing the Josephson junction insulating layer by forming a PVD coating through physical vapor deposition (PVD); preparing the Josephson junction insulating layer by synthesizing a CVD coating through chemical vapor deposition (CVD); and preparing the Josephson junction insulating layer by forming an ALD deposited film through atomic layer deposition (ALD).

[0063] As an optional embodiment, when preparing the second layer electrode of the Josephson junction, similar to preparing the first layer electrode of the Josephson junction, multiple methods can be used. For example, the following method can be used to achieve this: depositing the second layer of superconducting material in the xy plane parallel to the y axis and at a fourth angle to the z axis to prepare the second layer electrode of the Josephson junction.

[0064] As an optional embodiment, the superconducting materials used in the 0th superconducting material layer, the 1st electrode layer and the 2nd electrode layer can be of various types, for example, can include at least one of the following: aluminum, tantalum, niobium, titanium nitride.

[0065] In one method of preparing superconducting quantum bits in the related art, ion milling is used before the deposition of the first layer of superconducting material (such as Al). The ion milling process does not have regional selectivity and will act indiscriminately on all structural areas that are not masked by PR after photolithography. It will cause significant damage to the substrate surface of the non-Josephson junction part. After the superconducting material layer is deposited on this damaged substrate surface, there will be considerable dielectric loss on this surface, which will reduce the lifetime of the superconducting quantum bit. Therefore, under the existing preparation method, the substrate surface of the non-Josephson junction part that has been treated with ion milling will bring about considerable dielectric loss, which will reduce the lifetime of the superconducting quantum bit.

[0066] Another process for preparing superconducting quantum bits first uses an additional pattern transfer process to prepare a large non-Josephson junction region, and then the Josephson junction part is prepared separately, which includes the ion milling process. This process route avoids the damage to the substrate surface of the non-Josephson junction region caused by ion milling, but the process complexity is significantly increased: a series of additional processes such as superconducting material layer deposition-photolithography-etching or etching-mask removal, or photolithography-superconducting material layer deposition-stripping are required, which increases the process steps and reduces the yield. At the same time, the separately prepared Josephson junction part needs to be well electrically connected to the previously prepared large non-Josephson junction part, which may cause potential contact resistance problems, or require more additional processes to solve.

[0067] In view of the above problems, in an optional embodiment of the present invention, a new low-loss superconducting quantum bit preparation method is proposed, which avoids the substrate surface in the non-Josephson junction area of the superconducting quantum bit from being damaged by the ion milling process, thereby effectively reducing the dielectric loss on the substrate surface in the non-Josephson junction area, which directly helps to improve the superconducting quantum ratio characteristics.

[0068] Figure 3a is a schematic diagram of steps a and b in a method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention. Figure 3b is a schematic diagram of steps c and d in the method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention, Figure 3c Schematic diagram of steps e and f in the method for preparing a low-loss superconducting quantum bit according to an embodiment of the present invention. Figure 3a ,3b,3c, the method includes the following processing:

[0069] a. Prepare the mask structure required for the lift-off process ( Figure 3aPR is used as an example in the example, defining the Josephson junction region (the thin cross intersection) and other large-area structures. It should be noted that in the embodiment of the present invention, the mask portion uses optical photoresist (PR) as an example; in actual implementation, it can also be implemented in other ways, such as EBL photoresist or inorganic materials.

[0070] b. Deposit the first layer of superconducting material at an angle of alpha (α) to the x-axis and 90-theta (90-θ) to the z-axis in the xy plane. Figure 3a Taking Al as an example, it is defined as the Al0 layer, where Figure 3a By selecting the angles α and θ, the Josephson junction region is blocked by the shadow effect of the mask and no superconducting material is deposited.

[0071] c. Perform ion milling on the Josephson junction and non-Josephson junction parts (i.e. the entire structure) Figure 3b In the figure, the ion milling process is performed using Ar ions as an example, with the downward arrow representing the Ar ion flux. The Josephson junction region has no superconducting material protection, and its substrate surface is cleaned ( Figure 3b The right-leaning oblique line portion represents the ion milling cleaned surface, wherein Figure 3b The remaining large-area structure is protected by the 0th layer of superconducting material, and its substrate surface is protected.

[0072] d. Deposit the first layer of superconducting material in the xy plane parallel to the x axis and at a 90-theta2 angle to the z axis ( Figure 3b Taking Al as an example, it is defined as Al1 layer, where Figure 3b In the figure, the non-Josephson junction part is represented by the horizontal line part added to the left-tilted oblique part (i.e., Al0 layer), that is, the left-tilted oblique part plus the horizontal line part is used to represent Al0+Al1. The Josephson junction part is represented by the horizontal line part added to the right-tilted oblique part (i.e., the surface cleaned by ion milling) (due to the angle of deposition, the Al1 layer is only present in the part parallel to x, so in Figure 3b Only the part parallel to x has the horizontal line)) to prepare the first layer of the Josephson junction electrode; then prepare the Josephson junction insulating layer ( Figure 3b Taking the oxide layer (abbreviated as OL in the figure) as an example, Figure 3b The dots are added after the Al1 layer is deposited in the Josephson junction. Figure 3bIn the right-slanting oblique line part, the part after the horizontal line covering the dot in the part parallel to x represents the Josephson junction insulating layer. Figure 3b The preparation of the Josephson junction insulating layer is exemplified by oxidation; in a specific implementation, it can also be achieved by other methods such as PVD, CVD, and ALD.

[0073] e. Deposit the second layer of superconducting material in the xy plane parallel to the y axis and at a 90-theta3 angle to the z axis ( Figure 3c Taking Al as an example, it is defined as Al2 layer, where Figure 3c In the figure, the non-Josephson junction part is represented by the left-tilted oblique part (i.e., Al0 layer) plus the horizontal part (i.e., Al1 layer) plus the vertical part, that is, the left-tilted oblique part plus the horizontal part plus the vertical part is used to represent Al0+Al1+Al2. The Josephson junction part is represented by the right-tilted oblique part (i.e., the surface cleaned by ion milling) plus the vertical part (due to the angle of deposition, the Al2 layer is only present in the part parallel to y, so in Figure 3c Only the part parallel to y has this vertical line)) to prepare the second layer electrode of the Josephson junction.

[0074] f. Remove the mask layer and release all structures by lift-off to complete the preparation of superconducting quantum bits.

[0075] It should be noted that the superconducting materials used in this embodiment can be various. In the embodiment of the present invention, Al is used as an example for description, but other superconducting materials such as Ta, Nb, TiN, etc. can also be used.

[0076] This optional embodiment utilizes triple superconducting material layer projection deposition. The zero-layer superconducting material protects the substrate surface in the large non-Josephson junction region before ion milling, preventing damage to the substrate surface during ion milling. This reduces dielectric losses during ion milling and improves the lifetime of the superconducting qubit. This eliminates the need for additional ex-situ process steps, maintaining process simplicity and improving yield.

[0077] Furthermore, using this optional embodiment eliminates the need for additional processing to prepare the non-Josephson junction region; all process steps are performed in situ. The number of patterning passes is minimized (one), maintaining process simplicity and improving yield. Furthermore, the Josephson junction and other structures are fabricated in an integrated manner, eliminating electrical contact issues.

[0078] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0079] Through the description of the above embodiments, those skilled in the art will clearly understand that the methods according to the above embodiments can be implemented by software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a terminal device to execute the methods of various embodiments of the present invention.

[0080] Example 2

[0081] According to an embodiment of the present invention, a quantum storage device is further provided, which uses superconducting quantum bits to store quantum computing information, wherein the superconducting quantum bits are prepared using the method for preparing superconducting quantum bits of the above-mentioned embodiment 1.

[0082] According to an embodiment of the present invention, a quantum computer is further provided, comprising: a quantum storage device and a quantum effector device, wherein both the quantum storage device and the quantum effector device perform quantum manipulation through the quantum state constituted by any of the above-mentioned superconducting quantum bits.

[0083] According to an embodiment of the present invention, a quantum computer is further provided. Figure 4 is a schematic diagram of the structure of a quantum computer provided according to an embodiment of the present invention, such as Figure 4 As shown, the quantum computer includes: a quantum transistor 42, a quantum storage 44 and a quantum effector 46, which communicate with each other, wherein the quantum transistor 42 is used to realize the switching function of the transistor, the quantum storage 44 is used to store quantum computing information, and the quantum effector 46 is used to control the quantum algorithm and quantum coding, wherein the quantum transistor, the quantum storage and the quantum effector all perform quantum manipulation through the quantum state composed of superconducting quantum bits, wherein the superconducting quantum bit includes: a Josephson junction and a non-Josephson junction part, wherein the non-Josephson junction part includes: a 0th layer of superconducting material layer, wherein the 0th layer of superconducting material layer is a superconducting material deposited on the non-Josephson junction part before ion milling of the Josephson junction and the non-Josephson junction part when preparing the superconducting quantum bit carrier.

[0084] Optionally, the superconducting material of the 0th superconducting material layer includes at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0085] Optionally, the Josephson junction includes: a Josephson junction first layer electrode deposited from a first layer of superconducting material after ion milling the Josephson junction and non-Josephson junction parts, a Josephson junction insulating layer, and a Josephson junction second layer electrode deposited from a second layer of superconducting material.

[0086] Optionally, the first layer of superconducting material and the second layer of superconducting material each include at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

[0087] Optionally, the Josephson junction insulating layer includes at least one of the following: an oxide produced by oxidation, a PVD coating formed by physical vapor deposition (PVD), a CVD coating synthesized by chemical vapor deposition (CVD), and an ALD deposited film formed by atomic layer deposition (ALD).

[0088] By adopting an optional embodiment of the present invention, a superconducting material is deposited on the non-Josephson junction part before ion milling the Josephson junction and the non-Josephson junction part, that is, a zero-layer superconducting material layer is prepared on the non-Josephson junction part, thereby achieving the purpose of protecting the substrate surface of the non-Josephson junction part, thereby avoiding damage to the substrate surface of the non-Josephson junction part, reducing the dielectric loss of the substrate surface of the non-Josephson junction part, and achieving the technical effect of improving the life of the superconducting quantum bit, thereby solving the technical problem in the related art that, under the preparation method of the superconducting quantum bit, the ion milling process is used to treat the substrate surface, resulting in considerable dielectric loss, which leads to a reduction in the life of the superconducting quantum bit.

[0089] It can be understood by those skilled in the art that Figure 4 The structure shown is for illustration only. Figure 4 The structure of the above electronic device is not limited. For example, a quantum computer may also include Figure 4 More or fewer components than shown, or with Figure 4 Different configurations shown.

[0090] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a quantum computer-readable storage medium.

[0091] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0092] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0094] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0095] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0096] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored on a quantum computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This quantum computer software product, stored on a storage medium, includes instructions for enabling a quantum computer device to execute all or part of the steps of the methods described in various embodiments of the present invention.

[0097] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A superconducting quantum bit, characterized in that: include: A Josephson junction and a non-Josephson junction portion, wherein the non-Josephson junction portion includes: a 0th layer of superconducting material layer, wherein the 0th layer of superconducting material layer is a superconducting material deposited on the non-Josephson junction portion before ion milling of the Josephson junction and the non-Josephson junction portion when preparing the superconducting quantum bit carrier, wherein the Josephson junction includes: a Josephson junction first layer electrode deposited from the first layer of superconducting material after ion milling of the Josephson junction and the non-Josephson junction portion, a Josephson junction insulating layer, and a Josephson junction second layer electrode deposited from the second layer of superconducting material.

2. The superconducting quantum bit according to claim 1, characterized in that The superconducting material of the 0th superconducting material layer includes at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

3. The superconducting quantum bit according to claim 1, wherein The first layer of superconducting material and the second layer of superconducting material each include at least one of the following: aluminum, tantalum, niobium, and titanium nitride.

4. The superconducting quantum bit according to claim 1, wherein The Josephson junction insulating layer includes at least one of the following: Oxides produced by oxidation, PVD coatings formed by physical vapor deposition (PVD), CVD coatings synthesized by chemical vapor deposition (CVD), and ALD deposited films formed by atomic layer deposition (ALD).

5. A method for preparing a superconducting quantum bit, characterized in that: include: preparing a mask structure, wherein the mask structure is used to determine a Josephson junction and a non-Josephson junction portion; Depositing a 0th superconducting material layer on the non-Josephson junction portion; performing ion milling on the Josephson junction and the non-Josephson junction portion; preparing a Josephson junction first layer electrode, a Josephson junction insulating layer and a Josephson junction second layer electrode; Removing the mask structure to obtain the superconducting quantum bit; The Josephson junction includes: a Josephson junction first layer electrode deposited from a first layer of superconducting material after ion milling of the Josephson junction and the non-Josephson junction portion, a Josephson junction insulating layer, and a Josephson junction second layer electrode deposited from a second layer of superconducting material.

6. The method according to claim 5, characterized in that The material of the mask structure includes at least the following: optical photoresist, electron beam lithography (EBL) photoresist, and inorganic material.

7. The method according to claim 5, characterized in that Depositing the zeroth superconducting material layer in the non-Josephson junction portion includes: In the xyz coordinate space where the superconducting quantum bit is located, the zero-layer superconducting material is deposited at a first angle to the x-axis and a second angle to the z-axis in the xy plane, so that the Josephson junction is blocked by the mask shadow effect and no superconducting material is deposited, while superconducting material is deposited in the non-Josephson junction portion.

8. The method according to claim 7, characterized in that The preparation of the first layer electrode of the Josephson junction comprises: The first layer of superconducting material is deposited in an xy plane parallel to the x axis and at a third angle to the z axis to prepare the first layer electrode of the Josephson junction.

9. The method according to claim 8, characterized in that The Josephson junction insulating layer is prepared by at least one of the following methods: preparing the Josephson junction insulating layer by generating oxides through an oxidation reaction; The Josephson junction insulating layer is prepared by forming a PVD coating through physical vapor deposition (PVD); The Josephson junction insulating layer is prepared by synthesizing a CVD coating through chemical vapor deposition (CVD); The Josephson junction insulating layer is prepared by forming an ALD deposited film through atomic layer deposition (ALD).

10. The method according to claim 9, characterized in that The preparation of the second layer electrode of the Josephson junction comprises: The second layer of superconducting material is deposited in the xy plane in parallel with the y axis and at a fourth angle to the z axis to prepare the second layer electrode of the Josephson junction.

11. The method according to claim 10, characterized in that The superconducting materials used in the 0th superconducting material layer, the 1st electrode layer and the 2nd electrode layer all include at least one of the following: aluminum, tantalum, niobium and titanium nitride.

12. A quantum storage device, characterized in that: include: Superconducting quantum bits are used to store quantum computing information, wherein the superconducting quantum bits are prepared using the method according to any one of claims 5 to 11.

13. A quantum computer, characterized in that: include: A quantum storage device and a quantum effector device, wherein both the quantum storage device and the quantum effector device are quantum manipulated by the quantum state constituted by the superconducting quantum bit according to any one of claims 1 to 4.

14. A quantum computer, characterized in that include: Quantum transistor, quantum storage and quantum effector, wherein the quantum transistor is used to realize the switching function of the transistor, the quantum storage is used to store quantum computing information, and the quantum effector is used to control quantum algorithms and quantum coding, wherein, The quantum transistor, the quantum storage and the quantum effector are all quantum manipulated through the quantum state composed of superconducting quantum bits, wherein: The superconducting quantum bit includes: a Josephson junction and a non-Josephson junction part, wherein the non-Josephson junction part includes: a 0th layer of superconducting material layer, wherein the 0th layer of superconducting material layer is a superconducting material deposited on the non-Josephson junction part before ion milling is performed on the Josephson junction and the non-Josephson junction part when preparing the superconducting quantum bit carrier, wherein the Josephson junction includes: a Josephson junction first layer electrode deposited from the first layer of superconducting material after ion milling is performed on the Josephson junction and the non-Josephson junction part, a Josephson junction insulating layer and a Josephson junction second layer electrode deposited from the second layer of superconducting material.

Images