Differential operational amplifier circuit and electronic device

Abstract

The embodiment of the application discloses a differential operational amplifier circuit and electronic equipment, the differential operational amplifier circuit comprises a differential amplifier and a common-mode feedback circuit, the common-mode feedback circuit comprises a biasing subcircuit, a first resistor and a second resistor; one end of the common-mode feedback circuit is connected with a power input end, and the other end of the common-mode feedback circuit is connected with a power output end; the biasing subcircuit comprises a first biasing tube and a second biasing tube, the input end of the differential amplifier is connected with a differential signal input end, the first output end of the differential amplifier is connected with the first biasing tube, and the first output end of the differential amplifier is connected with the first biasing tube through the first resistor, the second output end of the differential amplifier is connected with the second biasing tube, and the second output end of the differential amplifier is connected with the second biasing tube through the second resistor. The common-mode feedback is realized by detecting the resistance, on the basis of simplifying the circuit structure, fast response can be realized, and the differential operational amplifier circuit is suitable for various high-speed signal amplification scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a differential operational amplifier circuit and an electronic device. BACKGROUND

[0002] The full differential operational amplifier circuit is an integrated circuit which converts single-ended signal into differential signal or converts differential signal into differential signal, and has the characteristics of low noise, effective common-mode noise suppression and large voltage swing.

[0003] In the full differential operational amplifier circuit with high gain, the output common-mode level is easily affected by the characteristics and mismatch of the devices. In addition, the full differential operational amplifier circuit cannot stabilize the DC operating point by negative feedback of the differential signal. Usually, a common-mode feedback network is needed to detect the output common-mode level of the full differential operational amplifier circuit and adjust the bias current. However, the addition of the common-mode feedback network requires an additional control chip, which makes the integrated circuit structure design complex and cannot guarantee the stable output common-mode level. SUMMARY

[0004] Therefore, the present application aims to overcome the deficiencies in the prior art, and provides a differential operational amplifier circuit and an electronic device to solve the problem that the common-mode feedback network cannot output stable common-mode level.

[0005] In a first aspect, one embodiment of the present application provides a differential operational amplifier circuit, comprising a differential amplifier and a common-mode feedback circuit, wherein the common-mode feedback circuit comprises a bias sub-circuit, a first resistor and a second resistor;

[0006] One end of the common-mode feedback circuit is connected with a power supply input end, and the other end of the common-mode feedback circuit is connected with a power supply output end.

[0007] The bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with a differential signal input end, the first output end of the differential amplifier is connected with the first bias tube, and the first output end of the differential amplifier is connected with the first bias tube through the first resistor, the second output end of the differential amplifier is connected with the second bias tube, and the second output end of the differential amplifier is connected with the second bias tube through the second resistor, and the gate of the first bias tube is connected with the gate of the second bias tube.

[0008] The differential amplifier is used to output differential signal to the bias sub-circuit, the bias sub-circuit is used to set the output level, the first resistor is used to feed back the positive signal output by the differential amplifier to the bias sub-circuit, and the second resistor is used to feed back the negative signal output by the differential amplifier to the bias sub-circuit.

[0009] With reference to the first aspect, in a first possible implementation manner, the differential amplifier further comprises an enable switch, one end of the enable switch being connected to a power input end of the differential amplifier, and the other end of the enable switch being connected to one end of the common-mode feedback circuit.

[0010] The enable switch is configured to receive an external enable signal to control on-off of the common-mode feedback circuit.

[0011] With reference to the first aspect, in a second possible implementation manner, the differential amplifier comprises an NMOS differential input tube, a first output end of the NMOS differential input tube being connected to a drain of the first bias tube, and the first output end of the NMOS differential input tube further being connected to a gate of the first bias tube through the first resistor, a second output end of the NMOS differential input tube being connected to a drain of the second bias tube, and the second output end of the NMOS differential input tube further being connected to a gate of the second bias tube through the second resistor.

[0012] With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the common-mode feedback circuit further comprises a first switch and a second switch, the first output end of the NMOS differential input tube being connected to the first resistor through the first switch, the second output end of the NMOS differential input tube being connected to the second resistor through the second switch, and a gate of the first switch being connected to a gate of the second switch.

[0013] With reference to the first aspect, in a fourth possible implementation manner, the differential amplifier comprises a PMOS differential input tube, a first output end of the PMOS differential input tube being connected to a drain of the first bias tube, and the first output end of the PMOS differential input tube further being connected to a gate of the first bias tube through the first resistor, a second output end of the PMOS differential input tube being connected to a drain of the second bias tube, and the second output end of the PMOS differential input tube further being connected to a gate of the second bias tube through the second resistor.

[0014] With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, the common-mode feedback circuit further comprises a third switch and a fourth switch, the first output end of the PMOS differential input tube being connected to the first resistor through the third switch, and the second output end of the PMOS differential input tube being connected to the second resistor through the fourth switch.

[0015] In a sixth possible implementation manner of the fourth possible implementation manner of the first aspect, the common-mode feedback circuit further includes a fifth switch tube and a sixth switch tube, the first output end of the PMOS differential input tube is connected with the power input end through the fifth switch tube, and the second output end of the PMOS differential input tube is connected with the power input end through the sixth switch tube.

[0016] In a seventh possible implementation manner of the first aspect, the common-mode feedback circuit further includes a filter capacitor, and the gate of the first bias tube is connected with the power output end through the filter capacitor.

[0017] In an eighth possible implementation manner of the first aspect, the input end of the differential amplifier includes a first input end and a second input end, the first input end of the differential amplifier is connected with the positive signal input end of the differential signal input end, the second input end of the differential amplifier is connected with the negative signal input end of the differential signal input end, the first output end of the differential amplifier is connected with the drain of the first bias tube, the gate of the first bias tube is connected with the first resistor, the second output end of the differential amplifier is connected with the drain of the second bias tube, and the gate of the second bias tube is connected with the second resistor.

[0018] In a second aspect, an embodiment of the present application provides an electronic device, which includes a power input end, a power output end, a differential signal input end and a differential operational amplifier circuit as described in the first aspect, the power input end is connected with the power output end through the differential operational amplifier circuit, and the input end of the differential amplifier is connected with the differential signal input end.

[0019] The present application provides a differential operational amplifier circuit, which includes a differential amplifier and a common-mode feedback circuit, the common-mode feedback circuit includes a bias sub-circuit, a first resistor and a second resistor, one end of the common-mode feedback circuit is connected with a power input end, the other end of the common-mode feedback circuit is connected with a power output end, the bias sub-circuit includes a first bias tube and a second bias tube, the input end of the differential amplifier is connected with a differential signal input end, the first output end of the differential amplifier is connected with the first bias tube, and the first output end of the differential amplifier is connected with the first bias tube through the first resistor, the second output end of the differential amplifier is connected with the second bias tube, and the second output end of the differential amplifier is connected with the second bias tube through the second resistor. The common-mode feedback is realized by detecting the resistor, without configuring an additional control chip, so that the circuit structure is simplified, and an additional bias circuit is not needed, so that the circuit area is reduced. Meanwhile, the differential operational amplifier circuit of the present application can quickly respond, can be applied as an independent module, and is suitable for various high-speed signal amplification scenes. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the protection scope of the present application. In the various drawings, similar components are denoted by similar reference numerals.

[0021] Figure 1 A first structure schematic diagram of the differential operational amplifier circuit provided by the embodiments of the present application is shown;

[0022] Figure 2 A second structure schematic diagram of the differential operational amplifier circuit provided by the embodiments of the present application is shown;

[0023] Figure 3 A third structure schematic diagram of the differential operational amplifier circuit provided by the embodiments of the present application is shown;

[0024] Figure 4 A fourth structure schematic diagram of the differential operational amplifier circuit provided by the embodiments of the present application is shown;

[0025] Figure 5 A structure schematic diagram of the electronic device provided by the embodiments of the present application is shown.

[0026] Main component symbol explanation:

[0027] 100 - differential operational amplifier circuit, 200 - differential signal input end; 110 - common mode feedback circuit; 111 - biasing sub-circuit; VDD - power input end, VSS - power output end; OP - differential amplifier, POP - PMOS differential input tube, NOP - NMOS differential input tube, R1 - first resistor, R2 - second resistor, R3 - first protection resistor, R4 - second protection resistor, M1 - first biasing tube, M2 - second biasing tube, MEN - enabling switch tube, VDD-VDS - power input end through the enabling switch tube, M3 - first switch tube, M4 - second switch tube, M5 - third switch tube, M6 - fourth switch tube, M7 - fifth switch tube, M8 - sixth switch tube, C - filter capacitor; INP - first input end of the differential amplifier, INN - second input end of the differential amplifier, OUTN - first output end of the differential amplifier, OUTP - second output end of the differential amplifier, OUTN1 - first output end of the PMOS differential input tube, OUTP1 - second output end of the PMOS differential input tube, OUTN2 - first output end of the NMOS differential input tube, OUTP2 - second output end of the NMOS differential input tube. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application.

[0029] The components of the embodiments of the present application generally described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of the present application.

[0030] Hereinafter, the terms "include", "have", and their conjugates used in various embodiments of the present application are only intended to denote a certain characteristic, number, step, operation, element, component, or a combination thereof, and should not be construed as excluding the presence or addition of one or more other characteristics, numbers, steps, operations, elements, components, or combinations thereof.

[0031] In addition, the terms "first", "second", "third", and the like are used only to distinguish descriptions, and should not be understood as indicating or implying relative importance.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present application belong. The terms (such as terms defined in a generally used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized or overly formal meaning, unless clearly defined in various embodiments of the present application.

[0033] Please refer to Figure 1 , Figure 1 A first structure schematic diagram of a differential operational amplifier circuit provided by an embodiment of the present application is shown. Exemplarily, the differential operational amplifier circuit 100 of the present application includes a differential amplifier OP and a common-mode feedback circuit 110, the common-mode feedback circuit 110 including a biasing sub-circuit 111, a first resistor R1 and a second resistor R2;

[0034] One end of the common-mode feedback circuit 110 is connected with a power input terminal VDD, and the other end of the common-mode feedback circuit 110 is connected with a power output terminal VSS;

[0035] The biasing sub-circuit 111 comprises a first biasing tube M1 and a second biasing tube M2, the input end of the differential amplifier is connected with a differential signal input end, the first output end OUTN of the differential amplifier is connected with the first biasing tube M1, and the first output end OUTN of the differential amplifier is connected with the first biasing tube M1 through the first resistor R1, the second output end OUTP of the differential amplifier is connected with the second biasing tube M2, and the second output end OUTP of the differential amplifier is connected with the second biasing tube M2 through the second resistor R2, the gate of the first biasing tube M1 is connected with the gate of the second biasing tube M2;

[0036] The differential amplifier OP is used for outputting a differential signal to the biasing sub-circuit 111, the biasing sub-circuit 111 is used for setting an output level, the first resistor R1 is used for feeding back a positive signal output by the differential amplifier OP to the biasing sub-circuit 111, and the second resistor R2 is used for feeding back a negative signal output by the differential amplifier OP to the biasing sub-circuit 111.

[0037] The differential amplifier OP is used for amplifying the difference between two input voltages with a fixed gain to obtain a stronger output signal than the input signal. At the same time, the differential amplifier OP requires as wide a common-mode input voltage range as possible, and the signal at the output end of the differential amplifier OP is fed back to the biasing sub-circuit 111 through a resistor, and common-mode feedback is realized by detecting the resistor, without the need to configure an additional control chip, thereby simplifying the circuit structure. At the same time, the common-mode feedback circuit 110 can quickly respond, so that the differential amplifier circuit 100 of the present application can be applied to various high-speed signal amplification scenarios.

[0038] It should be understood that the first biasing tube M1 and the second biasing tube M2 can be any field effect transistor, which is not limited herein. For the purpose of understanding the present application, in the present embodiment, the first biasing tube M1 and the second biasing tube M2 are MOS (Metal-Oxide-Semiconductor Field-Effect) tubes. The signal at the output end of the differential amplifier OP is fed back to the gate end of the first biasing tube M1 and the second biasing tube M2 through a resistor, and when the input voltage changes, the voltage at the gate of the first biasing tube M1 and the second biasing tube M2 can be adjusted in time. The current of the first biasing tube M1 and the second biasing tube M2 changes with the output, and a stable output common-mode level is obtained.

[0039] The first output terminal OUTN of the differential amplifier is fed back to the gate of the first biasing tube M1 through the first resistor R1, and the second output terminal OUTP of the differential amplifier is fed back to the gate of the second biasing tube M2 through the second resistor R2, and the current of the first biasing tube M1 and the second biasing tube M2 varies with the output. The common-mode level output to the power output terminal VSS can be determined as:

[0040] V out = (V outp + V outn ) * 0.5

[0041] It should be understood that V out is the common-mode level output to the power output terminal VSS, V outn is the voltage value of the first resistor R1, and V outp is the voltage value of the second resistor R2. When the voltage of the first output terminal OUTN of the differential amplifier is greater than the voltage of the second output terminal OUTP of the differential amplifier, the voltage value of the second resistor R2 is greater than the voltage value of the first resistor R1, and at this time the output stable common-mode level is output. When the voltage of the first output terminal OUTN of the differential amplifier gradually decreases to equal the voltage of the second output terminal OUTP of the differential amplifier, the current of the first biasing tube M1 is increased and the current of the second biasing tube M2 is decreased, thereby ensuring the output stable common-mode level. Similarly, when the voltage of the first output terminal OUTN of the differential amplifier gradually decreases to be less than the voltage of the second output terminal OUTP of the differential amplifier, the current of the first biasing tube M1 is increased and the current of the second biasing tube M2 is decreased, thereby ensuring the output stable common-mode level.

[0042] Please refer to Figure 2 , Figure 2 Fig. 2 shows a second structural schematic diagram of the differential operational amplifier circuit provided by the embodiment of the present application. In an optional example, the differential operational amplifier circuit 100 further comprises an enabling switch tube MEN, one end of the enabling switch tube MEN is connected with the power input terminal of the differential amplifier OP, and the other end of the enabling switch tube MEN is connected with one end of the common-mode feedback circuit 110.

[0043] The enabling switch tube MEN is used for receiving an external enabling signal to control the on-off of the common-mode feedback circuit 110.

[0044] When the differential operational amplifier circuit 100 does not need to operate, the enabling switch tube MEN receives an external enabling signal to turn off the common-mode feedback circuit 110 in real time, thereby reducing the power consumption of the differential operational amplifier circuit 100. After the power input terminal VDD passes through the enabling switch tube, the voltage changes, thereby forming a power input terminal VDD-VDS passing through the enabling switch tube.

[0045] In an alternative example, the differential amplifier OP includes an NMOS differential input tube NOP, a first output end OUTN2 of the NMOS differential input tube is connected with the drain of the first bias tube M1, and the first output end OUTN2 of the NMOS differential input tube is also connected with the gate of the first bias tube M1 through the first resistor R1, a second output end OUTP2 of the NMOS differential input tube is connected with the drain of the second bias tube M2, and the second output end OUTP2 of the NMOS differential input tube is also connected with the gate of the second bias tube M2 through the second resistor R2.

[0046] In an actual application scenario, different input swing ranges are required. When the difference between the positive signal input end of the differential signal input end 200 and the negative signal input end of the differential signal input end 200 is greater than 0.5 times the voltage value of the voltage input end, it is determined that the input voltage is in a high voltage range, and the differential input pair composed of the NMOS differential input tube NOP functions as an operational amplifier.

[0047] In an alternative example, the common-mode feedback circuit 110 further includes a first switch tube M3 and a second switch tube M4, the first output end OUTN2 of the NMOS differential input tube is connected with the first resistor R1 through the first switch tube M3, the second output end OUTP2 of the NMOS differential input tube is connected with the second resistor R2 through the second switch tube M4, and the gate of the first switch tube M3 is connected with the gate of the second switch tube M4.

[0048] The static operating point is also called the bias point. When the AC input signal of the transistor is zero, the circuit is in a DC operating state, and the point determined by the current and voltage values through the characteristic curve is the static operating point. The static operating point is added to the first switch tube M3 to obtain a bias current, thereby avoiding the direct connection of the first resistor R1 to the first output end OUTN2 of the NMOS differential input tube. The static operating point is added to the second switch tube M4 to obtain a bias current, thereby avoiding the direct connection of the second resistor R2 to the second output end OUTP2 of the NMOS differential input tube.

[0049] It should be understood that in the present embodiment, the first switch tube M3 and the second switch tube M4 are both NMOS tubes, and the gate of the first switch tube M3 is connected with the gate of the second switch tube M4 to set the static operating point.

[0050] In an optional example, the differential amplifier OP includes a PMOS differential input tube POP, a first output end OUTN1 of the PMOS differential input tube is connected with the drain of the first bias tube M1, and the first output end OUTN1 of the PMOS differential input tube is also connected with the gate of the first bias tube M1 through the first resistor R1, a second output end OUTP1 of the PMOS differential input tube is connected with the drain of the second bias tube M2, and the second output end OUTP1 of the PMOS differential input tube is also connected with the gate of the second bias tube M2 through the second resistor R2.

[0051] When the difference between the input signal of the non-inverting signal input end of the differential signal input end 200 and the input signal of the negative signal input end of the differential signal input end 200 is less than or equal to 0.5 times of the voltage value of the voltage input end, it is determined that the input voltage is in the low voltage interval, and the differential input pair composed of the PMOS differential input tube POP functions as an operational amplifier.

[0052] In addition, when the input voltage has both high voltage and low voltage, the differential input composed of the PMOS differential input tube POP and the NMOS differential input tube NOP simultaneously functions as an operational amplifier, and when a full-swing input signal is input, the differential operational amplifier circuit 100 of the present application can work normally, thereby increasing the application scenarios.

[0053] Please refer to Figure 3 , Figure 3 A third structure diagram of the differential operational amplifier circuit provided by the embodiment of the present application is shown.

[0054] In an optional example, the common-mode feedback circuit 110 further includes a third switch tube M5 and a fourth switch tube M6, the first output end OUTN1 of the PMOS differential input tube is connected with the first resistor R1 through the third switch tube M5, and the second output end OUTP1 of the PMOS differential input tube is connected with the second resistor R2 through the fourth switch tube M6.

[0055] In the embodiment, the gates of the third switch tube M5 and the fourth switch tube M6 are connected with the first resistor R1, a bias current is formed, and then a suitable static working point is provided for the common-mode feedback circuit 110.

[0056] In an optional example, the common-mode feedback circuit 110 further includes a fifth switch tube M7 and a sixth switch tube M8, the first output end OUTN1 of the PMOS differential input tube is connected with the power input end VDD through the fifth switch tube M7, and the second output end OUTP1 of the PMOS differential input tube is connected with the power input end VDD through the sixth switch tube M8.

[0057] In the embodiment, the gates of the fifth switch tube M7 and the sixth switch tube M8 are connected with the power input terminal VDD, a bias current is formed, and then a suitable static working point is provided for the common mode feedback circuit 110. The switch tube provides an accurate static working point for the common mode feedback circuit 110, which not only makes the differential output of the differential operational amplifier circuit 100 accurate, but also does not need to set a circuit responsible for compensation through a control chip or other integrated circuits to respond quickly, so that the differential operational amplifier circuit 100 is simple in structure.

[0058] Please refer to Figure 4 , Figure 4 A fourth structural schematic diagram of the differential operational amplifier circuit provided by the embodiment of the application is shown. In order to facilitate the understanding of the application, in the embodiment, the gate of the first bias tube M1 is connected with the gate of the second bias tube M2, the gate of the first switch tube M3 is connected with the gate of the second switch tube M4, the gate of the third switch tube M5 is connected with the gate of the fourth switch tube M6, the gate of the fifth switch tube M7 is connected with the gate of the sixth switch tube M8, a bias current path is formed, and a static working point required by the differential operational amplifier circuit is provided.

[0059] The gate of the first switch tube M3 is connected with the gate of the first bias tube M1 through the first protection resistor R3, so as to avoid that the first switch tube M3 is directly connected with the first bias tube M1; the gate of the second switch tube M4 is connected with the gate of the second bias tube M2 through the second protection resistor R4, so as to avoid that the second switch tube M4 is directly connected with the second bias tube M2 and affect the formation of the current bias point.

[0060] In an optional example, the common mode feedback circuit 110 further includes a filter capacitor C, and the gate of the first bias tube M1 is configured to be connected with the power output terminal VSS through the filter capacitor C.

[0061] The filter capacitor C is configured to reduce the alternating current ripple coefficient, so as to obtain a smooth direct current output. Meanwhile, the filter capacitor C is configured to filter noise, so as to make the differential operational amplifier circuit 100 output a signal of a specific frequency.

[0062] In an optional example, the input terminal of the differential amplifier OP includes a first input terminal and a second input terminal, the first input terminal INP of the differential amplifier is configured to be connected with the positive-phase signal input terminal of the differential signal input terminal 200, the second input terminal INN of the differential amplifier is configured to be connected with the negative-phase signal input terminal of the differential signal input terminal 200, the first output terminal OUTN of the differential amplifier is connected with the drain of the first bias tube M1, the gate of the first bias tube M1 is connected with the first resistor R1, and the second output terminal OUTP of the differential amplifier is connected with the drain of the second bias tube M2, and the gate of the second bias tube M2 is connected with the second resistor R2.

[0063] The differential transmission is a signal transmission technique. Specifically, in the embodiment, the signal amplitudes of the first input end INP of the differential amplifier and the second input end INN of the differential amplifier are the same, and the phases are opposite. The signal difference between the first output end OUTN of the differential amplifier and the second output end OUTP of the differential amplifier is taken as an output signal, which can effectively reduce errors.

[0064] The application provides a differential operational amplifier circuit, which comprises a differential amplifier and a common-mode feedback circuit, the common-mode feedback circuit comprising a biasing sub-circuit, a first resistor and a second resistor; one end of the common-mode feedback circuit is connected with a power input end, and the other end of the common-mode feedback circuit is connected with a power output end; the biasing sub-circuit comprises a first biasing tube and a second biasing tube; an input end of the differential amplifier is connected with a differential signal input end; a first output end of the differential amplifier is connected with the first biasing tube, and the first output end of the differential amplifier is connected with the first biasing tube through the first resistor; a second output end of the differential amplifier is connected with the second biasing tube, and the second output end of the differential amplifier is connected with the second biasing tube through the second resistor. The common-mode feedback is realized by detecting the resistor, without the need of configuring an additional control chip, so that the circuit structure is simplified, and an additional biasing circuit is not needed, thereby reducing the circuit area. Meanwhile, the differential operational amplifier circuit can quickly respond and can be applied as an independent module, and is suitable for various high-speed signal amplification scenes.

[0065] Please refer to Figure 5 , Figure 5 The application provides a differential operational amplifier circuit, which comprises a differential amplifier and a common-mode feedback circuit, the common-mode feedback circuit comprising a biasing sub-circuit, a first resistor and a second resistor; one end of the common-mode feedback circuit is connected with a power input end, and the other end of the common-mode feedback circuit is connected with a power output end; the biasing sub-circuit comprises a first biasing tube and a second biasing tube; an input end of the differential amplifier is connected with a differential signal input end; a first output end of the differential amplifier is connected with the first biasing tube, and the first output end of the differential amplifier is connected with the first biasing tube through the first resistor; a second output end of the differential amplifier is connected with the second biasing tube, and the second output end of the differential amplifier is connected with the second biasing tube through the second resistor. The common-mode feedback is realized by detecting the resistor, without the need of configuring an additional control chip, so that the circuit structure is simplified, and an additional biasing circuit is not needed, thereby reducing the circuit area. Meanwhile, the differential operational amplifier circuit can quickly respond and can be applied as an independent module, and is suitable for various high-speed signal amplification scenes.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation manners, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0067] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0068] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or the part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0069] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A differential operational amplifier circuit, characterized in that, The differential operational amplifier circuit includes a differential amplifier and a common-mode feedback circuit, wherein the common-mode feedback circuit includes a bias sub-circuit, a first resistor, and a second resistor; One end of the common-mode feedback circuit is connected to the power input terminal, and the other end of the common-mode feedback circuit is connected to the power output terminal; The bias sub-circuit includes a first bias transistor and a second bias transistor. The input terminal of the differential amplifier is connected to the differential signal input terminal. The first output terminal of the differential amplifier is connected to the drain of the first bias transistor and is connected to the gate of the first bias transistor through the first resistor. The second output terminal of the differential amplifier is connected to the drain of the second bias transistor and is connected to the gate of the second bias transistor through the second resistor. The gate of the first bias transistor is connected to the gate of the second bias transistor. The differential amplifier is used to output a differential signal to the bias sub-circuit, the bias sub-circuit is used to set the output level, the first resistor is used to feed back the positive signal output by the differential amplifier to the bias sub-circuit, and the second resistor is used to feed back the negative signal output by the differential amplifier to the bias sub-circuit.

2. The differential operational amplifier circuit according to claim 1, characterized in that, It also includes an enable switch, one end of which is connected to the power input terminal of the differential amplifier, and the other end of which is connected to one end of the common-mode feedback circuit. The enable switch is used to receive an external enable signal to control the on / off state of the common-mode feedback circuit.

3. The differential operational amplifier circuit according to claim 1, characterized in that, The differential amplifier includes an NMOS differential input transistor. The first output terminal of the NMOS differential input transistor is connected to the drain of the first bias transistor, and the first output terminal of the NMOS differential input transistor is also connected to the gate of the first bias transistor through the first resistor. The second output terminal of the NMOS differential input transistor is connected to the drain of the second bias transistor, and the second output terminal of the NMOS differential input transistor is also connected to the gate of the second bias transistor through the second resistor.

4. The differential operational amplifier circuit according to claim 3, characterized in that, The common-mode feedback circuit further includes a first switch and a second switch. The first output terminal of the NMOS differential input transistor is connected to the first resistor through the first switch, and the second output terminal of the NMOS differential input transistor is connected to the second resistor through the second switch. The gate of the first switch is connected to the gate of the second switch.

5. The differential operational amplifier circuit according to claim 1, characterized in that, The differential amplifier includes a PMOS differential input transistor. The first output terminal of the PMOS differential input transistor is connected to the drain of the first bias transistor, and the first output terminal of the PMOS differential input transistor is also connected to the gate of the first bias transistor through the first resistor. The second output terminal of the PMOS differential input transistor is connected to the drain of the second bias transistor, and the second output terminal of the PMOS differential input transistor is also connected to the gate of the second bias transistor through the second resistor.

6. The differential operational amplifier circuit according to claim 5, characterized in that, The common-mode feedback circuit further includes a third switch and a fourth switch. The first output terminal of the PMOS differential input transistor is connected to the first resistor through the third switch, and the second output terminal of the PMOS differential input transistor is connected to the second resistor through the fourth switch.

7. The differential operational amplifier circuit according to claim 5, characterized in that, The common-mode feedback circuit further includes a fifth switch and a sixth switch. The first output terminal of the PMOS differential input transistor is connected to the power input terminal through the fifth switch, and the second output terminal of the PMOS differential input transistor is connected to the power input terminal through the sixth switch.

8. The differential operational amplifier circuit according to claim 1, characterized in that, The common-mode feedback circuit also includes a filter capacitor, and the gate of the first bias transistor is connected to the power output terminal through the filter capacitor.

9. The differential operational amplifier circuit according to claim 1, characterized in that, The differential amplifier has a first input terminal and a second input terminal. The first input terminal is connected to the non-inverting signal input terminal of the differential signal input terminal, and the second input terminal is connected to the negative-inverting signal input terminal of the differential signal input terminal. The first output terminal is connected to the drain of the first bias transistor, and the gate of the first bias transistor is connected to the first resistor. The second output terminal is connected to the drain of the second bias transistor, and the gate of the second bias transistor is connected to the second resistor.

10. An electronic device, characterized in that, It includes a power input terminal, a power output terminal, a differential signal input terminal, and a differential operational amplifier circuit as described in any one of claims 1 to 9, wherein the power input terminal is connected to the power output terminal through the differential operational amplifier circuit, and the input terminal of the differential amplifier is connected to the differential signal input terminal.

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