Scalable and programmable coherent waveform generator

Abstract

The present disclosure describes various aspects of a system with a scalable and programmable coherent waveform generator. A network and digital-to-analog conversion (DAC) cards used by the network are described, wherein each DAC card has a clock divider / replicator device having an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC component is used to control a beam of a separate qubit for a quantum information processing (QIP) system. The network also includes a first distribution network that provides a clock signal to the clock divider / replicator device in the DAC card, and a second distribution network that provides a start signal to the DAC card, wherein when the start signal is asserted, the digital logic component in the DAC card uses the start signal to assert the input SYNC pin unless the start signal is masked by the digital logic component.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 877,979, filed on July 24, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to waveform or signal generators and, more particularly, to scalable and programmable coherent waveform generators for quantum information processing (QIP) systems. Background Art

[0004] Trapped atoms (or atomic ions: atomic ions) are one of the main implementations of quantum information processing, and superconducting devices are another possible implementation. Atom-based qubits can be used as quantum memories, like quantum gates in quantum computers and simulators, and can act as nodes in quantum communication networks. By applying modulated beams to these atoms or atomic ions, these atoms or atomic ions are at least partially controlled during various operations in the QIP system, including the performance of quantum algorithms / computations and quantum simulations. These beams are in turn at least partially provided to the radio frequency (RF) signal control of the acousto-optic modulator (AOM) used to modulate the beam. It is important that the electronics driving the RF signals are well synchronized and have a strictly controlled phase relationship to ensure correct operation across multiple qubits in the system. When the number of trapped atoms or atomic ions available in the QIP system is scaled up (e.g., increased), the QIP system needs to be able to maintain the synchronization and phase relationship of the RF signals even if more electronics are needed to handle additional RF signals and beams for the additional number of trapped atoms or atomic ions.

[0005] Furthermore, these electronics need to operate in an efficient manner to ensure that the RF signal has the appropriate waveform to be applied to the trapped atoms or atomic ions by the beam. Since the waveform of the RF signal is typically generated by a digital-to-analog converter (DAC), it is desirable that these DACs be configured to be not only scalable, but also to operate in a manner that overcomes latency, such as that introduced by the waveform information being provided by a stream from a network host.

[0006] It would therefore be desirable to develop and implement techniques that enable scalability and programmability of coherent waveform or signal generators (eg, DDS) for use in different types of systems, including QIP systems. Summary of the invention

[0007] The following is a brief summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is not intended to identify key or critical elements of all aspects, nor to delineate the scope of any or all aspects. Its purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that is presented later.

[0008] The present invention discloses techniques related to the expansion and programming of waveform or signal generators (e.g., direct digital synthesizers (DDS)). More specifically, the present invention describes techniques related to the expansion and programming of waveform or signal generators for quantum information processing (QIP) systems.

[0009] In one aspect of the present invention, a network for synchronizing multiple digital-to-analog converter (DAC) cards in a QIP system is described. The network includes the multiple DAC cards, each of which has a clock divider / replicator having an input synchronization (SYNC) pin, a digital logic component, and one or more DAC components, wherein each output of the DAC component is used to control one or more beams of a separate qubit of the QIP system. The network also includes a first distribution network and a second distribution network, the first distribution network providing a clock signal to the clock divider / replicator in each of the multiple DAC cards, and the second distribution network providing a central start signal to each of the multiple DAC cards. For each of the multiple DAC cards, the digital logic component in the DAC card uses the central start signal to assert the input SYNC pin of the clock divider / replicator of the DAC card in response to the central start signal being asserted, unless the central start signal is shielded by the digital logic component.

[0010] In another aspect of the invention, a DAC card for controlling qubits in a QIP system is described. The DAC card may include a digital logic component having: one or more direct digital synthesizers (DDS) for each output of the DAC card, wherein each output controls one or more beams for a separate qubit of the QIP system; and a pair of tables for collectively providing commands to the one or more DDSs, the first table of the pair of tables being a function table, the second table of the pair of tables being an instruction table, the function table defining parameterized functions generated by the one or more DDSs, and the instruction table defining subroutine calls to the function table or conditional loop instructions for the function table. The DAC card may also include one or more DAC components, wherein each DAC component provides one or more outputs of the DAC card, and wherein each DAC component receives a parameterized function generated by the one or more DDSs to generate the one or more outputs, wherein the parameterized function is in digital form and the one or more outputs are in analog form.

[0011] Methods, apparatus, and computer-readable storage media are described herein to implement various aspects associated with techniques for expansion and programming of waveform or signal generators. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings depict only some embodiments and therefore should not be considered limiting in scope.

[0013] Figure 1A A diagram of a vacuum chamber housing electrodes for trapping atomic ions in a crystal is shown in accordance with aspects of the present invention.

[0014] Figure 1B is a diagram illustrating an example of a simplified energy level diagram for applying laser radiation (eg, a light beam) for state initialization according to aspects of the present invention.

[0015] Figure 1C is a diagram illustrating an example of a simplified energy level diagram for applying laser radiation (eg, a light beam) to qubit state detection by fluorescence in accordance with aspects of the present invention.

[0016] Figure 2A is a diagram showing an example of the geometry of a Raman beam according to aspects of the present invention.

[0017] Figure 2B is a diagram showing an energy level diagram of coherent stimulated Raman transitions coupled to qubit states according to aspects of the present invention.

[0018] Figure 3is a diagram showing an example of the frequency dependence of a diffracted laser light or beam using an acousto-optic modulator (AOM) according to aspects of the present invention.

[0019] Figure 4A An example of a digital-to-analog conversion (DAC) card according to aspects of the present invention is shown.

[0020] Figure 4B An example of implementing multiple direct digital synthesizers, instructions, and spline tables in a DAC card according to aspects of the present invention is shown.

[0021] Figure 4C An example of using multiple DAC cards to control the operation of trapped atomic ions used as qubits according to aspects of the present invention is shown.

[0022] Figure 5A An example of a start signal distribution network for multiple DAC cards according to aspects of the present invention is shown.

[0023] Figure 5B An example of a clock distribution network for multiple DAC cards according to aspects of the present invention is shown.

[0024] Figure 6 An example of combined operation of an instruction table and a function or spline table according to aspects of the present invention is shown.

[0025] Figure 7 is a diagram illustrating an example of a computer device according to aspects of the present invention.

[0026] Figure 8 is a block diagram illustrating an example of a QIP system according to aspects of the present invention. DETAILED DESCRIPTION

[0027] The detailed description set forth below in conjunction with the accompanying drawings is intended to describe various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known components are shown in block diagram form to avoid obscuring these concepts.

[0028] As described above, trapped atoms can be used to implement quantum information processing. Atom-based qubits can be used as different types of devices, including but not limited to quantum memories, quantum gates in quantum computers and simulators, and nodes for quantum communication networks. Qubits based on trapped atomic ions can have very good coherence, can be prepared and measured with an efficiency close to 100%, and can be easily entangled with each other by modulating their Coulomb interactions with a suitable external control field (such as a light field or a microwave field). As used in the present invention, the terms "atomic ions", "atoms" and "ions" can be used interchangeably to describe particles that are confined or actually trapped in a trap to form a crystal or a similar arrangement or configuration, and these particles are used as qubits in quantum computing and simulation. The present invention describes technologies that allow the scalability and programmability of coherent waveforms or signal generators (e.g., DDS) used in different types of systems (including QIP systems) based on atomic qubits.

[0029] The typical ion trap geometry or structure used for quantum information and metrology purposes is the linear radio frequency (RF) Paul trap (also called RF trap, surface trap or simply Paul trap), in which nearby electrodes maintain static and dynamic potentials, forming an effective inhomogeneous harmonic trapping of ions. An RF Paul trap is a trap that uses an electric field to capture or trap charged particles in a specific area, position or location. When atomic ions are laser-cooled to very low temperatures in such a trap, the atomic ions form a fixed crystal of qubits (e.g., a structured arrangement of qubits), and the Coulomb repulsion counteracts the external trapping forces. For sufficient trap anisotropy, the ions can form a crystal along the weakly trapped direction, and this is the arrangement typically used for applications in quantum information and metrology.

[0030] Figure 1A A diagram 100 is shown showing the trapping of atomic ions in a crystal 110 using, for example, a linear trap (by using electrodes within a vacuum chamber), such as a linear radio frequency Paul trap. The crystal 110 may be, for example, a linear crystal or a linear lattice. Figure 1A In the example shown, the vacuum chamber in the quantum system may include a vacuum chamber for trapping N (N ≥ 1) atomic ytterbium ions (e.g., 171 Yb + ions) 120, which are trapped in the crystal 110 and can be laser cooled to near rest. The number of trapped atomic ions can be configured. 171 Yb + The resonant laser radiation illuminates the atoms and images the fluorescence of the atomic ions onto a camera. In one example, the atomic ions can be separated from each other by about 5 micrometers (μm), which can be verified by fluorescence. The separation of the atomic ions is determined by the balance between external trapping forces and Coulomb repulsion.

[0031] Strong fluorescence from a single trapped atomic ion relies on efficient recycling of photons, so the atomic structure of the ion must have strong closed optical transitions that allow laser cooling motion, qubit state initialization, and efficient qubit readout. This rules out many atomic ion species, except for simple atomic ions with a single external electron, such as alkaline earth metals (Be + Mg + , Ca + , Sr + , Ba + ) and certain transition metals (Zn + , Hg + 、Cd + and Yb + ). In these atomic ions, a qubit can be represented by two stable electronic energy levels, typically characterized by having two states |↑> and |↓>, or equivalently, having effective spins |1> and |0>. Figure 1B and Figure 1C Atomic ions are shown separately 171 Yb + Simplified energy diagrams 125 and 155 of FIG. 125, where the qubit energy levels |↑> and |↓> 130 are represented by stable hyperfine levels in the ground state electronic state and by the frequency ω 0 / 2π=12.64GHz separation. 171 Yb + The excited electronic states |e> and |e′>140 are themselves split by a small hyperfine coupling and are separated from the ground state by an optical separation with an energy corresponding to a wavelength of light of 369.53 nm.

[0032] Laser radiation tuned to just below resonance in these optical transitions allows Doppler laser cooling to confine the atomic ions to near the bottom of the trap. Other more complex forms of laser cooling can keep the atomic ions nearly stationary in the trap.

[0033] When with Transition and When a two-color laser or light beam resonating on both sides of the transition (e.g., a beam with two tones resulting from sidebands caused by optical modulation) is applied to the atom, it rapidly enters the state |↓> and no longer interacts with the light field, allowing the qubit to be initialized with essentially 100% fidelity (e.g., see Figure 1B ).

[0034] When applied with When a single laser or beam is in resonance with the transition, the closed-loop optical transition causes the ions in the |↑> state to fluoresce strongly, while the ions in the |↓> state remain dark due to the laser frequency being far from their resonance (see, for example, Figure 1C ). Collection of even a small portion of this fluorescence allows detection of atomic qubit states with near-perfect efficiency or precision. Other atomic species may have similar initialization / detection schemes.

[0035] exist Figure 1B and Figure 1C In FIG. 1 , all allowed transitions from excited electronic states |e> and |e′> 140 are shown as downward wavy arrows. On the other hand, the applied laser radiation (which is shown as an upward straight arrow) drives these transitions for initialization to Figure 1B The state |↓> shown in FIG. 1 is used for fluorescence detection of the qubit state (|↑> = fluorescence, |↓> = no fluorescence), as shown in FIG. Figure 1C shown.

[0036] use Figures 1A to 1C Performing quantum processing requires the use of lasers or light beams to control the phase, frequency, amplitude and / or polarization of the quantum information in the qubit.

[0037] For entangled multi-qubit operations, the motion of many trapped ions is coupled via Coulomb interactions, much like an array of pendulums connected by springs. The natural way to implement entangled quantum logic gates between atomic ions in a crystal is to use motion as a medium, such as Figure 2A , which shows a diagram 200 illustrating an example of a Raman beam geometry, and in which application of the beam produces motion in a qubit. In diagram 200, there are beams 210 and 220 directed toward a linear lattice or crystal 110 having atomic ion qubits 120. Beams in the same direction may be referred to as co-propagating beams, and beams in opposite directions may be referred to as non-co-propagating beams or counter-propagating beams. Beam 210 (co-propagating) is a focused or individually addressed beam, while beam 220 (which counter-propagates relative to beam 210) is an unfocused global beam. As used herein, the terms laser beam, laser radiation, beam, optical radiation, beam, optical field, and field may be used interchangeably. In conjunction with Figures 1A to 1C and Figure 2, Figure 2B Diagram 230 in shows that the qubit levels are separated in energy and that there are different ways to achieve transitions in the qubit levels.

[0038] In order to manipulate or control the frequency, phase, amplitude and / or polarization of the above-mentioned light beams, an acousto-optic modulator (AOM) is used in quantum computing and simulation applications. One or more RF signals and a laser beam are applied to the AOM, and the RF signal is imprinted onto a portion of the laser beam. This portion is deflected ("diffracted") by the AOM from the unaffected beam and can be separated spatially.

[0039] Pairs of modulated beams typically need to be applied simultaneously to the same atoms to produce the desired quantum information manipulation. An AOM can generate multiple manipulated laser beams by applying the sum of two or more RF signals, each with a specific frequency (e.g., f 1 、f 2 However, if the two or more laser beams have different frequencies, the two modulated beams do not overlap after being diffracted by the AOM. The laser beams can be "refocused" (or reimaged) onto the atoms or ions so that the two beams overlap at the atoms.

[0040] Figure 3 A diagram 300 is shown showing an example of the frequency dependence of a diffracted laser or light beam as described above. In this example, the diffracted laser or light beam is generated by an RF generator 310a based on a frequency or tone f 1 A first RF signal (eg, a modulated signal) is generated and modulated by the RF generator 310b based on a frequency or tone f 2 The second RF signal is generated. The two signals are combined by adder 2315 and applied to AOM 320a. The RF control signals (first RF signal and second RF signal) are typically analog signals generated by an analog-to-digital converter (DAC) that converts a digital waveform into an analog waveform represented in the RF control signal.

[0041] The AOM 320a receives a portion of the undiffracted incident laser beam 325 (eg, the undiffracted laser beam 330 generated by the 0th order diffraction). On the other hand, two modulated laser beams (eg, for the tone f ) are generated from the incident laser beam 325 by diffraction at the AOM 320a. 1 The diffracted laser beam 335a and the color tone f 2 The two diffracted laser beams 335a and 335b are both produced by 1st order diffraction - higher order diffracted beams can be spatially filtered). The two diffracted laser beams are diffracted at different angles and do not co-propagate. Therefore, the two diffracted laser beams need to pass through an optical element 340 (e.g., for f 1 The focused laser beam 345a and the 2 The focused laser beam 345b) is focused onto corresponding ions or atoms 120 in a lattice or crystal 110 formed in an ion trap for quantum processing (see Figure 1A ). The refocused laser beam may not reach the ion or atom 120 in the same propagation direction (eg, no co-propagation), and techniques may be applied so that this does not cause errors in quantum state manipulation.

[0042] As quantum information processing systems are scaled up, i.e., as the number of atoms or ions 120 increases, it is important to be able to maintain synchronization and phase relationships among RF signals (e.g., RF control signals) among the various atoms or ions 120 so as to also maintain the synchronization and phase relationships when manipulating or controlling the frequency, phase, amplitude, and / or polarization of the above-mentioned light beams.

[0043] As above combined Figures 1A to 3 As described, a trapped ion quantum information processing system, such as a quantum computer, requires two (2) non-parallel Raman laser beams to strike each of the atoms or atomic ions 120 in a crystal or lattice 110, with a known and stable phase relationship with similar laser beams striking other atoms or atomic ions 120 in the same trap. As described above, when the atomic species used for the qubit is 171 Yb + When the laser beam can be 355 nm, and a global beam (e.g. Figure 2A The global beam 220 in diagram 200 is shared by all qubits.

[0044] By using an AOM, a laser or light beam can have the ability to be transformed from an electronic signal (e.g. Figure 3 The RF control signal in the diagram 300 in FIG. 3 is imprinted on the phase, thereby simplifying the phase control from the purely optical domain to mainly in the electronic domain. 171 Yb + In the case of qubits, a 355 nm (e.g., ultraviolet) light source can be used to generate the laser or light beam. In some cases, the light source can be a light source used for commercial semiconductor lithography and adapted or repurposed for trapped ion quantum information processing. The original laser or light beam generated by the light source can be split into a single global beam (e.g., Figure 2A 200) and multiple individual beams (e.g., Figure 2A 200 in the diagram 210) to address each atom or atomic ion 120 individually. Then, as Figure 3 As shown in diagram 300 in , these beams may be passed through one or more AOMs, where optics may be used to widen the global beam so that it may be expanded over all atoms or atomic ions 120, and to aim or focus the individual beams onto their respective atoms or atomic ions 120. In some examples, the crystal or lattice 110 may include up to 32 or more atoms or atomic ions 120 (e.g., up to 100 or even more atoms or atomic ions 120), and the number of beams required (and their respective electronic signals, such as RF control signals) will scale with the number of atoms or atomic ions 120. Figure 3The example shown in diagram 300 is one AOM for each beam, however, multi-channel AOMs may also be used, in which case a single optical device group may be sufficient to manipulate the beams generated by the multi-channel AOM. For example, in qubits involving 171 Yb + And using a typical AOM the required electronic signal will have a frequency between 150 MHz and 250 MHz.

[0045] As described above, it is important that the electronics used to generate the RF signal that drives the electrical input to the AOM (e.g., the signal generator of the RF control signal) have a tightly controlled phase relationship. They do not need to have a specific phase relative to each other (e.g., 16 degrees or 567 picoseconds), but the phase does need to be substantially fixed over the duration of a set of experiments or calculations so that the applied calibration does not change. In preferred operation, the calibration that occurs before the signal generator is finally powered off or reset will still be valid later when the same signal generator is powered back on or the reset is released.

[0046] One aspect of achieving tightly controlled phase relationships as described in the present disclosure is that when multiple signal generators are used to provide RF control signals to multiple AOMs (or to a multi-channel AOM), the signal generators are configured to derive their digital clocks from a common source so that their outputs can remain in phase over longer periods, since even good oscillators that start at the same frequency tend to drift different amounts over the same time period.

[0047] In another aspect of the present disclosure, during an experiment (e.g., a quantum computation or algorithm) or simulation performed by a quantum information processing system, it may be necessary to individually change the control crystal or lattice (e.g., see Figure 1A The signal generator may be a quantum computer or a quantum computer. The signal generator may be a computer program product that generates an electrical signal (e.g., a waveform) for each qubit in the crystal or lattice 110 in the diagram 100. The statements or instructions for a particular quantum algorithm or quantum simulation that dictates how the qubits interact and evolve need to be compiled into a specific set of commands for the signal generator to change the parameters accordingly.

[0048] In a trapped-ion quantum information processing system, there may be several different types of lasers or beams that are used and need to be controlled: (1) a pulsed laser that converts motion into information - for 171 Yb + qubits, which may involve ultraviolet (UV) light (e.g., 355 nm); (2) continuous wave (CW) lasers (Doppler cooling) for erasing or deleting information - for 171 Yb + qubits, which may involve 369nm+14GHz UV light); (3) CW lasers are171 Yb + qubit preparation qubit state, which may involve 369nm + 2.105GHz light; and (4) a CW laser for detecting the qubit state - for 171 Yb + qubits, which could involve 369nm light. In one example, a 369nm (or about 370nm) laser or light beam could be used Figure 2B In the transition shown in diagram 230 of 2 S 1 / 2 and 2 P 1 / 2 between.

[0049] Furthermore, in trapped-ion quantum information processing systems, the algorithm or simulation typically involves one or more of the following stages: (1) coarse Doppler cooling; (2) fine (sideband) cooling by alternating pulsed and CW lasers; (3) preparing all atoms or atomic ions (qubits) into known states; (4) entanglement of qubits for algorithms or simulations using pulsed lasers (this may involve multiple steps); and (5) state detection. In such an algorithm or simulation, the term "shot" may refer to running each of the above stages, the term "experiment" may refer to running a large number of shots, for example, somewhere between 100 and 10,000 shots, the term "pulse" may refer to the action of a signal generator during qubit entanglement in the algorithm or simulation to cause single-qubit or multi-qubit coherent operations, the term "pulse duration" may refer to the duration of a single-qubit operation of approximately 10 microseconds (μs) and the duration of a two-qubit operation of approximately 100 μs (possibly longer when more than two qubits are involved), and the term "entanglement" may refer to the fact that two or more qubits interact, and as long as only coherent operations are performed on the qubits, they will still be connected so that operations on one qubit affect another qubit.

[0050] During state detection (stage (5) above), an atom or atomic ion (qubit) that can be in any superposition of the |0> state and the |1> state collapses to a "0" or "1" (light or dark) classical state. The probability of detecting a "0" or "1" is controlled by the original quantum superposition, but since each emission provides only one sample per qubit, the experiment requires multiple emissions to obtain a statistical population large enough to estimate the original superposition with the required accuracy.

[0051] As described above, the signal generator is used to provide electrical signals (e.g., RF signals or RF control signals) that control lasers or light beams used in quantum operations (e.g., algorithms / computations or simulations). These electrical signals can be used to control the lasers or light beams using an AOM. The type of signal generator described in this disclosure can be used in conjunction with, for example, phases (2) and (4) (fine (sideband) cooling and entanglement) described above.

[0052] In some experiments, the behavior of the signal generator during the experiment (e.g., the waveform or signal to be generated / provided, or the parameters used to generate the waveform or signal) is known even before the experiment begins. In other types of experiments, it may be desirable for the behavior of the signal generator to change during the experiment based on feedback from the experiment itself. A quantum information processing system can be configured to handle either type of experiment.

[0053] Arbitrary waveform generators (AWGs) have been used as signal generators for quantum information processing systems. The AWG is typically configured to store each output of a corresponding digital-to-analog converter (DAC) over time, as long as the experiment is running. Since this can be a large amount of data, transferring the samples from the computer to the AWG can take a long time. This "upload time" can dominate the experimental time, whether the experiment can be repeated many times in succession, or whether each run of the experiment is short or limited. Therefore, systems that rely on AWGs may have limited operating speeds, especially when the information used to generate the samples provided to the AWG is streamed into the system from a host or network.

[0054] Different approaches have been proposed (see, for example, the Artiq project, https: / / m-labs.hk / artiq / ), where waveform or signal parameters are explicitly specified, rather than generating each sample of the waveform or signal to be used. That is, instead of specifying each analog voltage to be generated, a few parameters are specified to describe the signal or waveform over a period of time. The advantage is that less data is required to specify the parameters than the moment-to-moment analog voltage. When a parameter does not need to change for a given interval (for example, the frequency does not change when the amplitude is mainly changed), the parameter can be omitted from the description to save space, because the signal generator hardware knows how to run the frequency freely without external help.

[0055] Additionally, predictable changes in signal parameters (e.g., frequency increasing by N Hz per Tμs, or amplitude increasing by one thousandth of a full-scale amplitude per Tμs) can also be described succinctly so that the signal generator can do the right thing in the absence of new inputs for a period of time. These types of changes are unlikely to be sufficient to fully describe the desired behavior of the signal generator for a given time interval, and therefore additional parameters may need to be provided, but the advantage is that these additional parameters / changes do not need to be provided frequently, so less data needs to be pushed to the signal generator.

[0056] Typically, the changes indicated by a statement such as "change parameter P in N steps over time T" convey a linear equation to the signal generator. More complex equations with higher order terms (such as square and cubic) or higher order terms are also useful, depending on the shape that needs to be described in the waveform or signal. These methods of describing parameter changes are called or referred to as "splines". In the case of third order equations, they are called or referred to as "cubic splines".

[0057] An example of a type of hardware (e.g., a signal generator) that can be used to control a waveform or signal by indicating a signal parameter and / or a change in a signal parameter is a direct digital synthesis device, also known as a direct digital synthesizer or DDS. For example, a DDS can generate the requested frequency indefinitely. A DDS allows the frequency and / or phase to be specified at any time, and it changes the sampling that it can feed to the DAC very quickly to match the newly specified parameters. Amplitude may not be a parameter that a DDS inherently allows to change (because it can usually operate at full-scale amplitude), but by inserting a digital multiplication unit between the output of the DDS and the input of the DAC, amplitude parameter modulation can be easily processed outside the DDS. Internally, a DDS may include a lookup table (LUT) of a sine wave DAC sample and some mathematical capabilities to increase precision. Some examples of the mathematical capabilities of a DDS include, but are not limited to, Taylor series (expansion), linear interpolation, and low-pass filtering. Further details about DDS devices or typical operation of DDS are generally available (see, for example, https: / / www.analog.com / en / analog-dialogue / articles / all-about-direct-digital-synthesis.html, https: / / en.wikipedia.org / wiki / Direct_digital_synthesis).

[0058] DDS can be implemented as a stand-alone integrated circuit ("chip") or as an intellectual property (IP) block for insertion into an integrated circuit with other processing blocks, typically where the digital logic of the DDS feeds an internal or external DAC. Such IP blocks can be used in field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs) to implement, for example, system-on-chip (SOC) solutions. For example, the aforementioned Artiq project provides DDS soft IP for free. In addition, FPGA manufacturers such as Xilinx and Intel / Altera also sell DDS IP blocks, and chip manufacturer Analog Devices also has open source DDS IP blocks.

[0059] In some instances, it is desirable to run the digital logic of the FPGA (or ASIC) at a slower clock rate than the samples that will be output by the DAC. For example, a DAC channel may be capable of receiving 1 billion samples per second from the digital logic (e.g., DDS), but it may be desirable to implement and run the digital logic on the FPGA to run no faster than, for example, 250 MHz.

[0060] One approach could be to run parallel copies of the DDS at a slower clock rate. For example, instead of a single DDS, four instances of the DDS (or sub-DDS) could be implemented and used to generate 1 billion samples per second, but each DDS is actually clocked at 250MHz. The multiple sub-DDSs start with phase offsets of 0, 90, 180, and 270 degrees, and are all given the same frequency. They then each scan out a different 1 / 4 portion of the waveform, so that four (4) samples (1 from each sub-DDS) are fed to a DAC per clock, typically using some small portion of an FPGA or ASIC specifically designed to feed data off-chip at high rates, such as a serializer-deserializer (SERDES).

[0061] In this example, since there are four (4) instances of the DDS (e.g., four DDS IP blocks) that will use approximately four times the logic, random access memory (RAM), and clock resources within the FPGA or ASIC, it may be preferable to run fewer instances at a higher clock rate. Using the example of 1 billion DAC samples per second again, instead of using four sub-DDSs, it may be preferable to use three (3) instances at 333MHz or two (2) instances at 500MHz. The above approach will still be used, only with different phase offsets: (0, 120, 240) degrees for 3 instances; (0, 180) degrees for 2 instances. Note that when fewer gates use a clock domain, it can generally run faster than the entire chip. A dual clock first-in, first-out (FIFO) can be used to transfer data between a small fast clock domain and the majority of the chip running at a slower clock rate (perhaps 250MHz).

[0062] Another problem that may arise in the context of quantum information processing systems is that it may not be possible to find a single FPGA or ASIC that can drive enough DAC chips to generate enough signals to control e.g. Figure 1A 100 in the diagram. Or if one such FPGA is available, its cost may be prohibitive. In addition, the time or cost required to construct a board using such an FPGA may also be prohibitive. In all of these cases, it may be necessary to use many separate FPGAs, perhaps on separate boards, to control the total number of atoms or atomic ions (qubits) in the system. Since the system can be scalable (e.g., the number of qubits can be increased), having a modular or scalable approach can allow the system to be easily expanded. The outputs of all DACs on all boards need to be synchronized so that the relative phases of these outputs remain static, preferably during power-up and reset.

[0063] In view of the above problems, the present disclosure describes various aspects or techniques for synchronizing clocks across physically separated DAC cards for use in a QIP system to control a scalable number of qubits. In one such aspect, a central or common clock can be run through a passive splitter (e.g., a 1:N splitter) and distributed to each DAC card in the QIP system so that the DAC cards see the rising edge of the clock at the same time (see, e.g., Figure 5B ). A DAC card may also be referred to as a DAC board, and may include one or more DAC components (e.g., DAC integrated circuits or modules) that provide DAC outputs (e.g., analog electrical signals) that are used to control a laser or light beam to manipulate the qubits. One way to achieve having all DAC cards see the rising edge of the clock at the same time is by using coaxial cables that are all of the same length. In another such aspect, on the DAC card, the clock runs through a clock divider / replicator device so that the associated clock (e.g., a local clock on the DAC card) can reach both the DAC components and additional digital logic such as an FPGA or ASIC, where one or more DDSs may be implemented (see, e.g., Figure 4A and Figure 4B ). The clock divider / replicator device has an input SYNC pin that will hold all of its outputs at a known value and clear internal counters that may drive some of its outputs. In yet another such aspect, a central or common start signal is also distributed to all DAC cards in the QIP system. This start signal is used to drive the DAC components, and therefore the DAC cards are expected to receive the start signal at the same time. One way to distribute a start signal with good signal integrity and fast rise time is to use low voltage differential signaling (LVDS) on a shielded twinaxial cable (see, e.g., Figure 5A). The Samtec C28S cable is an example (see, e.g., https: / / www.samtec.com / rf / components / original / bayonet-twinax). In yet another such aspect, the SYNC input pin of the divider / replicator device can be driven from the output of digital logic (e.g., FPGA / ASIC) that is programmed to assert whenever the start signal is asserted (unless the start signal is masked) (see, e.g., Figure 4A ). In this case, the FPGA / ASIC can be the same as the one that implements DDS.

[0064] One of the reasons slower clocks are preferred in digital logic (such as an FPGA or ASIC) with DDS is that it is easier to get all of the many divider / replicator devices to clear on the same clock cycle (and therefore have zero phase between their outputs) after the input clock rate is reduced from 1GHz to 250MHz.

[0065] The above aspects and technologies regarding synchronous DAC cards and their outputs will be combined below FIG. 4A to FIG. 5B Describe in more detail.

[0066] Figure 4A Diagram 400a is shown showing an example of a DAC board or card 410 according to aspects of the present disclosure. A QIP system, or some other similar system in which a DAC card may be used to control individual operations, devices, or elements, may include one or more of DAC cards 410. Each output 480 of DAC card 410 is used to control a separate laser or beam used with a particular qubit in the QIP system. For example, each of outputs 480 may include one or more waveforms or signals, such as RF control signals applied to an AOM, as described above in Figure 3 300 in FIG. 4. In this example, DAC card 410 provides eight (8) outputs 480, so that the single DAC card 410 can be used to manipulate or control up to eight (8) qubits in the QIP system. For a larger number of qubits, additional DAC cards 410 can be added to the system.

[0067] Each DAC card 410 includes a divider / replicator device 420 with a SYNC input, a digital logic component 430, an interface logic 460, and one or more DAC components 470 (e.g., DAC-1, ..., DAC-n). Each of the DAC components 470 is configured to receive samples (i.e., digital voltages representing digital waveforms or signals) and convert the samples to analog voltages representing corresponding analog waveforms or signals (e.g., RF control signals). The digital waveforms or signals are generated by the digital logic component 430 based on parameterized functions and adapted by the interface logic component 460 to be compatible with the inputs of the DAC components 470.

[0068] The divider / replicator device 420 is configured to receive a clock signal 421, which may correspond to the central or common clock described above. The divider / replicator device 420 may be configured to divide the rate of the clock signal 421 (e.g., may operate as a clock divider) or simply replicate or maintain the rate of the clock signal 421 when generating a local clock signal 425. The local clock signal 425 is provided to the digital logic component 430, the interface logic 460, and / or the DAC component 470 for synchronous operation.

[0069] The digital logic component 430 can be configured to generate samples that are provided to the DAC component 470 through the interface logic component 460. The digital logic component 430 can include an asynchronous logic component 435, a DDS component 440, and a table component 450.

[0070] The asynchronous logic component 435 may receive a start signal 436, which may correspond to the central or common start signal described above, and may use the start signal 436 to assert an input SYNC pin of the clock divider / replicator device 420 in response to the start signal 436 being asserted, unless the start signal 436 is masked by the asynchronous logic component 435. The start signal 436 is also used to synchronize the DAC component 470 across multiple DAC cards 410. In other words, the start signal 436 is used for two purposes, which is to provide a coordinated start for all DAC cards 410 in the system, in which case the start signal 436 is masked by the asynchronous logic component 435 and not provided to the divider / replicator device 420, or it may be used to assert an input SYNC pin of the clock divider / replicator device 420, in which case the start signal 436 is not masked from the clock divider / replicator device 420 by the asynchronous logic component 435. The asynchronous logic component 435 may generate a separate signal based on the start signal 436 to assert the input SYNC pin of the clock divider / replicator device 420 .

[0071] The DDS component 440 is configured to implement one or more direct digital synthesizers or synthesizers (DDS) for each output 480 of the DAC card 410 (see, e.g. Figure 4B As mentioned above, a DDS can be a type of signal generator that can construct samples indefinitely once it has been given phase and frequency parameters. Each DDS for a particular output 480 generates a parameterized function that corresponds to a digital version of the waveform or signal that would be provided in analog form by the output 480. For example, the output 480 can provide two tones (f 1 , f 2 ) are associated with two (2) RF control signals, such as Figure 3 In this case, the DDS component 440 may include two (2) DDSs for each output 480, one DDS for generating a parameterized function that is converted to correspond to the first tone (f 1 ) and another DDS is used to generate a parameterized function that is converted to a second tone (f 2 ) associated RF control signal. Different sets of DDS can be implemented for different outputs 480 of the DAC card 410.

[0072] The table component 450 is configured to store a pair of tables for each output 480 of the DAC card 410, wherein the pair of tables collectively provide commands to one or more DDSs in the DDS component 440 for the output 480. The pair of tables includes a first table as a function table and a second table as an instruction table, wherein the function table defines a parameterized function (e.g., a digital sample of a waveform or signal) to be generated by each DDS, and the instruction table defines a subroutine call to the function table or a conditional loop instruction for the function table. In some aspects, the parameterized function defined by the function table is a spline curve. Various parameters can be used to define or characterize each of the multiple segments of the spline curve, including one or more of amplitude, phase, or frequency. As Figure 4A As shown in diagram 400a in FIG. 4 , the digital logic component 430 may receive parameter / configuration information 431, which may be used to populate and / or update parameters in various tables stored in the table component 450, and the parameter / configuration information 431 is used as a basis for DDS to generate parameterized functions.

[0073] Although the digital logic component 430 is described above as being implemented using an FPGA or ASIC, it should be understood that several components or assemblies of the DAC card 410 may be implemented in the same integrated circuit (e.g., an FPGA or ASIC). For example, the digital logic component 430 along with one or more of the divider / replicator device 420, the interface logic component 460, or the DAC component 470 may be implemented in a single integrated circuit. The entire DAC card 410 may also be implemented in a single integrated circuit, and in some instances, more than one DAC card 410 may be implemented in a single integrated circuit.

[0074] Figure 4B A diagram 400b is shown that illustrates an example of implementing multiple DDSs and instructions and spline tables in a DAC card such as the DAC card 410. In this example, it is assumed that the DAC card 410 includes two DAC components 470 (e.g., DAC-1 and DAC-2), where each of the DAC components 470 provides four (4) outputs 480 for a total of eight (8) outputs 480 of the DAC card 410. The DDS component 440 in the digital logic component 430 includes multiple DDSs to support the eight outputs 480. For example, a first set of DDSs 441 may include eight DDSs, where two DDSs are used for each of the four outputs 480 of the first DAC component 470, and a second set of DDSs 442 may also include eight DDSs, where two DDSs are used for each of the four outputs 480 of the second DAC component 470. A subset 443 in the set 441 corresponds to one of the four outputs 440 of the first DAC component 470. The subset 443 includes a DDS for generating a first tone (f 1 ) and a first DDS 444 (DDS 1A) for generating a parameterized function of a first RF control signal associated with a second tone (f 2 ) is used with a second DDS 445 (DDS 1B) that is a parameterized function of an RF control signal associated with the first DAC component 470. Similarly, DDS 2A and DDS 2B are used with different outputs 480 of the first DAC component, as are DDS 3A and DDS 3B and DDS 4A and DDS 4B. A similar arrangement as described above is also used with a second set of DDSs 442, which includes pairs of DDSs 5A and DDS 5B, DDS 6A and DDS 6B, DDS 7A and DDS 7B, and DDS 8A and DDS 8B, which generate parameterized functions for generating RF control signals in the four outputs 480 of the second DAC component 470.

[0075] Table component 450 in digital logic component 430 includes multiple tables that support DDS in DDS component 440. For example, a first set of tables 451 may include eight tables, two of which are used for each pair of DDS associated with four outputs 480 of first DAC component 470, and a second set of tables 452 may also include eight tables, two of which are used for each pair of DDS associated with four outputs 480 of second DAC component 470. Subset 453 in set 451 corresponds to two tables used with subset 443 (DDS 1A and DDS 1B) of DDS in DDS component 440. In this example, subset 453 includes a first table 454 (table 1A) and a second table 455 (table 1B), wherein first table 454 is a function table and second table 455 is an instruction table. Similarly, for the remaining tables in set 451, Table 2A (function table) and Table 2B (instruction table) are used with DDS 2A and DDS 2B, Table 3A (function table) and Table 3B (instruction table) are used with DDS 3A and DDS 3B, and Table 4A (function table) and Table 4B (instruction table) are used with DDS 4A and DDS 4B. A similar arrangement as described above is also used for the second set of tables 452, which include Table 5A (function table) and Table 5B (instruction table) used with DDS 5A and DDS 5B, Table 6A (function table) and Table 6B (instruction table) used with DDS 6A and DDS 6B, Table 7A (function table) and Table 7B (instruction table) used with DDS 7A and DDS 7B, and Table 8A (function table) and Table 8B (instruction table) used with DDS 8A and DDS 8B. Since the parameterized function defined by the function table may be a spline curve, the function table may also be referred to as, for example, a spline table.

[0076] Each of the DDSs shown in DDS component 440 may be a separate and distinct instantiation of a DDS IP block in an FPGA or ASIC, while each of the tables in table component 450 may be implemented in a separate and distinct portion of memory in an FPGA or ASIC.

[0077] Figure 4C FIG. 4 shows an example of using multiple DAC cards 410 to control trapped atoms or atomic ions (e.g., Figure 1AFIG400c is an illustration of an example of an operation of using the atoms or atomic ions 120 in the diagram 100 of FIG4 as a qubit. In this example, N DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) are used in the QIP system, where N ≥ 1. Each of the DAC cards 410 can be implemented or configured as shown in the diagram 400a, and each of the DAC cards 410 can have eight outputs 480. The outputs 480 are then provided to a corresponding AOM or multi-channel AOM to modulate a laser or light beam applied to the atoms or atomic ions 120. If the QIP system supports up to 32 atoms or atomic ions 120, four (4) DAC cards 410 (N = 4) can be used to provide the required 32 outputs 480. If the QIP system is scalable and the number of atoms or atomic ions 120 increases, additional DAC cards 410 can be used to provide the appropriate number of outputs 480.

[0078] As described above, each of the DAC cards 410 receives a clock signal 421 (also referred to as a central or common clock signal) and a start signal 436 (also referred to as a central or common start signal). To achieve proper synchronization across multiple DAC cards 410, these signals are provided through a distribution network that is part of the overall QIP system.

[0079] Figure 5A A diagram 500a is shown showing an example of a start signal distribution network for multiple DAC cards according to aspects of the present disclosure. Diagram 500a shows a master control system 510 at the top of the start signal distribution network, which exchanges a master control signal 512 with a digital logic component 515. The master control signal 512 includes a START1 signal and a START2 signal from the master control system 510 to the digital logic component 515, and a DONE signal from the digital logic component 515 to the master control system 510. The digital logic component 515 uses the START1 signal and the START2 signal to generate a differential start signal 436 having a START+ signal and a START- signal. The digital logic component 515 can be implemented using an FPGA. In one example, the digital logic component 515 can be implemented using a Xilinx Kintex7 FPGA.

[0080] The start signal 436 is provided by the digital logic component 515 to the separator 520, which is configured to separate the start signal 436 so that it is further provided to each of the DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) used in the QIP system, where N ≥ 1. The start signal 436 is provided to each of the DAC cards 410, such as Figure 4AAs described in diagram 400a in FIG. 4 . Since there can be up to N DAC cards 410 in a QIP system, the splitter 520 can be referred to as a 1:N splitter. As described above, one way to distribute the start signal 436 with good signal integrity and fast rise time is to use LVDS routing, such as LVDS on a shielded twinax cable. Each of the cables 530 (dashed lines) shown in diagram 500a can be an LVDS-based cable to achieve the type of signal integrity and rise time required for the start signal 436 to arrive at each DAC card 410 at the same time.

[0081] Figure 5B A diagram 500b is shown showing an example of a clock distribution network for multiple DAC cards according to aspects of the present disclosure. Diagram 500b shows a reference clock source 540 at the top of the clock distribution network, which provides a reference clock signal 541 to a multiplier component 545. The reference clock source 540 may not be part of the clock distribution network, but may be connected to the clock distribution network to provide the reference clock signal 541.

[0082] The multiplier component 545 can be configured to receive the reference clock signal 541 and generate the clock signal 421 from the reference clock signal 541 using one or more multiplier stages. In one example, the multiplier component 545 can be a gold multiplied crystal oscillator (GMXO-PLD) from Wenzel Associates, which has one or more low noise multiplier stages to generate a signal in the range of, for example, 200 MHz to 12 GHz.

[0083] In one example, the reference clock source 540 is an atomic clock source, the reference clock signal 541 is a 10 MHz signal, and the clock signal 421 generated by the multiplier component 545 is a 250 MHz signal.

[0084] The clock signal 421 is provided by the multiplier component 515 to the splitter 550, which is configured to split the clock signal 421 so that it is further provided to each of the DAC cards 410 (e.g., DAC card 410-1, ..., DAC card 410-N) used in the QIP system, where N ≥ 1. The clock signal 421 is provided to the divider / replicator device 420 in each DAC card 410, such as Figure 4A As described in diagram 400a in FIG. 400b. Since there can be up to N DAC cards 410 in a QIP system, the splitter 550 can be referred to as a 1:N splitter. As described above, one way to achieve that all DAC cards 410 see the rising edge of the clock signal 421 at the same time is by using coaxial cables that are all the same length. Each cable 560 (dashed line) shown in diagram 500b can be a coaxial cable of the same length.

[0085] In addition to the aspects and techniques described above with respect to synchronous DAC cards and their outputs, the present disclosure also describes aspects and techniques for enhancing the representation of spline curves, which are then used by DDS to generate parameterized functions. This enhanced spline curve representation includes two methods of reusing sequences: (1) through subroutine calls and (2) through conditional loop instructions.

[0086] To achieve this, instead of using one table, two tables (a spline or function table and an instruction table) are used as described above (see e.g. Figure 4B ). The rows in the spline or function table specify parameters such as amplitude, phase, frequency, etc., and the relative times at which they should occur. The rows in the instruction table usually act as "subroutine calls" to some subsection of the spline table, but can also act as loop iterators.

[0087] To save space, a single spline row (e.g., a single row in a spline table) cannot specify all parameters. Each row has an opcode field to describe which of a set of known parameters it contains, such as frequency slope, initial phase, or amplitude acceleration. In a spline table, a "spline node" consists of many consecutive spline rows. Rows that are not the last for a spline node are marked in some way, perhaps a special bit that is always present, or a special value for a field that usually has some other use, such as all ones ("1") in a relative timestamp field. In addition, not all fields are usually specified in most spline nodes. Unspecified fields either default to a static value, such as zero ("0"), or retain whatever value they had at the end of the previous spline node. This helps achieve space compression. For example, when you only want to specify non-zero values ​​for the 0th and 2nd order coefficients of the amplitude spline, and it is perfect to make the 1st and 3rd order coefficients zero ("0"), then the last two coefficients can be omitted. In another example, when a single spline opcode allows more than one parameter to be specified in the same line, space can be saved if the parameters are used together in common.

[0088] In another aspect, it is sometimes useful for an instruction line (eg, a row in an instruction table) to have additional information, such as modifiers for the amplitude or phase that the spline line may specify.

[0089] In another aspect, the instructions in the instruction table may have an alternative "jump" variant that compares 1 of the N counters to a constant. If it is equal to or greater than the constant, the operation proceeds to the next instruction. Otherwise, it increments the counter and then jumps to the user-defined line of the instruction table. The jump instruction does not result in a "subroutine call" to the spline table. In addition, jump instructions can be distinguished from non-jump instructions by having a reserved bit for this purpose in all instructions or by using a special value.

[0090] In yet another aspect, there may be two (2) types of timestamps used in conjunction with a function or spline table and an instruction table. For example, each instruction line may use a global timestamp (e.g., a timestamp associated with tracking the time since the start of an experiment shot), while each spline line has a narrower relative timestamp (e.g., a timestamp associated with tracking the time since the start of a spline subroutine). However, only the timestamp of the last line may be used to control execution time. Lines other than the last line may use a timestamp field to indicate something else, e.g., not the last line. The sum of the global timestamp and the relative timestamp needs to correspond exactly to the current time, i.e., when the wide counter is cleared at the start of an experiment shot, the first portion of the spline subroutine is to run.

[0091] When a spline function is generated by using an instruction table in addition to a spline or function table, the above technique provides a level of indirection to indicate how the spline table is reused.

[0092] Figure 6 A diagram 600 is shown showing an example of a combined operation of an instruction table 610 and a function or spline table 620 according to aspects of the present disclosure. The instruction table 610 may correspond to the instruction table in the table component 450 (see, e.g., Figure 4A FIG. 400a and Figure 4B 400b), and the spline table 620 can correspond to the spline table in the table component 450.

[0093] In this example, the instruction table 610 has two parameters, "Call" and "Jump". As described above, "Jump" can be used to repeat in the instruction table, compare any number of counters to the value in the instruction, and increment if it is to jump back and repeat. In this example, there are program instructions one "Call", one "Jump", and one "End". "End" is indicated by a "0" in the timestamp field (e.g., an absolute timestamp), although other fields or special values ​​can also be used to indicate "End" in the instruction table 610.

[0094] The difference between a "call" and a "jump" is indicated by a special value in the field. This field may be called a "jump where" field, and may be, for example, a 12-bit field. In one example, the maximum value of the "jump where" field may be reserved to indicate that it is a "jump" rather than a "call".

[0095] The "Call" in this example calls location "123" in spline table 620 and is intended to return from spline table 620 three (3) rows later. Therefore, rather than using an explicit return in spline table 620, one can indicate in the "Call" in instruction table 610 how long the subroutine is.

[0096] On the right side of instruction table 610 is the corresponding timestamp (absolute timestamp), which is the time when the "call" will occur. If it is not the current time, it will wait for a large counter until it is the value "11" in the example. This value "11" is not the value that will be used, but the engine running the operations of these tables will use the value "11" in instruction table 610 and get the corresponding value from the relative timestamp field in spline table 620 (e.g., the third or right column in spline table 620). The number "4" in the third column of spline table 620 is added to "11" to get "15", which is the combined time value provided by the absolute timestamp and the relative timestamp, and is the value used by the system to start execution (e.g., execution starts at "15" ticks).

[0097] The spline table 620 has an "Operation Code" field (the first or left column in the spline table 620) that indicates which parameter is specified. This approach is in contrast to having a spline function or waveform defined by a stream from a host, and requires a large amount of memory, as the intent here is to compress the contents of the table as much as possible, thereby using fewer memory bits to represent common operations, parameters, etc. For example, in the first row shown for the spline table 620 (e.g., row "123"), a single row may be used to specify a frequency value, in this case "200 MHz". In another example, in the second row shown for the spline table 620 (e.g., row "124"), a single row may be used to specify the zero order and third order values ​​of the gain parameter. For the gain parameter, the zero order is referred to as the starting point, the first order is referred to as the slope, the second order is referred to as the acceleration, and the third order is referred to as the jerk. In this example, the second row identifies the value of the zero order or starting point as "32k" and the third order or jerk as "0" (e.g., there is no jerk). In another example, the third row in spline table 620 also specifies a phase value of "48°". The "-1" in the right column (e.g., relative timestamp) in the first and second rows of spline table 620 indicates that these rows are not the last rows of the subroutine. A bit field or a specific value can also be used to indicate that a row is not the last row.

[0098] Typically, there will be many rows grouped together, and they are part of something happening at the same time in the spline table 620. That is, multiple changes happening in the same group of rows happen on the same clock cycle. Therefore, all commands are flattened into the last command.

[0099] The only one of these rows that is relevant for timing is the last row (e.g., row "125") which has a value of "4". The engine running the table operation iterates through the rows until it reaches row "125", which does not have a "-1" in the relative timestamp. The engine accumulates all commands up to the last row and unwinds all command operations that will occur at the appropriate time. Depending on how the system is set up to operate, any parameters not specified in the various rows may default to zero values ​​and / or previous values.

[0100] In addition to the various aspects described above, another aspect of the present disclosure relates to adding features to the instruction table that allow for resetting an embedded DDS (e.g., a DDS in DDS component 430) with fine granularity. This may be useful when implementing pulse boundaries. For example, each non-jump instruction location may have a bit flag (e.g., a "resync" bit flag) that causes the DDS to be told to reset its internal phase accumulator when the instruction's global timestamp and relative timestamp match the current time of day.

[0101] In this regard, the instruction table 610 may include another column, such as a single bit field, that may be renumbered by the engine running the table when execution time is reached, and one of the things that may be done is clearing the phase accumulator of the DDS. That is, when execution time is finally reached (e.g., at Figure 6 In the example in diagram 600, the added value is "15"), the engine can not only instruct the corresponding DDS to clear its internal phase to "0°", but also set it to the phase shown in the "125" row, that is, set its phase to "48°".

[0102] In yet another aspect, some parameters outside of the spline mechanism outlined above may also be changed so that parameters can be scaled globally without the need to download or update new splines for a signal generator (e.g., DDS) for a particular atom or atomic ion. An example of such a change may be to calibrate the optical power seen by an atom or atomic ion. It may be desirable to change the electrical amplitude after each "shot" of each experiment so that changes in brightness may be tracked with as little lag as possible. Techniques for increasing the bandwidth in the controlled loop may be used to reduce latency so that rapid changes in brightness may be tracked without missing a single one.

[0103] For example, since a DDS typically operates at full scale, any smaller values ​​can be achieved by multiplication or scaling after the DDS provides a parameterized function. If the DDS is implemented in an FPGA or ASIC, it may include a multiplier to perform such a function. If not, an external multiplier may be required. In either case, a multiplier may be used to adjust the parameters in the instruction table 610, a different multiplier may be used to adjust the parameters in the spline table 620, and / or a global multiplier may be used to adjust the parameters from either table or both tables.

[0104] Although the parameters of the waveform or parameterized function generated by DDS have been combined in Figure 6 An example is shown in diagram 600 in A, where each pair of tables (e.g., instruction table 610 and spline table 620) can be used to control the operation of more than one DDS. In this case, additional fields or columns can be used to indicate which of the multiple DDSs being supported is being controlled.

[0105] Figure 7 700 is a diagram illustrating an example of a computer device 705 according to aspects of the present disclosure. The computer device 705 may be used to implement aspects of a scalable and programmable coherent waveform generator for a QIP system. In one example, the computer device 705 may include a processor 710 for performing processing functions associated with one or more features described herein. For example, the computer device 705 may be used to control and / or manage the above-described FIG. 4A to FIG. 6 DAC card 410, the distribution network in diagram 500a and 500b, and / or the operation of table 610 and 620 described. Processor 710 can include single group or multiple groups of processors or multi-core processors. In addition, processor 710 can be implemented as an integrated processing system and / or a distributed processing system. Processor 710 can include a central processing unit (CPU), a quantum processing unit (QPU), a graphics processing unit (GPU) or a combination of these types of processors. In one aspect, processor 710 can refer to a general-purpose processor of computer device 705, which can also include additional processors 710 to perform more specific functions.

[0106] In one example, the computer device 705 may include a memory 720 for storing instructions executable by the processor 710 for performing the functions described herein. In one implementation, for example, the memory 720 may correspond to a computer-readable storage medium storing code or instructions to perform one or more of the functions or operations described herein. In one example, the memory 720 may include an instruction table and a spline table. Like the processor 710, the memory 720 may refer to the general memory of the computer device 705, which may also include additional memory 720 to store instructions and / or data for more specific functions.

[0107] In addition, the computer device 705 may include a communication component 730 that provides for the use of hardware, software, and services to establish and maintain communications with one or more parties. The communication component 730 may carry communications between components on the computer device 705 and between the computer device 705 and external devices (e.g., devices located on a communication network and / or devices connected in series or locally to the computer device 705). For example, the communication component 730 may include one or more buses and may further include a transmit chain component and a receive chain component associated with a transmitter and a receiver, respectively, which are operable to interface with external devices.

[0108] In addition, computer device 705 may include data storage 740, which may be any suitable combination of hardware and / or software that provides mass storage of information, databases, and programs employed in conjunction with the implementations described herein. For example, data storage 740 may be a data repository for operating system 760 (e.g., a classical OS or a quantum OS). In one implementation, data storage 740 may include memory 720.

[0109] Computer device 705 may also include user interface component 750, which may be operable to receive input from a user of computer device 705, and may also be operable to generate output for presenting to a user or providing to different systems (directly or indirectly). User interface component 750 may include one or more input devices, including but not limited to keyboard, numeric keypad, mouse, touch-sensitive display, digitizer, navigation key, function key, microphone, speech recognition component, any other mechanism that may receive input from a user, or any combination thereof. In addition, user interface component 750 may include one or more output devices, including but not limited to display, loudspeaker, tactile feedback mechanism, printer, any other mechanism that may present output to a user, or any combination thereof.

[0110] In one implementation, the user interface component 750 may send and / or receive messages corresponding to the operation of the operating system 760. In addition, the processor 710 may execute the operating system 760 and / or applications, programs or algorithms, and the memory 720 or data storage 740 may store them.

[0111] When computer device 705 is implemented as part of a cloud-based infrastructure solution, user interface component 750 may be used to allow a user of the cloud-based infrastructure solution to interact with computer device 705 remotely.

[0112] Figure 88 is a block diagram 800 illustrating an example of a QIP system 805 according to aspects of the present disclosure. The QIP system 805 may also be referred to as a quantum computing system, a quantum computer, a computer device, etc. In one aspect, the QIP system 805 may correspond to Figure 7 Part of a quantum computer implementation scheme of computer device 705 in.

[0113] The QIP system 805 may include a source 860 that provides atomic species (e.g., a flux of neutral atoms) to a chamber 850 having an ion trap 870 that captures the atomic species once ionized (e.g., photoionized) by the optical controller 820. The ion trap 870 may be used to capture ions in a crystal (e.g., Figure 1A 100a in FIG. 100b). The light source 830 in the optical controller 820 may include one or more laser or beam sources that may be used for ionization of atomic species, control of atomic ions (e.g., phase control), fluorescence of atomic ions, which may be monitored and tracked by image processing algorithms operating in an imaging system 840 in the optical controller 820, and / or perform other optical control functions associated with the techniques described herein. In one aspect, the light source 830 may be implemented separately from the optical controller 820.

[0114] The imaging system 840 may include a high-resolution imager (e.g., a CCD camera) for monitoring the atomic ions as they are provided to the ion trap or after they are provided to the ion trap 870. In one aspect, the imaging system 840 may be implemented separately from the optical controller 820, however, the use of image processing algorithms to detect, identify, and label the fluorescence of the atomic ions may require coordination with the optical controller 820.

[0115] The acousto-optic modulator AOM 845 may be used to perform modulation of the laser or light beam generated by the light source 830. In this regard, the optical controller 820 may also include a DAC card 846, which may be an example of the DAC card 410 described above, and may be used to generate an output to drive a radio frequency (RF) source 847 to modulate the AOM 845.

[0116] The QIP system 805 may also include an algorithm component 810 that may operate with other parts of the QIP system 805 (not shown) to perform quantum algorithms or quantum operations, including single-qubit operations or multi-qubit operations and extended quantum computations. Thus, the algorithm component 810 may provide instructions to various components of the QIP system 805 (e.g., to the optical controller 820) to implement the implementation of the quantum algorithm or quantum operation, and thus implement the various techniques described herein.

[0117] The QIP system 805 may also include a distribution network 880, which may include a clock signal network 882 and a start signal network 883. The clock signal network 882 corresponds to the above combination. Figure 5B The distribution network described in the diagram 500b in FIG. 8, the start signal network 883 corresponds to the above combination Figure 5A The distribution network 880 is depicted in diagram 500a in FIG. The distribution network 880 may be used to provide a common signal to multiple DAC cards 486 and / or other portions of the QIP system 805 .

[0118] Although the present disclosure has been provided according to the illustrated implementations, it will be readily appreciated by those skilled in the art that there may be variations to the embodiments, and these variations will be within the scope of the present disclosure. Therefore, many modifications may be made by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A system for synchronizing multiple digital-to-analog converter cards, i.e., multiple DAC cards, in a quantum information processing (QIP) system, the system comprising a network, the network include: The plurality of DAC cards, each DAC card comprising: A clock divider / replicator device with an input SYNC pin; Digital logic components; and one or more DAC components, wherein each output of the DAC components is used to control one or more beams for a separate qubit of the QIP system; a first distribution network for providing a clock signal to a clock divider / replicator device in each DAC card of the plurality of DAC cards, a second distribution network for providing a start signal to each DAC card of the plurality of DAC cards, Wherein, for each DAC card of the plurality of DAC cards, a digital logic component in the DAC card uses the start signal to assert an input SYNC pin of a clock divider / replicator device of the DAC card in response to the start signal being asserted, unless the start signal is shielded by the digital logic component.

2. The system according to claim 1, in, Each DAC card of the plurality of DAC cards is implemented as a single integrated circuit, and the clock divider / replicator device, the digital logic component, and the one or more DAC components are part of the integrated circuit.

3. The system according to claim 1, in, Two or more of the plurality of DAC cards are implemented as a single integrated circuit, and the clock divider / replicator device, the digital logic component, and the one or more DAC components of each of the DAC cards are part of the single integrated circuit.

4. The system according to claim 1, in, One or more of the clock divider / replicator device, the digital logic component, and the one or more DAC components of each DAC card of the plurality of DAC cards are implemented as a single integrated circuit.

5. The system according to claim 1, in, Each DAC card also includes interface logic that connects the digital logic component to the one or more DAC components.

6. The system according to claim 1, in, The digital logic component in each DAC card includes asynchronous logic that receives the start signal and generates another signal to assert an input SYNC pin of a clock divider / replicator device in that DAC card.

7. The system according to claim 1, in, The first distribution network includes a passive splitter and is configured to receive the clock signal at the passive splitter, which is then configured to provide the clock signal to a clock divider / replicator device in each DAC card of the plurality of DAC cards.

8. The system according to claim 7, in, The first distribution network includes a plurality of coaxial cables of the same length, and the clock signal is provided from the passive splitter to each DAC card of the plurality of DAC cards through a corresponding one of the plurality of coaxial cables.

9. The system according to claim 1, in, The first distribution network includes multiplier logic and is configured to receive a reference clock signal at the multiplier logic, the multiplier logic being configured to generate the clock signal from the reference clock signal using one or more multiplier stages.

10. The system according to claim 1, in, The second distribution network includes a splitter and is configured to receive the start signal at the splitter, the splitter being configured to then provide the start signal to the plurality of DAC cards.

11. The system according to claim 10, in, The second distribution network includes a plurality of low voltage differential signals, ie, a plurality of LVDS, on a shielded twinaxial cable, and the start signal is provided from the splitter to each DAC card of the plurality of DAC cards through a corresponding one of the plurality of LVDS on the shielded twinaxial cable.

12. The system according to claim 1, in, Each individual qubit of the QIP system that is controlled corresponds to an atom or atomic ion in the trap of the QIP system.

13. A digital-to-analog converter (DAC) card for controlling quantum bits in a quantum information processing (QIP) system, the DAC card include: A digital logic component having: one or more direct digital synthesizers (DDS) for each output of the DAC card, wherein each output controls one or more beams for a separate qubit of the QIP system; and collectively providing a pair of tables of commands to the one or more DDSs, a first table of the pair of tables being a function table and a second table of the pair of tables being an instruction table, the function table defining parameterized functions to be generated by the one or more DDSs, and the instruction table defining subroutine calls to the function table or conditional loop instructions for the function table; and one or more DAC components, each DAC component providing one or more outputs of the DAC card, each DAC component receiving a parameterized function generated by the one or more DDS to generate the one or more outputs, wherein the parameterized function is in digital form and the one or more outputs are in analog form, The parameterized function defined by the function table is a spline curve, and the parameters for each segment of the spline curve include one or more of amplitude, phase, and frequency.

14. The DAC card according to claim 13, in, The spline curve includes an amplitude defined by one or more of a starting point or zero order, a slope or first order, an acceleration or second order, and a jerk or third order.

15. The DAC card according to claim 13, in, The function table includes a plurality of spline nodes, and each spline node includes parameters for defining a corresponding segment of the spline curve.

16. The DAC card according to claim 15, in, Each spline node includes one or more sequential rows, and each row specifies a different parameter of the corresponding segment of the spline curve.

17. The DAC card according to claim 16, in, Each row has an identifier that identifies a different parameter defined by that row.

18. The DAC card according to claim 17, in, The identifier identifies more than one different parameter defined by the row.

19. The DAC card according to claim 16, in, An end of each spline knot is explicitly identified in a last row of the one or more sequential rows of the spline knots.

20. The DAC card according to claim 19, in, Each row of the spline nodes comprises a timestamp field, the unambiguous identification in the last row being made in the corresponding timestamp field of the last row.

21. The DAC card according to claim 16, in, One or more different parameters of the corresponding segment of the spline curve that are not specified in one or more rows of the spline knots are defaulted to static values ​​or retained as the values ​​of the end of the previous spline knot.

22. The DAC card according to claim 13, in, The instruction table includes instructions to change one or both of the amplitude or phase parameters.

23. The DAC card according to claim 13, in, The instruction table includes one or more jump instructions, each jump instruction performs a comparison of one of the N counters with a constant, and if they are equal or greater, proceeds to the next instruction, otherwise increments the counter and jumps to a user-defined row of the instruction table.

24. The DAC card according to claim 23, in, The one or more jump instructions can be distinguished from other instructions in the instruction table by having reserved bits or by using special values.

25. The DAC card according to claim 13, in, The rows in the instruction table include a global timestamp field for tracking operations since the start of an experiment shoot, and the rows in the function table include relative timestamps for tracking operations associated with spline nodes defining corresponding segments of the parameterized function.

26. The DAC card according to claim 25, in, The current time when the spline node is executed is the sum of the value of the global timestamp and the value of the relative timestamp.

27. The DAC card according to claim 13, in, For instructions other than jump instructions in the instruction table, the bit flag resynchronization is configured to cause the one or more DDSs associated with the instruction table to reset an internal phase accumulator at a boundary of the parameterized function.

28. The DAC card according to claim 27, in, A reset of the internal phase accumulator occurs when the value of the global timestamp field in the instruction table and the value of the relative timestamp field in the function table match the current time of day.

29. The DAC card of claim 13, further comprising a clock divider / replicator device having an input SYNC pin, in, The digital logic component is configured to receive a start signal for asserting an input SYNC pin of a clock divider / replicator device unless the start signal is masked by the digital logic component.

30. The DAC card according to claim 29, in, The digital logic component includes an asynchronous logic component configured to receive the start signal and generate another signal to assert an input SYNC pin of the clock divider / replicator device.

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