Testing input / output speed conversion and related equipment and methods

Abstract

This invention discloses a test input / output speed conversion device and related apparatus and method. One apparatus includes a glued-connect circuit and a BIST circuit for a core circuit system of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glued-connect circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glued-connect circuit is configured to convert between a second speed test interface signal and a second speed input / output signal operating at a second speed, and a first speed test interface signal and a first speed input / output signal operating at the first speed. The second speed is different from the first speed.

Description

[0001] Priority Claim

[0002] This application claims the filing date benefit of U.S. Patent Application No. 16 / 953,828, entitled “TEST INPUT / OUTPUT SPEED CONVERSION AND RELATED APPARATUSES AND METHODS”, filed November 20, 2020. Technical Field

[0003] This disclosure generally relates to testing input / output speed conversion, and more specifically, to the conversion between a first speed signal and a second speed signal for a built-in self-test (BIST) circuit operating at a first speed. Background Technology

[0004] The P1500 standard is a test operation standard specified by the Institute of Electrical and Electronics Engineers (IEEE). The P1500 test interface is a test interface between the embedded core and the system-on-a-chip (SoC), used to test core interoperability. P1500 specifies the Core Test Language (CTL) for transmitting test knowledge about the core and its extensible wrappers. P1500 does not specify how to test the core itself. More precisely, P1500 specifies the test wrappers surrounding the core and their interfaces to one or more Test Access Mechanisms (TAMs). Summary of the Invention

[0005] In some embodiments, a device includes a built-in self-test (BIST) circuit and a glued connection circuit for a core circuitry system of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. The glued connection circuit is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glued connection circuit is configured to switch between a second-speed test interface signal and a second-speed input / output signal operating at a second speed and a first-speed test interface signal and a first-speed input / output signal operating at the first speed. The second speed is different from the first speed.

[0006] In some embodiments, a device includes a built-in self-test (BIST) circuit for a core circuitry system of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. The device also includes a glue-connected circuit electrically connected to the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The glue-connected circuit is configured to switch between a second-speed test interface signal and a second-speed input / output signal operating at a second speed and a first-speed test interface signal and a first-speed input / output signal operating at a first speed. The second speed is different from the first speed. The device further includes a clock generator configured to provide a first-speed clock signal operating at the first speed to the glue-connected circuit.

[0007] In some embodiments, a method of interfacing with a built-in self-test (BIST) circuit includes providing a first speed wrapper clock signal to the BIST circuit. The first speed wrapper clock signal operates at a first speed. The method further includes providing a first speed test interface signal, operating at the first speed, to a test interface of the BIST circuit in response to a second speed test interface signal, operating at a second speed. The second speed is different from the first speed. The method further includes providing one or more first speed input signals, operating at the first speed, to one or more inputs of the BIST circuit in response to one or more second speed input signals, operating at the second speed. The method also includes providing one or more second speed output signals, operating at the second speed, in response to one or more first speed output signals, operating at the first speed, received from one or more outputs of the BIST circuit.

[0008] In some embodiments, a device includes circuitry and adhesive bonding circuitry. The circuitry includes one or more inputs and one or more outputs. The circuitry is configured to operate at a first speed. The one or more inputs are configured to receive one or more first speed input signals. The one or more outputs are configured to provide one or more first speed output signals. The adhesive bonding circuitry is configured to interface with the one or more inputs and one or more outputs of the circuitry. The adhesive bonding circuitry is configured to switch between one or more second speed input signals operating at a second speed and one or more first speed input signals operating at a first speed. The adhesive bonding circuitry is further configured to switch between one or more second speed output signals operating at a second speed and one or more first speed output signals operating at a first speed. The second speed is different from the first speed. Attached Figure Description

[0009] Although this disclosure concludes with claims that particularly point out and expressly assert particular embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily apparent from the following description, read in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a block diagram of a test wrapper according to some embodiments;

[0011] Figure 2 This is a flowchart illustrating a method of interfacing with a BIST circuit according to some embodiments;

[0012] Figure 3 This is a block diagram of a test wrapper according to some embodiments, which is Figure 1 An example of a test package that interfaces between a high-speed signal and a low-speed P1500 BIST circuit;

[0013] Figure 4 yes Figure 3 The signal timing diagram of an example of the test wrapper's signal;

[0014] Figure 5 This is a block diagram of a test wrapper according to some embodiments, which is Figure 1 An example of a test package that interfaces between a low-speed signal and a high-speed P1500 BIST circuit;

[0015] Figure 6 yes Figure 5 The signal timing diagram of an example of the test wrapper's signal;

[0016] Figure 7 yes Figure 5 Signal timing diagrams for other instances of the test wrapper's signals;

[0017] Figure 8 This is a block diagram of a high-bandwidth memory+ (HBM+) system according to some embodiments;

[0018] Figure 9 This is a block diagram of an integrated circuit device according to some embodiments; and

[0019] Figure 10 This is a block diagram of a computing system according to some embodiments. Detailed Implementation

[0020] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure and illustrate specific examples in which embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure. However, other embodiments implemented herein may be utilized, and structural, material, and process changes may be made without departing from the scope of the disclosure.

[0021] The descriptions presented herein are not intended to represent actual views of any particular method, system, apparatus, or structure, but are merely idealized representations for describing embodiments of this disclosure. In some instances, for the convenience of the reader, similar structures or components in the various figures may retain the same or similar numbering; however, similarity in numbering does not necessarily imply that the size, composition, configuration, or any other property of the structures or components are the same.

[0022] The following description may include examples that will enable those skilled in the art to practice the disclosed embodiments. The use of the terms “exemplary,” “by example,” and “for example” implies that the description is explanatory, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to the specified components, steps, features, functions, or the like.

[0023] It will be readily understood that the components of the embodiments generally described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following description of the various embodiments is not intended to limit the scope of this disclosure, but rather to illustrate the various embodiments only. While various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless explicitly indicated.

[0024] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Components, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Conversely, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise specified herein. Additionally, block definitions and logical divisions between blocks are examples of specific embodiments. It will be readily apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations and the like have been omitted, where such details are not necessary for obtaining a full understanding of this disclosure and are beyond the capabilities of those skilled in the art.

[0025] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and skills. For clarity of presentation and description, some diagrams may illustrate a signal as a single signal. Those skilled in the art should understand that a signal can represent a signal bus, wherein the bus can have various bit widths, and this disclosure can be implemented on any number of data signals comprising a single data signal.

[0026] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or executed using a general-purpose processor, special-purpose processor, digital signal processor (DSP), integrated circuit (IC), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor), multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration. A general-purpose computer containing a processor is considered a special-purpose computer, and the general-purpose computer is configured to execute computational instructions (e.g., software code) related to the embodiments of this disclosure.

[0027] Implementations can be described from the perspective of processes depicted as flowcharts, flow diagrams, or block diagrams. Although flowcharts can describe actions as a sequential process, many of these actions can be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. Processes can correspond to methods, threads, functions, programs, subroutines, subroutines, other structures, or combinations thereof. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, the functionality can be stored or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one place to another.

[0028] Any reference to elements indicated herein by designations such as "first," "second," etc., does not limit the number or order of said elements unless such limitation is expressly stated. Rather, these designations are used herein as a convenient way to distinguish two or more elements or examples of elements. Therefore, references to first and second elements do not imply that only two elements may be used therein, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may contain one or more elements.

[0029] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, as understood by one of ordinary skill in the art, the degree to which a given parameter, property, or condition is satisfied with a small range of variation (e.g., within acceptable manufacturing tolerances, for example). By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0030] As used herein, the term "velocity" refers to the frequency of a signal when used to describe a signal. Therefore, "first velocity signal" can refer to a signal having a first frequency, and "second velocity signal" can refer to a signal having a second frequency.

[0031] Standard low-speed P1500 blocks and newer high-speed P1500 blocks are known in the art. By way of non-limiting examples, high-speed P1500 blocks can operate at speeds up to 800 MHz (e.g., in High Bandwidth Memory 2 (HBM2) memory devices) to 1.6 GHz (e.g., in High Bandwidth Memory 3 (HBM3) memory devices), while low-speed P1500 blocks can operate at speeds as low as 100 MHz. Only low-speed inputs / outputs are available for standard low-speed P1500 blocks. However, these low-speed inputs / outputs have relatively longer runtimes compared to the high-speed inputs / outputs of newer high-speed P1500 blocks. Therefore, systems incorporating standard low-speed P1500 blocks are needed to check memory parameters such as cell hold time to avoid data loss in P1500 task mode interleaving situations.

[0032] The newer high-speed P1500 blocks avoid the drawbacks associated with the slow input / output of the standard low-speed P1500 blocks because they accept high-speed input / output associated with relatively short runtimes. However, these newer high-speed P1500 blocks impose relatively high design complexity on both the memory (e.g., dynamic random access memory (DRAM)) and controller sides to justify their use only in terms of the associated shorter runtimes.

[0033] This paper presents a glued-in circuit configured to switch between a first speed input / output and a second speed input / output signal in a BIST circuit. The glued-in circuit can therefore be used to switch between high-speed and low-speed input / output signals of a standard low-speed P1500 block to provide the advantages associated with shorter runtimes of high-speed input / output, while avoiding the relatively high design complexity associated with newer high-speed P1500 blocks. The glued-in circuit can also be used to switch between low-speed and high-speed input / output signals of a newer high-speed P1500 block to enable the newer high-speed P1500 block to interface with a system that would otherwise only be able to interface with a standard low-speed P1500 block, since the system can only utilize low-speed input / output signals in place of high-speed input / output signals.

[0034] In some embodiments, a device includes glued circuitry and a BIST circuitry for a core circuit system of an integrated circuit device. The BIST circuitry includes a test interface, one or more inputs, and one or more outputs. The BIST circuitry is configured to operate at a first speed. The glued circuitry is configured to interface with the test interface, the one or more inputs, and the one or more outputs of the BIST circuitry. The glued circuitry is configured to switch between a second speed test interface signal and a second speed input / output signal operating at a second speed and a first speed test interface signal and a first speed input / output signal operating at the first speed. The second speed is different from the first speed.

[0035] In some embodiments, a device includes a BIST circuit, a bonding circuit, and a clock generator. The BIST circuit is used in the core circuitry of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. The bonding circuit is electrically connected to the test interface, the one or more inputs, and the one or more outputs of the BIST circuit. The bonding circuit is configured to switch between a second-speed test interface signal and a second-speed input / output signal operating at a second speed and a first-speed test interface signal and a first-speed input / output signal operating at a first speed. The second speed is different from the first speed. The clock generator is configured to provide a first-speed clock signal operating at the first speed to the bonding circuit.

[0036] In some embodiments, a method of interfacing with a BIST circuit includes providing a first speed wrapper clock signal to the BIST circuit. The first speed wrapper clock signal operates at a first speed. The method further includes providing a first speed test interface signal, operating at the first speed, to a test interface of the BIST circuit in response to a second speed test interface signal, operating at a second speed. The second speed is different from the first speed. The method further includes providing one or more first speed input signals, operating at the first speed, to one or more inputs of the BIST circuit in response to one or more second speed input signals, operating at the second speed. The method also includes providing one or more second speed output signals, operating at the second speed, in response to one or more first speed output signals, operating at the first speed, received from one or more outputs of the BIST circuit.

[0037] In some embodiments, a device includes circuitry and adhesive bonding circuitry. The circuitry includes one or more inputs and one or more outputs. The circuitry is configured to operate at a first speed. The one or more inputs are configured to receive one or more first speed input signals. The one or more outputs are configured to provide one or more first speed output signals. The adhesive bonding circuitry is configured to interface with the one or more inputs and one or more outputs of the circuitry. The adhesive bonding circuitry is configured to switch between one or more second speed input signals operating at a second speed and one or more first speed input signals operating at a first speed. The adhesive bonding circuitry is further configured to switch between one or more second speed output signals operating at a second speed and one or more first speed output signals operating at a first speed. The second speed is different from the first speed.

[0038] Figure 1 This is a block diagram of a test package 100 according to some embodiments. The test package 100 can be configured to test the core circuitry of an integrated circuit device. Therefore, the integrated circuit device may include the test package 100 and the core circuitry. The test package 100 includes a BIST circuit 102, a target block 104, a bonding circuit 106, and optionally a clock generator 108. The BIST circuit 102 includes a test interface 116, one or more inputs 112, and one or more outputs 114. The BIST circuit is configured to operate at a first speed.

[0039] Adhesive bonding circuit 106 is electrically connected to and configured to interface with test interface 116, one or more inputs 112, and one or more outputs 114 of BIST circuit 102. Adhesive bonding circuit 106 is configured to switch between a second speed signal operating at a second speed and a first speed signal operating at a first speed. By way of non-limiting examples, the adhesive circuit 106 may be configured to switch between a second speed test interface signal 134 (e.g., a second speed capture signal 124, a second speed shift signal 126, and a second speed update signal 128) and a first speed test interface signal 148 (e.g., a first speed capture signal 138, a first speed shift signal 140, and a first speed update signal 142), between a second speed input / output signal (e.g., one or more second speed input signals 130 and one or more second speed output signals 132) and a first speed input / output signal (e.g., one or more first speed input signals 144 and one or more first speed output signals 146), between a second speed selection signal 122 and a first speed selection signal 136, and between a second speed packer clock signal 118 and a first speed packer clock signal 120.

[0040] The second speed is different from the first speed. Therefore, the adhesive circuit 106 includes a serializer / deserializer 110 configured to serialize a relatively slow parallel signal to generate a relatively fast serial signal and to deserialize a relatively fast serial signal to generate a relatively slow parallel signal.

[0041] In some embodiments, the first speed is slower than the second speed. In some such embodiments, the serializer / deserializer 110 includes a deserializer (not shown) electrically connected to one or more inputs 112. The deserializer may be configured to provide one or more first speed input signals 144 (e.g., first speed parallel input signals) to one or more inputs 112 in response to one or more second speed input signals 130 (e.g., second speed serial input signals). For example, the deserializer may be configured to convert one or more second speed input signals 130 (e.g., second speed serial input signals) into one or more first speed input signals 144 (e.g., first speed parallel input signals). The glued circuit 106 is configured to provide the first speed parallel input signal to one or more inputs 112 of the BIST circuit 102. In such embodiments, the serializer / deserializer 110 also includes a serializer (not shown) electrically connected to one or more outputs 114. The serializer can be configured to provide one or more second speed output signals 132 (e.g., second speed serial output signals) in response to one or more first speed output signals 146 (e.g., first speed parallel output signals) received from one or more outputs 114. For example, the serializer can be configured to convert one or more first speed output signals 146 (e.g., first speed parallel output signals) received from one or more outputs 114 of the BIST circuit 102 into one or more second speed output signals 132 (e.g., second speed serial output signals).

[0042] In some embodiments, the first speed is faster than the second speed. In some such embodiments, the serializer / deserializer 110 includes a serializer (not shown) electrically connected to one or more inputs 112. The serializer may be configured to provide one or more first speed input signals 144 (e.g., first speed serial input signals) to one or more inputs 112 in response to one or more second speed input signals 130 (e.g., second speed parallel input signals). For example, the serializer may be configured to convert one or more second speed input signals 130 (e.g., second speed parallel input signals) into one or more first speed input signals 144 (e.g., first speed serial input signals). Glue-connected circuitry 106 is configured to provide the first speed serial input signal to one or more inputs 112 of BIST circuitry 102. In such embodiments, glue-connected circuitry 106 also includes a deserializer (not shown) electrically connected to one or more outputs 114. The deserializer can be configured to provide one or more second speed output signals 132 (e.g., second speed parallel output signals) in response to one or more first speed output signals 146 (e.g., first speed serial output signals) received from one or more outputs 114. For example, the deserializer can be configured to convert one or more first speed output signals 146 (e.g., first speed serial output signals) received from one or more outputs 114 of the BIST circuit 102 into one or more second speed output signals 132 (e.g., second speed parallel output signals).

[0043] Adhesive bonding circuit 106 is configured to provide a first-speed packager clock signal 120, configured to operate at a first speed, to BIST circuit 102 and target block 104. Therefore, BIST circuit 102 and target block 104 are configured to operate at the first speed. Adhesive bonding circuit 106 is also configured to receive a second-speed packager clock signal 118, operating at a second speed.

[0044] In embodiments where the test package 100 includes a clock generator 108, the clock generator is configured to provide a first speed clock signal 150 operating at a first speed to the adhesive circuit 106. By a non-limiting example, the clock generator 108 may be configured to provide the first speed clock signal 150 in response to a reference clock signal (not shown) (e.g., an external clock signal, an internal clock signal, etc.). The adhesive circuit 106 may be configured to use the first speed clock signal 150 when switching between a second speed signal and a first speed signal. However, in some embodiments, the test package 100 may not include a clock generator 108, in which case the adhesive circuit 106 may receive the first speed clock signal 150 from outside the test package 100 (e.g., from outside the integrated circuit device, from the core circuitry, etc.).

[0045] Test wrapper 100 is configured to enable testing of the core circuitry of the integrated circuit device. By a non-limiting example, the core circuitry may include circuitry for a logic die of a high-bandwidth memory device (HBM device). Also by a non-limiting example, BIST circuit 102 may include a P1500 BIST circuit. As another non-limiting example, BIST circuit 102 may include a P1500 wrapper control block. As yet another non-limiting example, BIST circuit 102 may include another serial interface BIST circuit, such as the Joint Test Action Group (JTAG) (IEEE 1194.1) BIST.

[0046] Figure 2 This describes the BIST circuit according to some embodiments (e.g.) Figure 1 The flowchart of method 200 for interfacing with BIST circuit 102 is shown. In operation 202, method 200 provides a first speed packager clock signal to the BIST circuit, the first speed packager clock signal operating according to a first speed.

[0047] In operation 204, method 200 provides a first speed test interface signal operating at a first speed to the test interface of the BIST circuit in response to a second speed test interface signal operating at a second speed, the second speed being different from the first speed. In some embodiments, providing the first speed test interface signal includes providing a first speed selection, capture, shift, and update package signal in response to a second speed selection, capture, shift, and update package signal.

[0048] In operation 206, method 200 provides one or more first speed input signals, operating at a first speed, to one or more inputs of the BIST circuit in response to one or more second speed input signals operating at a second speed. In some embodiments, providing one or more first speed input signals in response to one or more second speed input signals includes providing a first speed parallel input signal in response to a second speed serial input signal. In some embodiments, providing one or more first speed input signals in response to one or more second speed input signals includes providing a first speed serial input signal in response to a second speed parallel input signal.

[0049] In operation 208, method 200 provides one or more second speed output signals operating at a second speed in response to one or more first speed output signals received from one or more outputs of the BIST circuit operating at a first speed. In some embodiments, providing one or more second speed output signals in response to one or more first speed output signals includes providing a second speed serial output signal in response to a first speed parallel output signal. In some embodiments, providing one or more second speed output signals in response to one or more first speed output signals includes providing a second speed parallel output signal in response to a first speed serial output signal.

[0050] Figure 3 This is a block diagram of a test wrapper 300 according to some embodiments, which is Figure 1 An example of a test package 100 is provided, which is connected between a high-speed signal and a low-speed P1500 BIST circuit 302 (e.g., a P1500 package control block). The test package 300 includes a P1500 BIST circuit 302, a target block 304, a bonding circuit 306, and a clock generator 308, similar to the one described above. Figure 1 The BIST circuit 102, target block 104, glued connection circuit 106, and clock generator 108 are discussed. However, the P1500 BIST circuit 302 is configured for low-speed operation. In other words, the P1500 BIST circuit 302 can be used for low-speed P1500 interfaces.

[0051] The adhesive circuit 306 is configured to convert between a high-speed P1500 signal (incompatible with the low-speed P1500 BIST circuit 302) and a low-speed P1500 signal (compatible with the P1500 BIST circuit 302). The adhesive circuit 306 is configured to receive a high-speed packager clock signal 312 and provide a low-speed packager clock signal 314 to the P1500 BIST circuit 302. The adhesive circuit 306 is also configured to receive a high-speed packager selection signal 316, convert the high-speed packager selection signal 316 into a low-speed packager selection signal 330, and provide the low-speed packager selection signal 330 to the P1500 BIST circuit 302. The adhesive bonding circuit 306 is further configured to receive high-speed test interface signals 328 (e.g., high-speed packer capture signal 318, high-speed packer shift signal 320, and high-speed packer update signal 322), convert the high-speed test interface signals 328 into low-speed test interface signals 338 (e.g., low-speed packer capture signal 332, low-speed packer shift signal 334, and low-speed packer update signal 336), and provide the low-speed test interface signals 338 to the P1500 BIST circuit 302. The P1500 BIST circuit 302 is configured to provide the low-speed test interface signals 338 to the target block 304.

[0052] The glued circuit 306 is also configured to receive a high-speed serial wrapper input signal 324, (using deserializer 310) convert the high-speed serial wrapper input signal 324 into a low-speed parallel wrapper input signal 348, and provide the low-speed parallel wrapper input signal 348 to the P1500 BIST circuit 302. By a non-limiting example, the deserializer 310 may include a register 342 configured to store individual data bits obtained from the high-speed serial wrapper input signal 324 to provide data bits separately in the low-speed parallel wrapper input signal 348. The glued circuit 306 is further configured to receive a low-speed parallel wrapper output signal 350 from the P1500 BIST circuit 302 and the target block 304, (using serializer 344) convert the low-speed parallel wrapper output signal 350 into a high-speed serial wrapper output signal 326, and provide the high-speed serial wrapper output signal 326.

[0053] Clock generator 308 can be an optional component of test package 300, as previously referenced. Figure 1 The clock generator 108 is discussed. However, in embodiments where the test package 300 includes a clock generator 308, the clock generator 308 may be configured to receive a high-speed package clock signal 312, an internal reference clock signal 358, an external reference clock signal 360, or a combination thereof, and in response, generate an internal low-speed clock signal 356. By a non-limiting example, the clock generator 308 may include a clock divider configured to generate the internal low-speed clock signal 356 in response to the high-speed package clock signal 312, the internal reference clock signal 358, or the external reference clock signal 360. In some embodiments (e.g., where the test package 300 does not include a clock generator 308), an external low-speed clock signal 354 may be provided. The adhesive circuit 306 is configured to receive a low-speed clock signal 340, which includes an internal low-speed clock signal 356 (e.g., in embodiments where the test package 300 includes a clock generator 308) or an external low-speed clock signal 354 (e.g., in embodiments where the test package 300 does not include a clock generator 308). In some embodiments, the clock generator 308 includes a reference clock selector configured to select among a high-speed package clock signal 312, an internal reference clock signal 358, and an external reference clock signal 360.

[0054] As previously discussed, the adhesive circuit 306 converts between high-speed and low-speed signals, including low-speed signals such as the low-speed packer clock signal 314, the low-speed packer select signal 330, the low-speed packer capture signal 332, the low-speed packer shift signal 334, the low-speed packer update signal 336, and the low-speed parallel packer input signal 348. These low-speed signals can be gated by the low-speed clock signal 340.

[0055] In some embodiments, the glued circuit 306 may be configured to selectively operate in either a speed-switching operation mode or a bypass operation mode in response to a mode selection signal 346. In the speed-switching operation mode, the glued circuit 306 may operate as described above to switch between a high-speed signal and a low-speed signal to enable the high-speed signal to interface with the low-speed P1500 BIST circuit 302. However, in the bypass operation mode, the high-speed signal may only be passed to and from the P1500 BIST circuit 302 without any switching between high-speed and low-speed signals.

[0056] Adhesive bonding circuit 306 and P1500 BIST circuit 302 are configured to receive packager reset signal 352. In response to the assertion of packager reset signal 352, adhesive bonding circuit 306 and P1500 BIST circuit 302 are configured to reset.

[0057] It should be noted that in some embodiments, the adhesive circuit 306 may be configured to provide, in addition to providing the high-speed serial packager output signal 326, a low-speed parallel packager output signal 350 received from the P1500 BIST circuit 302.

[0058] Figure 4 yes Figure 3 The signal timing diagram for an example of the test wrapper 300 and signal 400. Also refer to... Figure 3 and Figure 4 Signal 400 includes a high-speed packer clock signal 312, a mode selection signal 346, a high-speed test interface signal 328 (high-speed packer shift signal 320, high-speed packer update signal 322 and high-speed packer capture signal 318), a high-speed serial packer input signal 324, a high-speed serial packer output signal 326, a low-speed packer clock signal 314, a low-speed test interface signal 338 (low-speed packer shift signal 334, low-speed packer update signal 336 and low-speed packer capture signal 332), a low-speed parallel packer input signal 348 and a low-speed parallel packer output signal 350.

[0059] like Figure 4As explained, the high-speed packager clock signal 312 oscillates at a higher frequency than the low-speed packager clock signal 314. Therefore, the command pulse of the low-speed test interface signal 338 has a longer time width than the command pulse of the high-speed test interface signal 328. By way of a non-limiting example, the low-speed shift command pulse 416 of the low-speed packager shift signal 334 has a longer time width than its corresponding high-speed shift command pulse 402 of the high-speed packager shift signal 320. As another non-limiting example, the low-speed update command pulse 418 of the low-speed packager update signal 336 has a longer time width than its corresponding high-speed update command pulse 404 of the high-speed packager update signal 322. As another non-limiting example, the low-speed capture command pulse 420 of the low-speed packager capture signal 332 has a longer time width than its corresponding high-speed capture command pulse 406 of the high-speed packager capture signal 318.

[0060] Figure 4 It also describes the low-speed parallel input data 422 of the low-speed parallel input signal 348 corresponding to the high-speed serial input data 414 of the high-speed serial packager input signal 324. Figure 4 Further explanation is provided on the first low-speed parallel output data 424, the second low-speed parallel output data 426, and the third low-speed parallel output data 428 of the low-speed parallel packager output signal 350, which respectively correspond to the first high-speed serial output data 408, the second high-speed serial output data 410, and the third high-speed serial output data 412 of the high-speed serial packager output signal 326.

[0061] Figure 5 This is a block diagram of a test wrapper 500 according to some embodiments, which is Figure 1 An example of a test wrapper 100 is provided, and it is connected between a low-speed signal and a high-speed P1500 BIST circuit 502 (e.g., a high-speed P1500 wrapper control block). The test wrapper 500 includes components similar to... Figure 1 The P1500 BIST circuit 502, target block 504, glued circuit 506, and optionally clock generator 508 comprise the BIST circuit 102, target block 504, glued circuit 506, and clock generator 108. However, the P1500 BIST circuit 502 is configured for high-speed operation. In other words, the P1500 BIST circuit 502 can be used for a high-speed P1500 interface.

[0062] The adhesive circuit 506 is configured to convert between a low-speed P1500 signal (which is incompatible with the high-speed P1500 BIST circuit 502) and a high-speed P1500 signal (which is compatible with the P1500 BIST circuit 502). The adhesive circuit 506 is configured to receive a low-speed packer clock signal 512 and provide a high-speed packer clock signal 514 to the P1500 BIST circuit 502. The adhesive circuit 506 is also configured to receive a low-speed packer selection signal 516, convert the low-speed packer selection signal 516 into a high-speed packer selection signal 530, and provide the high-speed packer selection signal 530 to the P1500 BIST circuit 502. The adhesive bonding circuit 506 is further configured to receive low-speed test interface signals 528 (e.g., low-speed packer capture signal 518, low-speed packer shift signal 520, and low-speed packer update signal 522), convert the low-speed test interface signals 528 into high-speed test interface signals 538 (e.g., high-speed packer capture signal 532, high-speed packer shift signal 534, and high-speed packer update signal 536), and provide the high-speed test interface signals 538 to the P1500 BIST circuit 502. The P1500 BIST circuit 502 is configured to provide the high-speed test interface signals 538 (Sft / CapIR(DR)) to the target block 504.

[0063] The glued circuit 506 is also configured to receive a low-speed parallel wrapper input signal 524, (using serializer 510) convert the low-speed parallel wrapper input signal 524 into a high-speed serial wrapper input signal 560, and provide the high-speed serial wrapper input signal 560 to the P1500 BIST circuit 502. The glued circuit 506 is further configured to receive a high-speed serial wrapper output signal 526 from the P1500 BIST circuit 502 and the target block 504, (using deserializer 544) convert the high-speed serial wrapper output signal 526 into a low-speed parallel wrapper output signal 546, and provide the low-speed parallel wrapper output signal 546. By a non-limiting example, the deserializer 544 may include a register 542 configured to store individual data bits of the high-speed serial wrapper output signal 526 to separate the bits into parallel channels of the low-speed parallel wrapper output signal 546. The bidirectional low-speed parallel input / output signal 562, which includes the low-speed parallel packer input signal 524 and the low-speed parallel packer output signal 546, can therefore be exchanged via the adhesive circuit 506.

[0064] Clock generator 508 can be an optional component of test package 500, as previously referenced. Figure 1The clock generator 108 is discussed. However, in embodiments where the test package 500 includes a clock generator 508, the clock generator 508 may be configured to receive a low-speed package clock signal 512, an internal reference clock signal 556, an external reference clock signal 558, or a combination thereof, and in response, generate an internal high-speed clock signal 554. By a non-limiting example, the clock generator 508 may include a clock counter configured to generate the internal high-speed clock signal 554 in response to the low-speed package clock signal 512, the internal reference clock signal 556, or the external reference clock signal 558. In some embodiments (e.g., where the test package 500 does not include a clock generator 508), an external high-speed clock signal 552 may be provided. The adhesive circuit 506 is configured to receive a high-speed clock signal 540, which includes an internal high-speed clock signal 554 (e.g., in an embodiment where the test package 500 includes a clock generator 508) or an external high-speed clock signal 552 (e.g., in an embodiment where the test package 500 does not include a clock generator 508). In some embodiments, the clock generator 508 includes a reference clock selector configured to select among a low-speed package clock signal 512, an internal reference clock signal 556, and an external reference clock signal 558.

[0065] As previously discussed, the adhesive circuit 506 converts between low-speed signals and high-speed signals (e.g., high-speed packer clock signal 514, high-speed packer select signal 530, high-speed packer capture signal 532, high-speed packer shift signal 534, high-speed packer update signal 536, and high-speed serial packer input signal 560). These high-speed signals can be gated by the high-speed clock signal 540.

[0066] The glued circuit 506 can be configured to provide a high-speed enable signal 564 and a command disable signal 566 to the P1500BIST circuit 502. The P1500BIST circuit 502 can be configured to selectively operate in either a low-speed operating mode or a high-speed operating mode in response to the high-speed enable signal 564 provided by the glued circuit 506. By a non-limiting example, the P1500BIST circuit 502 can be configured to operate in a high-speed operating mode when the high-speed enable signal 564 is asserted to a logic level high voltage potential and in a low-speed operating mode when the high-speed enable signal 564 is deasserted to a logic level low voltage potential. The P1500BIST circuit 502 can be configured to respond to an assertion cutoff signal of the command disable signal 566 for faster operation.

[0067] Similar to Figure 3The adhesive bonding circuit 306 and P1500 BIST circuit 302 are configured to receive the packager reset signal 550 and reset in response to the assertion of the packager reset signal 550.

[0068] In some embodiments, the glued circuit 506 may be configured to selectively operate in either a speed-switching operation mode or a bypass operation mode in response to a mode selection signal 548. In the speed-switching operation mode, the glued circuit 506 may operate as described above to switch between low-speed and high-speed signals to enable the low-speed signal to interface with the high-speed P1500 BIST circuit 502. However, in the bypass operation mode, the high-speed signal may only be transmitted to and from the P1500 BIST circuit 502 without any switching between low-speed and high-speed signals.

[0069] Figure 6 yes Figure 5 The signal timing diagram for an example of the 500 signal packager 600 is shown below. Also refer to... Figure 5 and Figure 6 Signal 600 includes a low-speed packer clock signal 312, a low-speed test interface signal 528 (a low-speed packer shift signal 520, a low-speed packer update signal 522, and a low-speed packer capture signal 518), a high-speed enable signal 564, a low-speed parallel input / output signal 562, a high-speed packer clock signal 514, a high-speed test interface signal 538 (a high-speed packer shift signal 534, a high-speed packer update signal 536, and a high-speed packer capture signal 532), a high-speed serial packer input signal 560, a high-speed serial packer output signal 526, and a low-speed parallel packer output signal 546.

[0070] like Figure 6 As explained, the low-speed packager clock signal 512 oscillates at a lower frequency than the high-speed packager clock signal 514. Therefore, the command pulse of the low-speed test interface signal 528 has a longer time width than the command pulse of the high-speed test interface signal 538. By way of a non-limiting example, the low-speed shift command pulse 602 of the low-speed packager shift signal 520 has a longer time width than its corresponding high-speed shift command pulse 616 of the high-speed packager shift signal 534. As another non-limiting example, the low-speed update command pulse 604 of the low-speed packager update signal 522 has a longer time width than its corresponding high-speed update command pulse 618 of the high-speed packager update signal 536. As another non-limiting example, the low-speed capture command pulse 606 of the low-speed packager capture signal 518 has a longer time width than its corresponding high-speed capture command pulse 620 of the high-speed packager capture signal 532.

[0071] Figure 6It also describes the high-speed serial input data 622 of the high-speed serial wrapper input signal 560 corresponding to the low-speed parallel input data 608 of the low-speed parallel input / output signal 562. Figure 6 Further explanation is provided on the first high-speed serial output data 624, the second high-speed serial output data 626, and the third high-speed serial output data 628 of the high-speed serial packager output signal 526, which respectively correspond to the first low-speed parallel output data 610, the second low-speed parallel output data 612, and the third low-speed parallel output data 614 of the low-speed parallel input / output signal 562 and the low-speed parallel packager output signal 546.

[0072] Figure 7 yes Figure 5 The signal timing diagrams for other instances of the test wrapper 500 and 700 are also provided. See also... Figure 5 and Figure 7 Signal 700 includes a low-speed packer clock signal 512, a low-speed test interface signal 528 (low-speed packer shift signal 520, low-speed packer update signal 522 and low-speed packer capture signal 518), a command deactivation signal 566, a low-speed parallel input / output signal 562, a high-speed packer clock signal 514, a high-speed test interface signal 538 (high-speed packer shift signal 534, high-speed packer update signal 536 and high-speed packer capture signal 532), a high-speed serial packer input signal 560, a high-speed serial packer output signal 526 and a low-speed parallel packer output signal 546.

[0073] Similar to Figure 6 The command pulse of the low-speed packer shift signal 520 described in the text, Figure 7 The low-speed packer shift signal 520 described herein has a longer time width than the command pulse of the high-speed test interface signal 538. By way of a non-limiting example, the low-speed shift command pulse 702 of the low-speed packer shift signal 520 has a longer time width than its corresponding high-speed shift command pulse 716 of the high-speed packer shift signal 534. As another non-limiting example, the low-speed update command pulse 704 of the low-speed packer update signal 522 has a longer time width than its corresponding high-speed update command pulse 718 of the high-speed packer update signal 536. As another non-limiting example, the low-speed capture command pulse 706 of the low-speed packer capture signal 518 has a longer time width than its corresponding high-speed capture command pulse 720 of the high-speed packer capture signal 532.

[0074] Figure 7 It also describes the high-speed serial input data 722 of the high-speed serial wrapper input signal 560 corresponding to the low-speed parallel input data 708 of the low-speed parallel input / output signal 562. Figure 7Further explanation is provided on the first high-speed serial output data 724, the second high-speed serial output data 726, and the third high-speed serial output data 728 of the high-speed serial packager output signal 526, which respectively correspond to the first low-speed parallel output data 710, the second low-speed parallel output data 712, and the third low-speed parallel output data 714 of the low-speed parallel input / output signal 562 and the low-speed parallel packager output signal 546.

[0075] Figure 8 This is a block diagram of an HBM+ system 800 according to some embodiments. The HBM+ system 800 includes an HBM 804 and processing units 806 (e.g., a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), etc.) operatively coupled to the HBM 804. The HBM 804 includes a dynamic random access memory die, a DRAM die 808, and a logic die 802. The logic die 802 includes control circuitry 810 and a near-memory controller (NMC) 812. The processing unit 806 includes a far-memory controller (FMC) 814.

[0076] NMC 812 and FMC 814 are configured to function as the master memory controller. FMC 814 includes an HBM external memory controller, and NMC 812 includes an HBM on-memory controller located on a logic die 802 of HBM 804. By way of non-limiting example, logic die 802 may correspond to the bottom layer of a 3D stacked memory as HBM 804, while DRAM die 808 may correspond to one of the upper layers of HBM 804. Logic die 802 can control DRAM die 808 using NMC 812, which can be instructed by control circuitry 810 to control DRAM die 808. It should be noted that either or both of NMC 812 and FMC 814 may be represented by a general-purpose memory controller.

[0077] The logic die 802 includes a P1500 test wrapper 820, which includes a P1500 interface 816 operatively coupled to a P1500 control circuitry 818. The P1500 test wrapper 820 is configured to test the logic die 802. For example, the P1500 interface 816 may include glued circuitry according to embodiments disclosed herein (e.g., Figure 1 106. Adhesive-bonded circuit Figure 3 306 adhesive-bonded circuit Figure 5 The adhesive bonding circuit 506), and the P1500 control circuit 818 may include a P1500BIST circuit (e.g., according to embodiments disclosed herein) Figure 1 BIST circuit 102, Figure 3 P1500 BIST circuit 302, Figure 5The P1500 BIST circuit 502).

[0078] Figure 9 This is a block diagram of an integrated circuit device 900 according to some embodiments. The integrated circuit device 900 includes a core circuit system 902 (e.g., a logic die of HBM) and a test package 100 configured to test the core circuit system 902.

[0079] Figure 10 This is a block diagram of a computing system 1000 according to some embodiments. The computing system 1000 includes one or more processors 1004 operatively coupled to one or more memory devices 1002, one or more non-volatile data storage devices 1010, one or more input devices 1006, and one or more output devices 1008. In some embodiments, the computing system 1000 includes a personal computer (PC), such as a desktop computer, laptop computer, tablet computer, mobile computer (e.g., smartphone, personal digital assistant (PDA), etc.), web server, or other computer device.

[0080] In some embodiments, one or more processors 1004 may include a central processing unit (CPU) or other processors configured to control the computing system 1000. In some embodiments, one or more memory devices 1002 include random access memory (RAM), such as volatile data storage devices (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, one or more non-volatile data storage devices 1010 include hard drives, solid-state drives, flash memory, erasable programmable read-only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments, one or more input devices 1006 include a keyboard 1014, pointing devices 1018 (e.g., mouse, tracking pad, etc.), a microphone 1012, a keypad 1016, a scanner 1020, a camera 1028, other input devices, or any combination thereof. In some embodiments, an output device 1008 includes an electronic display 1022, a speaker 1026, a printer 1024, other output devices, or any combination thereof.

[0081] In some embodiments, one or more memory devices 1002 include a test wrapper according to embodiments disclosed herein (e.g., Figure 1 Test packaging 100 Figure 3 Test packaging 300, Figure 5 The test wrapper 500). By way of non-limiting examples, one or more memory devices 1002 may include BIST circuitry configured to operate at a first speed (e.g., the test wrapper 500). Figure 1 BIST circuit 102, Figure 3P1500 BIST circuit 302, Figure 5 The P1500 BIST circuit 502). One or more memory devices 1002 may also include adhesive circuitry (e.g., the P1500 BIST circuit 502) configured to switch between a second speed signal operating at a second speed different from the first speed and a first speed signal compatible with the operation of the BIST circuitry. Figure 1 106. Adhesive-bonded circuit Figure 3 306 adhesive-bonded circuit Figure 5 (506) Adhesive-bonded circuit.

[0082] As used in this disclosure, the terms "module" or "component" may refer to a specific hardware implementation of a software object or software routine configured to perform the actions of a module or component and / or executable on and / or by general-purpose hardware (e.g., computer-readable media, processing devices, etc.) of a computing system. In some embodiments, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on a computing system (e.g., as separate threads). While some systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific software implementations are also possible and contemplated.

[0083] As used in this disclosure, the term "combination" relating to multiple elements may include any combination of all elements or any of a variety of different sub-combinations of some elements. For example, the phrase "A, B, C, D or a combination thereof" may refer to: any one of A, B, C or D; a combination of each of A, B, C and D; and any sub-combination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0084] The terms used in this disclosure and especially in the appended claims (e.g., the body of the appended claims) are generally intended to be “open” terms (e.g., the term “including” should be interpreted as “including (but not limited to)”, the term “having” should be interpreted as “at least having”, the term “includes” should be interpreted as “including (but not limited to)”, etc.).

[0085] Furthermore, if a specific number of introduced claim statements are desired, this intent must be explicitly stated in the claims; otherwise, the intent does not exist. For example, to aid understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article “a / an” limits any particular claim containing such an introductory claim statement to only one embodiment of that statement, even if the same claim contains the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements.

[0086] Furthermore, even if a specific number of claims are explicitly stated, those skilled in the art will recognize that this statement should be interpreted as meaning at least a certain number of claims (e.g., a bare statement of "two claims" without other modifiers means at least two claims or two or more claims). Moreover, in those examples where conventions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, this construction generally intends to include only A, only B, only C, A and B simultaneously, A and C simultaneously, B and C simultaneously, or A, B, and C simultaneously, etc.

[0087] Furthermore, any extractive word or phrase presenting two or more alternatives, whether in the specification, claims, or drawings, should be understood to include the possibility of one, any, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0088] While this disclosure has been described herein with reference to specific embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Indeed, many additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed by the appended claims and their legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being covered within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus comprising: A built-in self-test (BIST) circuit is used in the core circuit system of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. The BIST circuit is configured to operate at a first speed. A bonding circuit configured to interface with the test interface, one or more inputs, and one or more outputs of the BIST circuit, the bonding circuit being configured to switch between a second speed test interface signal and a second speed input / output signal operating at a second speed and a first speed test interface signal and a first speed input / output signal operating at a first speed, the second speed being different from the first speed.

2. The device according to claim 1, wherein the first speed is slower than the second speed.

3. The device of claim 2, wherein the adhesive circuit includes a deserializer configured to convert a second speed serial input signal into a first speed parallel input signal and provide the first speed parallel input signal to the one or more inputs of the BIST circuit.

4. The device of claim 2, wherein the adhesive circuit includes a serializer configured to convert a first speed parallel output signal received from one or more outputs of the BIST circuit into a second speed serial output signal.

5. The device according to claim 1, wherein the first speed is faster than the second speed.

6. The device of claim 5, wherein the adhesive circuitry includes a serializer configured to convert a second speed parallel input signal into a first speed serial input signal and to provide the first speed serial input signal to the one or more inputs of the BIST circuitry.

7. The device of claim 5, wherein the adhesive circuit includes a deserializer configured to convert a first speed serial output signal received from one or more outputs of the BIST circuit into a second speed parallel output signal.

8. The device of claim 1, wherein the adhesive circuitry is configured to provide a first speed packer clock, configured to operate at the first speed, to the BIST circuitry.

9. An apparatus comprising: A built-in self-test BIST circuit is used in the core circuit system of an integrated circuit device. The BIST circuit includes a test interface, one or more inputs, and one or more outputs. A glued circuit electrically connected to the test interface, one or more inputs, and one or more outputs of the BIST circuit, the glued circuit being configured to switch between a second speed test interface signal and a second speed input / output signal operating at a second speed and a first speed test interface signal and a first speed input / output signal operating at a first speed, the second speed being different from the first speed; and A clock generator configured to provide a first speed clock signal operating at the first speed to the adhesive circuit.

10. The device of claim 9, further comprising the core circuitry, wherein the BIST circuitry is configured to enable testing of the core circuitry.

11. The device of claim 10, wherein the core circuit system comprises a circuit system for a logic die for a high-bandwidth memory device.

12. The apparatus of claim 9, wherein the clock generator is configured to provide the first speed clock signal in response to a reference clock signal.

13. The device of claim 9, wherein the adhesive bonding circuit comprises: A deserializer electrically connected to the one or more inputs, the deserializer being configured to provide a first-speed parallel input signal to the one or more inputs in response to a second-speed serial input signal; and A serializer electrically connected to the one or more outputs, the serializer being configured to provide a second speed serial output signal in response to a first speed parallel output signal received from the one or more outputs.

14. The device of claim 9, wherein the adhesive circuit comprises: A serializer electrically connected to the one or more inputs, the serializer being configured to provide a first-speed serial input signal to the one or more inputs in response to a second-speed parallel input signal; and A deserializer electrically connected to the one or more outputs, the deserializer being configured to provide a second speed parallel output signal in response to a first speed serial output signal received from the one or more outputs.

15. The device of claim 9, wherein the BIST circuitry includes a P1500 test packager control block.

16. The apparatus of claim 9, wherein the clock generator is configured to provide the first speed clock signal and receive a second speed wrapper clock signal operating according to the second speed.

17. A method for interfacing with a built-in self-test (BIST) circuit, the method comprising: A first speed wrapper clock signal is provided to the BIST circuit, and the first speed wrapper clock signal operates according to the first speed; In response to a second speed test interface signal operating at a second speed, a first speed test interface signal operating at a first speed is provided to the test interface of the BIST circuit, wherein the second speed is different from the first speed; In response to one or more second speed input signals operating at the second speed, one or more first speed input signals operating at the first speed are provided to one or more inputs of the BIST circuit; and In response to one or more first speed output signals operated at the first speed received from one or more outputs of the BIST circuit, one or more second speed output signals operated at the second speed are provided.

18. The method of claim 17, wherein providing the first speed test interface signal includes providing the first speed selection, capture, shift, and update package signal in response to a second speed selection, capture, shift, and update package signal.

19. The method of claim 17, wherein: Providing the one or more first speed input signals in response to the one or more second speed input signals includes providing a first speed parallel input signal in response to a second speed serial input signal; and Providing one or more second speed output signals in response to one or more first speed output signals includes providing a second speed serial output signal in response to a first speed parallel output signal.

20. The method of claim 17, wherein: Providing the one or more first speed input signals in response to the one or more second speed input signals includes providing a first speed serial input signal in response to a second speed parallel input signal; and Providing one or more second speed output signals in response to one or more first speed output signals includes providing second speed parallel output signals in response to first speed serial output signals.

21. An apparatus comprising: A circuit comprising one or more inputs and one or more outputs, the circuit being configured to operate at a first speed, the one or more inputs being configured to receive one or more first speed input signals, and the one or more outputs being configured to provide one or more first speed output signals; and A bonding circuit configured to interface with one or more inputs and one or more outputs of the circuit, the bonding circuit being configured to switch between one or more second speed input signals operating at a second speed and one or more first speed input signals operating at a first speed, the bonding circuit being further configured to switch between one or more second speed output signals operating at a second speed and one or more first speed output signals operating at a first speed, the second speed being different from the first speed.

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