Chip testing system and control method of chip testing system

Abstract

This application proposes a chip testing system and a control method for the chip testing system. Among them, the chip testing system includes: a chip and a tester. Among them, the chip includes a controller, pins, a data selector, and a test register; the controller is configured to receive a mode switching instruction sent by the tester and control the data selector to switch to the test mode according to the mode switching instruction; the data selector is configured to control the first input terminal of the data selector and the output terminal of the data selector to conduct when the data selector switches to the test mode; the controller is further configured to receive a test instruction sent by the tester and control the test register to output a test value; the tester is configured to collect the voltage output from the second end of the pin and generate a test result for the first end of the pin according to the voltage and the test instruction. Thus, it is possible to test the pins of the chip and introduce test logic during the chip design stage, improving the test speed and test accuracy rate.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to a chip test system and a control method for a chip test system. Background Art

[0002] The pins of a chip are devices for connecting the chip to the outside, used for input and output of data. Among them, input and output refer to input low level, input high level, output low level, and output high level. The judgment of high and low levels has certain standards. Those lower than a specific level value (for example: 0.3V) can be considered as low level; those higher than a specific level value (for example: 1.5V) can be considered as high level.

[0003] Due to the large number of pins of the chip, each pin is used for communication between the inside and the outside of the chip, and the reliability of the pins is particularly important. Related test technologies cannot be unified with the functional design process, and the test process takes a long time and is not intuitive. Summary of the Invention

[0004] Embodiments of this application provide a chip test system and a control method for a chip test system, which can test the pins of a chip and introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0005] A first aspect embodiment of this application proposes a chip test system, including a chip and a tester. The chip is connected to the tester. Among them, the chip includes a controller, pins, a data selector, and a test register. The controller is respectively connected to the control end of the data selector and the control end of the test register. The first input end of the data selector is connected to the output end of the test register. The output end of the data selector is connected to the first end of the pin. The second end of the pin is connected to the tester. The controller is configured to receive a mode switching instruction sent by the tester and control the data selector to switch to the test mode according to the mode switching instruction. The data selector is configured to control the first input end and the output end of the data selector to conduct when the data selector switches to the test mode. The controller is further configured to receive a test instruction sent by the tester and control the test register to output a test value. The tester is configured to collect the voltage output from the second end of the pin and generate a test result of the first end of the pin according to the voltage and the test instruction.

[0006] The chip testing system according to the embodiment of the present application generates a test result by a tester based on the output voltage and the test value of the chip pins, so that the pins of the chip can be tested by verifying the output voltage of the chip pins, and test logic can be introduced in the chip design stage, improving the test speed and test accuracy.

[0007] In addition, the chip testing system according to the above embodiment of the present application may further have the following additional technical features:

[0008] In an embodiment of the present application, the test instruction includes the test value, and the tester is specifically configured to: collect the voltage output from the second end of the pin, and generate the test result according to the voltage and the test value, where the test value is 0 or 1.

[0009] In an embodiment of the present application, the chip further includes a functional path, the functional path is connected to the second input end of the data selector, and the data selector is further configured to: when the data selector switches to the test mode, control the second input end of the data selector to be closed.

[0010] In an embodiment of the present application, the data selector is further configured to: when the chip is powered on, control the second input end and the output end of the data selector to be conducted, and control the first input end of the data selector to be closed.

[0011] Another chip testing system according to the second aspect embodiment of the present application includes a chip and a tester, the chip is connected to the tester, where the chip includes a controller, pins and a read-only register, where the controller is connected to the control end of the read-only register, the first end of the pin is connected to the input end of the read-only register, and the second end of the pin is connected to the tester; the tester is configured to provide a voltage for the second end of the pin; the read-only register is configured to read the test value corresponding to the voltage output from the first end of the pin and send the test value to the controller; the controller is configured to forward the test value to the tester; the tester is further configured to generate a test result of the second end of the pin according to the voltage and the test value.

[0012] The chip testing system according to the embodiment of the present application generates a test result by a tester according to the input voltage and the test value of the pin, so that the pins of the chip can be tested by verifying the input voltage of the chip pins, and test logic can be introduced in the chip design stage, improving the test speed and test accuracy.

[0013] In addition, the chip testing system according to the above embodiment of the present application may further have the following additional technical features:

[0014] In one embodiment of the present application, the test value is 0 or 1.

[0015] A control method for a chip test system according to a third aspect embodiment of the present application includes: receiving a mode switching instruction sent by the tester, and controlling the data selector to switch to the test mode according to the mode switching instruction; when the data selector switches to the test mode, controlling the first input terminal of the data selector to be conducted with the output terminal of the data selector; receiving a test instruction sent by the tester, and controlling the test register to output a test value according to the test instruction; collecting the voltage output from the second terminal of the pin, and generating a test result for the first terminal of the pin according to the voltage and the test instruction.

[0016] The control method of the chip test system according to the embodiment of the present application receives a mode switching instruction sent by the tester, controls the data selector to switch to the test mode according to the mode switching instruction, then when the data selector switches to the test mode, controls the first input terminal of the data selector to be conducted with the output terminal of the data selector, receives a test instruction sent by the tester, controls the test register to output a test value according to the test instruction, collects the voltage output from the second terminal of the pin, and generates a test result for the first terminal of the pin according to the voltage and the test instruction, so that the pins of the chip can be tested by verifying the output voltage of the chip pins, and test logic can be introduced in the chip design stage, improving the test speed and test accuracy.

[0017] In addition, the control method of the chip test system according to the above embodiment of the present application may further have the following additional technical features:

[0018] In one embodiment of the present application, the test instruction includes the test value, and the collecting the voltage output from the second terminal of the pin, and generating a test result for the first terminal of the pin according to the voltage and the test instruction includes: collecting the voltage output from the second terminal of the pin, and generating the test result according to the voltage and the test value, where the test value is 0 or 1.

[0019] A control method for a chip test system according to a fourth aspect embodiment of the present application includes: providing a voltage for the second terminal of the pin; reading a test value corresponding to the voltage output from the first terminal of the pin, and sending the test value to the controller; forwarding the test value to the tester; generating a test result for the second terminal of the pin according to the voltage and the test value.

[0020] According to the control method of the chip testing system according to the embodiments of the present application, first, a voltage is provided to the second end of the pin, then the test value corresponding to the voltage output from the first end of the pin is read, and the test value is sent to the controller, and the test value is forwarded to the testing machine, and according to the voltage and the test value, a test result of the second end of the pin is generated, so that the pins of the chip can be tested by verifying the input voltage of the chip pins, and the test logic can be introduced in the chip design stage, improving the test speed and test accuracy.

[0021] In addition, the control method of the chip testing system according to the above embodiments of the present application may further have the following additional technical features:

[0022] In an embodiment of the present application, the test value is 0 or 1.

[0023] The additional aspects and advantages of the present application will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, wherein:

[0025] Figure 1 FIG. is a schematic structural diagram of a chip testing system according to an embodiment of the present application;

[0026] Figure 2 FIG. is a schematic structural diagram of a chip testing system according to another embodiment of the present application;

[0027] Figure 3 FIG. is a schematic structural diagram of a chip testing system according to another embodiment of the present application;

[0028] Figure 4 FIG. is a schematic flowchart of a chip testing method according to an embodiment of the present application; and

[0029] Figure 5 FIG. is a schematic flowchart of a chip testing method according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain the present application and should not be construed as limiting the present application.

[0031] The chip testing system and the control method of the chip testing system according to the embodiments of the present application will be described below with reference to the drawings.

[0032] Figure 1 Schematic diagram of the structure of a chip testing system according to an embodiment of the present application.

[0033] As Figure 1 shown, the chip testing system 100 according to the embodiment of the present application may include: a chip 110 and a tester 120, and the chip 110 and the tester 120 are connected. Among them, the chip 110 may include a controller 111, pins 112, a data selector 113, and a test register 114. Among them, the controller 111 is respectively connected to the control end of the data selector 113 and the control end of the test register 114. The first input end of the data selector 113 is connected to the output end of the test register 114. The output end of the data selector 113 is connected to the first end of the pin 112, and the second end of the pin 112 is connected to the tester 120.

[0034] Among them, the controller 111 is configured to receive a mode switching instruction sent by the tester 120, and control the data selector 113 to switch to the test mode according to the mode switching instruction. Among them, the mode of the data selector 113 may include a working mode, a test mode, etc., and the tester 120 may be an Automatic Test Equipment (ATE).

[0035] In the embodiment of the present application, the tester 120 may send a mode switching instruction to the controller through a related protocol.

[0036] Specifically, when the chip testing system 100 tests the chip 110, the tester 120 may send a mode switching instruction to the controller 111. After receiving the mode switching instruction, the controller 111 may control the data selector 113 to switch the current mode to the test mode.

[0037] The data selector 113 is configured to control the first input end and the output end of the data selector 113 to conduct when the data selector 113 switches to the test mode.

[0038] Specifically, when the data selector 113 is not in the test mode, the first input end of the data selector 113 is in a closed state. When the data selector 113 switches to the test mode, it controls the first input end and the output end of the data selector 113 to conduct.

[0039] The controller 111 is further configured to receive a test instruction sent by the tester 120, and control the test register 114 to output a test value according to the test instruction.

[0040] In the embodiment of the present application, the tester 120 may send a test instruction to the controller 111 through a related protocol.

[0041] Specifically, after the data selector 113 switches to the test mode, the tester 120 can send a test instruction to the controller 111 through a relevant protocol. After receiving the test instruction, the controller 111 controls the test register 114 to output a test value according to the test instruction.

[0042] The tester 120 is configured to collect the voltage output from the second end of the pin 112, and generate a test result for the first end of the pin 112 according to the voltage and the test instruction.

[0043] To clearly illustrate the previous embodiment, in an embodiment of the present application, the test instruction may include a test value. The tester 120 is specifically configured to collect the voltage output from the second end of the pin 112, and generate a test result according to the voltage and the test value, where the test value is 0 or 1.

[0044] Wherein, the voltage may include a high voltage and a low voltage. The high voltage may be a voltage higher than a specific voltage value (for example, 1.5V), and the low voltage may be a voltage lower than the specific voltage value (for example, 0.3V).

[0045] In the embodiment of the present application, when the chip testing system 100 tests the chip 110, it can generate a test result according to the voltage output from the second end of the pin 112 collected by the tester 120 and the test value output by the test register 114.

[0046] Specifically, if the test value output by the test register 114 is 0, the voltage output from the second end of the pin 112 collected by the tester 120 is a low voltage, and if the test value output by the test register 114 is 1, the voltage output from the second end of the pin 112 collected by the tester 120 is a high voltage, it can be indicated that the pin 112 can work normally. Otherwise, it can be indicated that the pin 112 cannot work normally.

[0047] The chip testing system according to the embodiment of the present application can generate a test result by the tester according to the output voltage and the test value of the chip pin, so as to be able to test the chip pin by verifying the output voltage of the chip pin, and can introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0048] In an embodiment of the present application, as Figure 2 shown, the chip 110 may further include a functional path 115. The functional path 115 is connected to the second input terminal of the data selector 113. The data selector 113 is further configured to control the second input terminal of the data selector 113 to be closed when the data selector 113 switches to the test mode. Wherein, the functional path 115 may be a functional circuit inside the chip 110 for transmitting functional signals when the chip 110 works normally.

[0049] In an embodiment of the present application, when the data selector 113 is not in the test mode, the second input terminal of the data selector 113 is turned on, the first input terminal is turned off, and the data selector 113 can receive and output the signal transmitted by the functional path 115, and does not receive the signal transmitted by the test register 114; when the data selector 113 switches to the test mode, the controller 111 can control the second input terminal of the data selector 113 to be turned off, not receive the signal transmitted by the functional path 115, and can control the first input terminal of the data selector 113 to be turned on to receive and output the signal (i.e., the test value) transmitted by the test register 114, so as to test the chip 110.

[0050] In an embodiment of the present application, the data selector 113 is further configured to control the second input terminal and the output terminal of the data selector 113 to be turned on, and control the first input terminal of the data selector 113 to be turned off when the chip 110 is powered on.

[0051] Specifically, when the chip 110 is powered on, the chip 110 can be initialized, and the controller 111 is used to control the second input terminal and the output terminal of the data selector 113 to be turned on, and control the first input terminal of the data selector 113 to be turned off, so that the control selector exits the test mode and returns to the initial state.

[0052] Figure 3 FIG. is a schematic structural diagram of a chip test system according to another embodiment of the present application.

[0053] As Figure 3 shown, the chip test system 300 of the embodiment of the present application may include a chip 310 and a tester 320, and the chip 310 and the tester 320 are connected. Among them, the chip 310 may include a controller 311, a pin 312, and a read-only register 313. Among them, the controller 311 is connected to the control terminal of the read-only register 313, the first end of the pin 312 is connected to the input terminal of the read-only register 313, and the second end of the pin 312 is connected to the tester 320. Among them, the tester 320 may be an ATE.

[0054] The tester 320 is configured to provide a voltage for the second end of the pin 312.

[0055] Among them, the voltage may include a high voltage and a low voltage. The high voltage may be a voltage higher than a specific voltage value (for example, 1.5V), and the low voltage may be a voltage lower than a specific voltage value (for example, 0.3V).

[0056] Specifically, when the chip test system 300 tests the chip 310, the tester 320 can provide a high voltage or a low voltage for the second end of the pin 312.

[0057] The read-only register 313 is used to read the test value corresponding to the voltage output at the first end of the pin 312 and send the test value to the controller 311. The test value can be 0 or 1.

[0058] In the embodiment of the present application, the test value corresponding to the high voltage is 1, and the test value corresponding to the low voltage is 0. When the voltage output at the first end of the pin 312 is a high voltage, the test value read by the read-only memory 313 is 1. When the voltage output at the first end of the pin 312 is a low voltage, the test value read by the read-only memory 313 is 0.

[0059] Specifically, after the testing machine 320 provides a high voltage or a low voltage to the second end of the pin 312, the read-only register 313 can read the test value corresponding to the voltage output at the first end of the pin 312 and send the test value to the controller 311.

[0060] The controller 311 is used to forward the test value to the testing machine 320.

[0061] Specifically, after the controller 311 receives the test value sent by the read-only register 313, it can forward the test value to the testing machine 320.

[0062] The testing machine 320 is further used to generate a test result for the second end of the pin 312 according to the voltage and the test value.

[0063] In the embodiment of the present application, after the testing machine 320 receives the test value forwarded by the controller 111, it can generate a test result for the second end of the pin 312 according to the test value and the voltage provided by the testing machine 320 for the second end of the pin 312.

[0064] Specifically, if the voltage provided by the testing machine 320 for the second end of the pin 312 is a high voltage, the test value received by the testing machine 320 from the controller 111 is 1, and if the voltage provided by the testing machine 320 for the second end of the pin 312 is a low voltage, the test value received by the testing machine 320 from the controller 111 is 0, it indicates that the pin 312 can work properly. Otherwise, it indicates that the pin 312 cannot work properly.

[0065] The chip testing system in the embodiment of the present application can generate a test result by the testing machine according to the input voltage and the test value of the pin, so as to test the chip pin by verifying the input voltage of the chip pin, and can introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0066] Figure 4 It is a schematic flowchart of the control method of the chip testing system according to an embodiment of the present application.

[0067] The control method of the chip testing system according to the embodiments of the present application can be executed by the chip testing system provided by the embodiments of the first aspect of the present application to receive a mode switching instruction sent by a tester, control a data selector to switch to a test mode according to the mode switching instruction, and then when the data selector switches to the test mode, control the first input terminal of the data selector to be conducted with the output terminal of the data selector, receive a test instruction sent by the tester, control a test register to output a test value according to the test instruction, collect the voltage output from the second terminal of a pin, and generate a test result of the first terminal of the pin according to the voltage and the test instruction, so that the pins of the chip can be tested by verifying the output voltage of the chip pins, and test logic can be introduced in the chip design stage, improving the test speed and test accuracy.

[0068] As Figure 4 shown, the control method of the chip testing system may include the following steps:

[0069] Step 401: Receive a mode switching instruction sent by a tester, and control a data selector to switch to a test mode according to the mode switching instruction. Among them, the modes of the data selector may include a working mode and a test mode, etc., and the tester may be an ATE.

[0070] In the embodiments of the present application, the tester may send a mode switching instruction to the controller through a relevant protocol.

[0071] Specifically, when the chip testing system tests a chip, the tester may send a mode switching instruction to the controller. After receiving the mode switching instruction, the controller may control the data selector to switch the current mode to the test mode according to the mode switching instruction.

[0072] Step 402: When the data selector switches to the test mode, control the first input terminal of the data selector to be conducted with the output terminal of the data selector.

[0073] Specifically, when the data selector is not in the test mode, the first input terminal of the data selector and the output terminal of the data selector are in a closed state. When the data selector switches to the test mode, control the first input terminal of the data selector to be conducted with the output terminal of the data selector.

[0074] Step 403: Receive a test instruction sent by a tester, and control a test register to output a test value according to the test instruction.

[0075] In the embodiments of the present application, the tester may send a test instruction to the tester through a relevant protocol.

[0076] Specifically, after the data selector switches to the test mode, the tester can send a test instruction to the controller through a relevant protocol. After receiving the test instruction, the controller controls the test register to output a test value according to the test instruction.

[0077] Step 404: Collect the voltage output at the second end of the pin, and generate a test result for the first end of the pin based on the voltage and the test instruction.

[0078] To clarify the previous embodiment, in an embodiment of the present application, the test instruction may include a test value. Collecting the voltage output at the second end of the pin and generating a test result for the first end of the pin based on the voltage and the test instruction includes collecting the voltage output at the second end of the pin and generating a test result based on the voltage and the test value, where the test value is 0 or 1.

[0079] Among them, the voltage may include a high voltage and a low voltage. The high voltage may be a voltage higher than a specific voltage value (for example, 1.5V), and the low voltage may be a voltage lower than a specific voltage value (for example, 0.3V).

[0080] In the embodiment of the present application, when the chip test system tests the chip, it can generate a test result based on the voltage output at the second end of the pin collected by the tester and the test value output by the test register.

[0081] Specifically, if the test value output by the test register is 0 and the voltage output at the second end of the pin collected by the tester is a low voltage, and when the test value output by the test register is, and the voltage output at the second end of the pin collected by the tester is a high voltage, it can be shown that the pin can work normally. Otherwise, it can be shown that the pin cannot work normally.

[0082] It should be noted that the foregoing explanation of the chip test system provided in the first aspect embodiment of the present application also applies to the control method of the chip test system in this embodiment, and will not be elaborated here.

[0083] In the embodiment of the present application, first, receive a mode switching instruction sent by the tester, and control the data selector to switch to the test mode according to the mode switching instruction. Then, when the data selector switches to the test mode, control the first input end and the output end of the data selector to conduct, receive the test instruction sent by the tester, control the test register to output a test value according to the test instruction, collect the voltage output at the second end of the pin, and generate a test result for the first end of the pin based on the voltage and the test instruction. Thus, it is possible to test the pins of the chip by verifying the output voltage of the chip pins, and it is possible to introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0084] Figure 5Schematic flowchart of the control method for the chip testing system according to another embodiment of the present application.

[0085] The control method for the chip testing system according to the embodiment of the present application can be executed by the chip testing system provided in the second aspect of the present application to receive a mode switching instruction sent by a tester, control a data selector to switch to a test mode according to the mode switching instruction, and then when the data selector switches to the test mode, control the first input terminal and the output terminal of the data selector to conduct, receive a test instruction sent by the tester, control a test register to output a test value according to the test instruction, collect the voltage output from the second terminal of a pin, and generate a test result for the first terminal of the pin according to the voltage and the test instruction, so as to be able to test the pins of the chip by verifying the input voltage of the chip pins, and be able to introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0086] As Figure 5 shown, the control method for the chip testing system may include the following steps:

[0087] Step 501, provide a voltage to the second terminal of the pin.

[0088] Among them, the voltage may include a high voltage and a low voltage. The high voltage may be a voltage higher than a specific voltage value (for example, 1.5V), and the low voltage may be a voltage lower than a specific voltage value (for example, 0.3V).

[0089] Specifically, when the chip testing system tests the chip, the tester may provide a high voltage or a low voltage to the second terminal of the pin.

[0090] Step 502, read the test value corresponding to the voltage output from the first terminal of the pin, and send the test value to the controller. Among them, the test value may be 0 or 1.

[0091] In the embodiment of the present application, the test value corresponding to the high voltage is 1, and the test value corresponding to the low voltage is 0. When the voltage output from the first terminal of pin 312 is a high voltage, the test value read by the read-only memory 313 is 1. When the voltage output from the first terminal of pin 312 is a low voltage, the test value read by the read-only memory 313 is 0.

[0092] Specifically, after the tester provides a high voltage or a low voltage to the second terminal of the pin, the read-only register may read the test value corresponding to the voltage output from the first terminal of the pin, and send the test value to the controller.

[0093] Step 503, forward the test value to the tester.

[0094] Specifically, after the controller receives the test value sent by the read-only register, it may forward the test value to the tester.

[0095] Step 504: Generate a test result for the second end of the pin according to the voltage and the test value.

[0096] In the embodiment of the present application, after the tester receives the test value forwarded by the controller, it can generate a test result for the second end of the pin according to the test value and the voltage provided by the tester for the second end of the pin.

[0097] Specifically, when the voltage provided by the tester for the second end of the pin is a high voltage, and the test value received by the tester from the controller is 1, that is, the test value corresponding to the voltage output from the first end of the pin is 1, and when the voltage provided by the tester for the second end of the pin is a low voltage, and the test value received by the tester from the controller is 0, that is, the test value corresponding to the voltage output from the first end of the pin is 0, it indicates that the pin can work normally; otherwise, it indicates that the pin cannot work normally.

[0098] It should be noted that the foregoing explanation of the chip test system provided in the second aspect embodiment of the present application also applies to the control method of the chip test system in this embodiment, and will not be elaborated here.

[0099] In the embodiment of the present application, first, receive a mode switching instruction sent by the tester, and control the data selector to switch to the test mode according to the mode switching instruction. Then, when the data selector switches to the test mode, control the first input end of the data selector to be conducted with the output end of the data selector, receive a test instruction sent by the tester, and control the test register to output a test value according to the test instruction, and collect the voltage output from the second end of the pin, and generate a test result for the first end of the pin according to the voltage and the test instruction. Thus, it is possible to test the pins of the chip by verifying the input voltage of the chip pins, and it is possible to introduce test logic in the chip design stage, improving the test speed and test accuracy.

[0100] In the description of this specification, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0101] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0102] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A chip testing system, characterized in that, Comprising a chip and a tester, the chip and the tester are connected, wherein, The chip includes a controller, pins, a data selector, and a test register. Among them, the controller is respectively connected to the control end of the data selector and the control end of the test register. The first input end of the data selector is connected to the output end of the test register. The output end of the data selector is connected to the first end of the pin. The second end of the pin is connected to the tester; The controller is configured to receive a mode switching instruction sent by the tester and control the data selector to switch to the test mode according to the mode switching instruction; The data selector is configured to control the first input end and the output end of the data selector to conduct when the data selector switches to the test mode; The controller is further configured to receive a test instruction sent by the tester and control the test register to output a test value according to the test instruction; The tester is configured to collect the voltage output from the second end of the pin and generate a test result for the first end of the pin according to the voltage and the test instruction; Wherein, the test instruction includes the test value, and the tester is specifically configured to: Collect the voltage output from the second end of the pin and generate the test result according to the voltage and the test value, where the test value is 0 or 1.

2. The chip testing system according to claim 1, wherein, The chip further includes a functional path, the functional path is connected to the second input end of the data selector, and the data selector is further configured to: Control the second input end of the data selector to be closed when the data selector switches to the test mode.

3. The chip testing system according to claim 2, wherein The data selector is further configured to: When the chip is powered on, control the second input end and the output end of the data selector to conduct, and control the first input end of the data selector to be closed.

4. A chip testing system, characterized in that, Comprising a chip and a tester, the chip and the tester are connected, wherein, The chip includes a controller, pins, and a read-only register. Among them, the controller is connected to the control end of the read-only register. The first end of the pin is connected to the input end of the read-only register. The second end of the pin is connected to the tester; The tester is configured to provide a voltage for the second end of the pin; The read-only register is configured to read the test value corresponding to the voltage output from the first end of the pin and send the test value to the controller; The controller is configured to forward the test value to the tester after receiving the test value sent by the read-only register; The tester is further configured to generate a test result for the second end of the pin according to the voltage and the test value; Wherein, the test value is 0 or 1.

5. A control method for a chip testing system according to any one of claims 1-3, characterized in that, Comprising: Receiving a mode switching instruction sent by the tester and controlling the data selector to switch to the test mode according to the mode switching instruction; When the data selector switches to the test mode, controlling the first input end and the output end of the data selector to conduct; Receive the test instruction sent by the testing machine and control the test register to output a test value according to the test instruction; Collect the voltage output from the second end of the pin and generate a test result for the first end of the pin according to the voltage and the test instruction.

6. The control method of the chip testing system according to claim 5, wherein Wherein, The test instruction includes the test value, and the step of collecting the voltage output from the second end of the pin and generating a test result for the first end of the pin according to the voltage and the test instruction includes: Collect the voltage output from the second end of the pin and generate the test result according to the voltage and the test value, wherein the test value is 0 or 1.

7. A control method for a chip testing system according to claim 4, characterized in that, It includes: Provide a voltage for the second end of the pin; Read the test value corresponding to the voltage output from the first end of the pin and send the test value to the controller; Forward the test value to the testing machine; Generate a test result for the second end of the pin according to the voltage and the test value.

8. The control method of the chip testing system according to claim 7, wherein Wherein, The test value is 0 or 1.

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