Method and device for repairing weak memory order problem

Abstract

The present application discloses a method and device for repairing weak memory order problems, which relates to the field of computer technology. The method can automatically repair weak memory order problems in a multi-threaded program during the compilation phase of the program. The method comprises: determining a read-write instruction set in the code to be repaired; classifying the instructions in the read-write instruction set to determine the target instruction; inserting a memory barrier instruction between the previous read-write instruction of the target instruction and the target instruction; wherein the read-write instruction set comprises read instructions and / or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used to access memory.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for repairing a weak memory order problem. Background Art

[0002] When a multi-threaded program developed based on a non-weak memory model runs in a computer device that uses a weak memory model, the instruction semantics supported by the hardware under different memory models are different. This may cause the threads running in parallel in the program to execute read and write instructions for memory access out of order, resulting in a weak memory order problem.

[0003] For example, when a multi-threaded program developed based on a strong memory model is run in a computer device using a weak memory model, a weak memory order problem may occur when the threads running in parallel in the program execute read and write instructions for accessing memory. In this case, the functions to be implemented by the program may have logical errors, resulting in inaccurate output results after the program is run.

[0004] Based on this, how to fix the problem of weak memory order in multi-threaded programs is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present application provides a method and device for repairing weak memory ordering problems, which can automatically repair weak memory ordering problems in a multi-threaded program during the compilation phase of the program.

[0006] To achieve the above objectives, this application provides the following technical solutions:

[0007] In a first aspect, the present application provides a method for repairing a weak memory order problem, the method comprising: determining a read-write instruction set in a code to be repaired. Classifying the instructions in the read-write instruction set to determine a target instruction. Inserting a memory barrier instruction between a previous read-write instruction of the target instruction and the target instruction. The read-write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used to access memory.

[0008] Through the method provided by the present application, the target instruction can be determined by classifying the instructions to be repaired. Then, a memory barrier instruction is inserted before the target instruction so that the target instruction can be executed in the order required by the program itself, thereby automatically repairing the problem of weak memory order of the multi-threaded program. The method provided by the embodiment of the present application can automatically repair the problem of weak memory order of the multi-threaded program, greatly improving the efficiency of repairing the problem of weak memory order of the program.

[0009] In a possible design, the above “classifying instructions in the read-write instruction set to determine the target instruction” specifically includes: determining a first category of instructions in the read-write instruction set; and determining the target instruction based on the first category of instructions. The instructions in the first category of instructions are weakly memory-order-safe instructions. The target instruction is an instruction in the above read-write instruction set other than the first category of instructions.

[0010] In another possible design, the above “determining the target instruction based on the first category of instructions” specifically includes: determining the target instruction set based on the first category of instructions; and determining the target instruction in the target instruction set based on the optimization strategy. The target instruction set includes all instructions in the above read and write instruction set except the first category of instructions. The optimization strategy is used to indicate the type of read and write instructions that need to fix the weak memory order problem.

[0011] In another possible design, the above-mentioned optimization strategy includes at least one of the following strategies: First strategy, determine the read-write instructions in the target instruction set that are in the whitelist as the target instruction; or, determine the read-write instructions in the target instruction set except the read-write instructions in the blacklist as the target instruction. Second strategy, determine the only dependent read-write instructions among the read-write instructions with context dependencies in the target instruction set as the target instruction. Third strategy, determine the read-write instructions in the target instruction set except the read-write instructions related to special registers as the target instruction. Fourth strategy, determine the read-write instructions in the target instruction set except the read-write instructions related to input and output parameters as the target instruction.

[0012] In another possible design, the first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0013] Through these possible designs, the first-class instructions that are safe and do not have weak memory ordering problems can be accurately identified, and the target instructions can be determined by excluding the first-class instructions. Through this method, the read and write instructions that do not need to be repaired in the code to be repaired can be quickly excluded, thereby minimizing the insertion of unnecessary memory barrier instructions, thereby improving the running performance of the repaired multi-threaded program.

[0014] In addition, through optimization strategies, the insertion of unnecessary memory barrier instructions can be further reduced, thereby further improving the running performance of the repaired multi-threaded program.

[0015] In another possible design, the above-mentioned “classifying the instructions in the read-write instruction set to determine the target instruction” specifically includes: classifying the instructions in the read-write instruction set based on the above-mentioned optimization strategy to determine the target instruction. The optimization strategy is used to indicate the type of read-write instruction that needs to repair the weak memory order problem.

[0016] Through this possible implementation method, the present application can determine the read and write instructions that need to be inserted with memory barrier instructions in the read and write instruction set through optimization strategies, so that the insertion of unnecessary memory barrier instructions can be reduced, thereby improving the running performance of the repaired multi-threaded program.

[0017] In another possible design, the method further includes: obtaining a fifth strategy configured by the user and adding the fifth strategy to the optimization strategy.

[0018] Here, the fifth strategy may be a user-defined configuration strategy. In this case, through this possible design, the present application allows the code to be repaired to be repaired through the user-defined configuration strategy, thereby improving the flexibility of the application of the present application.

[0019] In another possible design, before the above-mentioned "determining the target instruction", the above-mentioned method also includes: receiving indication information, where the indication information is used to instruct the user to select the optimization strategy from the candidate optimization strategies.

[0020] Here, the optimization strategy to be selected may be an optimization strategy preset by the repair device. Thus, through this possible design method, the user can freely select an optimization strategy for repairing the code to be repaired from the optimization strategies to be selected, thereby improving the flexibility of the application of the present application.

[0021] Through this possible implementation, users can customize the configuration optimization strategy, thereby achieving flexible application of the method of the present application.

[0022] In another possible design, the above “determining the read-write instruction set” specifically includes: identifying instructions in the target function to determine the read-write instruction set. The target function is any function in the above code to be repaired.

[0023] Through this possible design, the present application can identify and repair weak memory order problems in the code to be repaired on a function basis, so that the method of the present application can be applied to repair weak memory order problems in large-scale multi-threaded programs, thereby improving the practicality of the method of the present application.

[0024] In another possible design, the code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program through a compiler.

[0025] In another possible design, the code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program through a compiler.

[0026] Through these two possible designs, the method for repairing weak memory order problems provided by the present application can be executed synchronously with the source code compilation of a multi-threaded program, thereby automatically repairing the weak memory order problems of the multi-threaded program, thereby improving the efficiency of repairing the weak memory order problems of the multi-threaded program.

[0027] In a second aspect, the present application provides a device for repairing weak memory order problems.

[0028] In a possible design, the device is used to execute any of the methods provided in the first aspect above. The present application may divide the functional modules of the device according to any of the methods provided in the first aspect above. For example, each functional module may be divided according to each function, or two or more functions may be integrated into one processing module. Exemplarily, the present application may divide the device into a determination unit and an insertion unit, etc. according to the function. The description of the possible technical solutions and beneficial effects executed by each of the functional modules divided above can refer to the technical solutions provided by the first aspect or its corresponding possible design, which will not be repeated here.

[0029] In another possible design, the device for repairing the weak memory order problem includes: a memory and one or more processors, the memory and the processor are coupled. The memory is used to store computer instructions, and the processor is used to call the computer instructions to execute any method provided by the first aspect and any possible design thereof.

[0030] In a third aspect, the present application provides a computer-readable storage medium, such as a non-transitory computer-readable storage medium, on which a computer program (or instruction) is stored, and when the computer program (or instruction) is executed on a device for repairing a weak memory order problem, the device for repairing a weak memory order problem executes any method provided by any possible implementation in the first aspect or the second aspect.

[0031] In a fourth aspect, the present application provides a computer program product, which, when executed on an apparatus for repairing weak memory order problems, enables any method provided by any possible implementation in the first aspect to be executed.

[0032] In a fifth aspect, the present application provides a chip system, comprising: a processor, the processor being used to call and run a computer program stored in a memory from the memory, and execute any one of the methods provided in the implementation manner in the first aspect.

[0033] It can be understood that any of the above-mentioned devices, computer storage media, computer program products or chip systems can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here.

[0034] In this application, the name of the device for repairing weak memory order problems does not limit the device or functional module itself. In actual implementation, these devices or functional modules may appear with other names. As long as the functions of each device or functional module are similar to those of this application, they fall within the scope of the claims of this application and their equivalent technologies.

[0035] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of a process of compiling a program source code into a machine executable program code in the prior art;

[0037] Figure 2 A schematic diagram of the hardware structure of a computing device provided in an embodiment of the present application;

[0038] Figure 3 A flowchart of a method for repairing a weak memory order problem provided in an embodiment of the present application;

[0039] Figure 4a A repair device provided in an embodiment of the present application obtains a schematic diagram of an optimization strategy selected by a user from among candidate optimization strategies based on a graphical interactive interface;

[0040] Figure 4b A flowchart of another method for repairing a weak memory order problem provided in an embodiment of the present application;

[0041] Figure 5 A structural schematic diagram of a repair device provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of the structure of a chip system provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of the structure of a computer program product provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to more clearly understand the embodiments of the present application, some terms or technologies involved in the embodiments of the present application are explained below:

[0045] 1) Compiler

[0046] Compilers are usually used to translate "one language" into "another language". For example, they translate the source code of a program developed by a developer in a high-level computer language (such as C language, C++ language, etc.) into machine language code (such as binary code) that can be recognized and run by the machine.

[0047] Generally, the compiler can integrate the assembly function. In this way, the compiler can first compile the program source code processed by the preprocessor into assembly code. The assembly code is the assembly language code. Then, the assembly code is further compiled into the target code through the assembly function. The target code is a language code that can be recognized by the machine, such as binary code. In this case, the target code combines the machine language programs that are independently assembled in the target code through the linker, and the program code that can be executed by the machine can be obtained.

[0048] Optionally, in order to improve the compilation effect, the compiler compiles the program source code processed by the preprocessor into an intermediate language before compiling it into assembly code. The intermediate language is generated by the compiler after parsing the preprocessed program source code, and the intermediate language is used to optimize the compiler to compile and obtain the target code.

[0049] As an example, refer to Figure 1 , Figure 1 A schematic diagram of the process of compiling program source code into machine executable program code is shown.

[0050] like Figure 1 As shown, after the program source code is processed by the preprocessor 11, it is input into the compiler 12. The subcompiler 121 of the compiler 12 can compile the preprocessed program source code into assembly code and output it. Then, the assembler 122 assembles and compiles the assembly code output by the subcompiler 121 to obtain the target code. The target code is the code that can be recognized by the machine. Finally, after the target code is processed by the linker 13, an executable program that can be run by the machine can be obtained.

[0051] After the subcompiler 121 parses the preprocessed program source code, an intermediate language can be generated. The subcompiler 121 can also further compile the intermediate language to obtain Figure 1 The assembly code shown.

[0052] 2) Multithreaded Programs

[0053] An instance of a running program is usually called a process. A process can include at least one thread, which refers to a single sequential control flow in a process. Usually, a process can have multiple threads running concurrently, and the multiple threads can run in parallel through multiple processing cores in a computer device to perform different tasks. Of course, a process can also have only one thread, which is not limited to this.

[0054] Therefore, a multi-threaded program refers to a program that includes multiple threads in one process during its running process.

[0055] 3) Other terms

[0056] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0057] In the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "plurality" means two or more.

[0058] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0059] It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0060] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0061] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0062] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] It should be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0064] It should be understood that the threads running in parallel in a multi-threaded program are independent control flows, but there may be a logical relationship between the instructions for accessing memory (for simplicity of description, the present application embodiment abbreviates "accessing memory" as "accessing memory") in different threads. Here, the instructions for accessing memory generally include read instructions and / or write instructions.

[0065] As an example, in a multi-threaded program developed based on a non-weak memory model, the write instruction 1 for memory access in the first thread is used to write (store) the value 0 in register 1 into the memory. The read instruction 2 for memory access in the second thread is used to read (load) the value 0 from the memory into register 2. Therefore, there is a logical order relationship between the write instruction 1 and the read instruction 2, that is, after the write instruction 1 writes the value 0 of register 1 into the memory, the read instruction 2 can read the value 0 in the memory into the register.

[0066] When the first thread and the second thread of the multi-threaded program are running in parallel through two processing cores of a computer device using a weak memory model, if write instruction 1 is executed before the read instruction or write instruction before write instruction 1 in the first thread, this may cause write instruction 1 to be executed later than read instruction 2 in the second thread. When write instruction 1 is executed later than read instruction 2 in the second thread, when read instruction 2 in the second thread is executed, the memory is empty, that is, the value 0 in register 1 has not been written to the memory. In this case, logical errors occur in the tasks executed by the first thread and the second thread, which may cause the program to crash or inaccurate output results. This situation is called the problem of weak memory ordering generated by write instruction 1 in the first thread.

[0067] Generally, when a program thread is running, weak memory order may occur, including: read-read (loadload), write-write (storestore), read-write (loadstore), and write-read (storeload). That is, the execution order of two read instructions is reversed, the execution order of two write instructions is reversed, the execution order of read instructions and write instructions is reversed, and the execution order of write instructions and read instructions is reversed. Here, the reversed execution order of instructions means that the execution order of instructions is opposite to the execution order required by the program itself.

[0068] For the above-mentioned weak memory order problem, a memory barrier instruction can usually be inserted before the memory access instruction to ensure that the two memory access instructions can be executed in the order required by the program.

[0069] For example, in program 1 developed based on a non-weak memory model, the normal execution order of instruction 1 for memory access and instruction 2 for memory access is "instruction 1→instruction 2". When program 1 runs in a computer device that adopts a weak memory model, a weak memory order problem may occur between instruction 1 and instruction 2. At this time, a memory barrier instruction can be inserted between instruction 1 and instruction 2, so that it can be ensured that when program 1 runs in a computer device that adopts a weak memory model, instruction 1 and instruction 2 can be executed in the order of "instruction 1→instruction 2".

[0070] However, in the traditional method, the location where the memory barrier instruction needs to be inserted in the program is generally determined by the developer based on experience. When the program is large in scale, the efficiency of this method is extremely low.

[0071] Based on this, an embodiment of the present application provides a method for repairing weak memory order problems, and the method is applied to a device for repairing weak memory order problems (for ease of description, in the embodiments of the present application below, the "device for repairing weak memory order problems" is referred to as a "repair device"). The method identifies the code to be repaired to determine a read-write instruction set in the code to be repaired, and the read-write instruction set includes read-write instructions for accessing memory. Then, the repair device classifies the read-write instructions in the read-write instruction set based on the determined read-write instruction set to determine the target instruction that needs to insert a memory barrier. Finally, a memory barrier instruction is inserted before the target instruction, thereby automatically repairing the weak memory order problem of the code to be repaired, greatly improving the efficiency of repairing the weak memory order problem of the code to be repaired.

[0072] The code to be repaired may be an intermediate language obtained by compiling a multi-threaded program source code through a compiler, or an assembly code obtained by compiling a compiler, which is not specifically limited in the embodiments of the present application.

[0073] The multi-threaded program source code may be a program source code developed in a high-level computer language such as C, C++ or Fortran, and the embodiments of the present application do not specifically limit this.

[0074] The embodiment of the present application also provides a repair device, which can be applied to any computing device with computing processing capabilities. The computing device can be a general-purpose computer or a server, etc., and the embodiment of the present application does not make specific limitations on this.

[0075] refer to Figure 2 , Figure 2 FIG. 2 shows a hardware structure diagram of a computing device 20 provided in an embodiment of the present application. The above-mentioned device for repairing memory access problems can be applied to the computing device 20. Figure 2 As shown, the computing device 20 includes a processor 21, a memory 22, a communication interface 23, an input / output interface 24, and a bus 25. The processor 21, the memory 22, the communication interface 23, and the input / output interface 24 may be connected via the bus 25.

[0076] The processor 21 is the control center of the computing device 20, and may be a general-purpose central processing unit (CPU) or other general-purpose processors, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0077] As an example, the processor 21 may include one or more CPUs, such as Figure 2 The CPU 0 and CPU 1 shown in FIG. Among them, CPU 0 and CPU 1 can run two threads of the multi-threaded program in parallel.

[0078] The memory 22 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto.

[0079] In a possible implementation, the memory 22 may exist independently of the processor 21. The memory 22 may be connected to the processor 21 via a bus 25, and is used to store data, instructions, or program codes. When the processor 21 calls and executes the instructions or program codes stored in the memory 22, the method for repairing the access disorder problem provided in the embodiment of the present application can be implemented.

[0080] In another possible implementation, the memory 22 may also be integrated with the processor 21 .

[0081] The communication interface 23 is used for connecting the computing device 20 to other devices (such as network nodes in a public cloud, etc.) through a communication network, and the communication network may be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface 23 may include a receiving unit for receiving data and a sending unit for sending data.

[0082] The input / output interface 24 is used to implement human-computer interaction between the user and the computing device 20. The input / output interface 24 can be a mouse, a keyboard, a touch screen, etc., but is certainly not limited thereto.

[0083] As an example, a user may submit a blacklist or a whitelist, etc. to a computing device based on an input-output interface.

[0084] The bus 25 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 2 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0085] It should be pointed out that Figure 2 The structure shown in the figure does not constitute a limitation on the computing device 20, except Figure 2 In addition to the components shown, the computing device 20 may include more or fewer components than shown, or combine certain components, or arrange the components differently.

[0086] The following describes a method for repairing the weak memory order problem provided by an embodiment of the present application in conjunction with the accompanying drawings.

[0087] refer to Figure 3 , Figure 3 A schematic diagram of a method for repairing a weak memory order problem provided by an embodiment of the present application is shown. The method can be applied to Figure 2 The repair device shown. The method may include the following steps:

[0088] S101, the repair device determines a read and write instruction set.

[0089] Specifically, the repair device may determine the read-write instruction set in the code to be repaired, where the read-write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used for memory access.

[0090] For example, the read instruction "ldr x1, [x0]" means reading the value from the memory address pointed to by the general register x0 and writing the value to the general register x1. For another example, the write instruction "str x1, [x0]" means writing the value in the general register x1 to the memory address pointed to by the general register x0.

[0091] For the sake of simplicity, in the following description of the embodiments of the present application, “read instructions and / or write instructions” are referred to as “read and write instructions” for short.

[0092] The code to be repaired may be an intermediate language obtained by compiling the source code of a multi-threaded program through a compiler. Alternatively, the code to be repaired may also be an assembly code obtained by compiling the source code of a multi-threaded program through a compiler, which is not specifically limited in the embodiments of the present application. Here, the description of the compiler and the intermediate language may refer to the above description, which will not be repeated here.

[0093] Optionally, the code to be repaired may also be an intermediate language obtained by compiling a module to be repaired in the source code of a multi-threaded program after being compiled by a compiler. Alternatively, the code to be repaired may also be an assembly code obtained by compiling a module to be repaired in the source code of a multi-threaded program after being compiled by a compiler, which is not specifically limited in the embodiments of the present application.

[0094] The module to be repaired may be one of the multiple modules obtained after the developer divides the source code of the multi-threaded program. Alternatively, the module to be repaired may be one of the multiple modules obtained after the preprocessor or compiler divides the source code of the multi-threaded program. This embodiment of the application is not limited to this.

[0095] The source code of the multi-threaded program may be divided according to the functions or uses that the code can achieve, but is certainly not limited thereto.

[0096] Among them, the multiple modules obtained after the source code of the multi-threaded program is divided include a security module and a non-security module. Among them, the security module refers to the read and write instructions obtained after the source code in the module is compiled, and the problem of weak memory order will not occur. The non-security module refers to the read and write instructions obtained after the source code in the module is compiled, which will cause the problem of weak memory order. Therefore, the non-security module is the above-mentioned module to be repaired.

[0097] Optionally, the security module may be determined through a large number of running tests to determine that it will not cause a weak memory order problem, which is not specifically limited.

[0098] Specifically, the repair device may identify instructions in the code to be repaired to determine the read and write instructions in the code to be repaired, thereby obtaining a read and write instruction set corresponding to the code to be repaired.

[0099] In a possible implementation, the repair device can identify the instructions in the target function based on the function in the code to be repaired, so as to determine the read and write instructions in the target function, thereby obtaining the read and write instruction set corresponding to the target function. The target function is any function in the code to be repaired. It should be understood that the code to be repaired is composed of at least one function.

[0100] Specifically, the repair device can traverse each instruction in the target function and identify each instruction in the target function to determine the read and write instructions in the target function, thereby obtaining the read and write instruction set corresponding to the target function.

[0101] In this way, after the repair device identifies the instructions in each function in the code to be repaired, it can determine the read and write instruction set corresponding to each function. The set of read and write instruction sets corresponding to each function includes all read and write instructions in the code to be repaired.

[0102] It can be seen that when the read-write instruction set is determined in this way, each function in the code to be repaired can correspond to a read-write instruction set, that is, the functions in the code to be repaired correspond to the determined read-write instruction set one by one. Alternatively, the code to be repaired can also correspond to a read-write instruction set. In this case, the read-write instruction set can be obtained by the repair device after aggregating the read-write instruction sets determined based on each function, and the embodiments of the present application do not specifically limit this.

[0103] In another possible implementation, the repair device may traverse the instructions in the code to be repaired and identify the instructions in the code to be repaired to determine the read and write instructions in the code to be repaired, thereby obtaining a read and write instruction set corresponding to the code to be repaired.

[0104] It can be seen that when the read-write instruction set is determined in this way, the code to be repaired corresponds to one read-write instruction set.

[0105] S102: The repair device determines a first category of instructions based on a read-write instruction set.

[0106] The repair device can determine the first category of instructions in the read-write instruction set based on the determined read-write instruction set. Here, the instructions in the first category of instructions will not cause weak memory ordering problems, that is, the first category of instructions are weak memory ordering safe instructions.

[0107] Among them, the instructions in the first category of instructions can be instructions that themselves will not cause weak memory ordering problems, or instructions that will not cause weak memory ordering problems in a preset context, and there is no limitation on this.

[0108] Optionally, the first category of instructions may include at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0109] Among them, the non-shared variable between threads is a variable dedicated to a thread (such as the first thread), and the variable will not be called by threads other than the first thread. In this way, for instructions to read and write such variables, weak memory ordering problems usually do not occur.

[0110] Exemplarily, the instructions for reading and writing non-shared variables between threads may include at least one of instructions for reading and writing local variables or instructions for reading and writing thread locals.

[0111] For read and write instructions with order-preserving semantics, their own semantics ensure that weak memory order issues will not occur during execution.

[0112] S103. The repair device determines a target instruction set according to the first category of instructions, and determines a target instruction in the target instruction set.

[0113] The instructions in the target instruction set are all instructions in the read-write instruction set except the first category of instructions. In this way, the repair device can determine the target instruction set in the read-write instruction set based on the first category of instructions determined above.

[0114] Furthermore, the repair device may determine a target instruction in a target instruction set.

[0115] In a possible implementation, the repair device may determine all instructions in the target instruction set as target instructions. That is, the repair device repairs all instructions in the target instruction set.

[0116] In another possible implementation, the repair device may determine the target instruction in the target instruction set based on at least one of the following optimization strategies: wherein the optimization strategy is used to indicate the type of read and write instructions that need to repair the weak memory ordering problem.

[0117] The repair device may be pre-installed with the optimization strategy, and the repair device may also obtain the optimization strategy configured by the user when starting to repair the code to be repaired, and there is no limitation on this.

[0118] The optimization strategy may include the first strategy to the fourth strategy described below. It can be understood that the first strategy to the fourth strategy are only exemplary descriptions, and the embodiments of the present application are not limited thereto.

[0119] In one case, when the above optimization strategy is an optimization strategy pre-configured by the user, the user can submit the optimization strategy to the repair device through the input and output interface of the computing device and in any of the following ways: graphical interactive interface, command line insertion, or configuration file setting. In response, the repair device can obtain the optimization strategy configured by the user, and determine the target instruction based on the obtained optimization strategy when repairing the code to be repaired.

[0120] Exemplary, a user submits an optimization strategy to a repair device through an input / output interface of a computing device and by setting a configuration file. Typically, a user can place a pre-configured optimization strategy file into the root directory of the repair device and modify the suffix format of the file, thereby setting a configuration file for the optimization strategy in the repair device. In this way, when the repair device executes the method provided in the embodiment of the present application, it can determine the target instruction in the target instruction set and repair it according to the optimization strategy indicated by the configuration file.

[0121] Of course, the above-mentioned optimization strategy may also include a fifth strategy that is customized and configured by the user based on his or her own needs, which is not limited in the embodiments of the present application.

[0122] In this case, the repair device can pre-acquire the fifth strategy of the user's custom configuration and add the fifth strategy to the above-mentioned optimization strategy. In this way, the repair device can determine the target instruction based on the optimization strategy including the fifth strategy when repairing the code to be repaired. Here, the process of the repair device pre-acquiring the fifth strategy of the user's custom configuration can refer to the description of the repair device acquiring the optimization strategy pre-configured by the user in the above text, which will not be repeated here.

[0123] In another case, the above-mentioned optimization strategy is preset in the repair device. In this way, the repair device can determine the target instruction in the process of repairing the code to be repaired according to the preset optimization strategy. Of course, the repair device can also use the preset optimization strategy as the selected optimization strategy. In this way, the repair device can receive the indication information input by the user when starting to repair the code to be repaired, and determine the target instruction based on the optimization strategy indicated by the indication information. Here, the indication information is used to indicate the optimization strategy selected by the user from the selected optimization strategies.

[0124] It should be understood that the optimization strategy preset in the repair device may include the fifth strategy of the user-defined configuration pre-acquired by the repair device. Of course, the repair device may also acquire the fifth strategy of the user-defined configuration when repairing the code to be repaired, and this is not limited. The following is an example of the repair device acquiring the fifth strategy of the user-defined configuration when repairing the code to be repaired.

[0125] Exemplary, reference Figure 4a , Figure 4a The schematic diagram shows that the repair device obtains the optimization strategy selected by the user from the candidate optimization strategies based on the graphical interactive interface. Figure 4aAs shown in (a), when the repair device starts to prepare to repair the code to be repaired, or when the source code of the multi-threaded program is compiled, the dialog box 411 on the display interface 41 (such as a display) of the computing device can display options: the first strategy, the second strategy, the third strategy, the fourth strategy, and the custom optimization strategy, so as to ask the user about the optimization strategy to be used when repairing the code to be repaired. Among them, the first strategy, the second strategy, the third strategy, and the fourth strategy are the optimization strategies preset by the repair device. Among them, the custom optimization strategy is the optimization strategy that needs to be submitted by the user immediately.

[0126] like Figure 4a As shown in (a) in the figure, when the user selects the options "first strategy" and "second strategy" by controlling the mouse (or keyboard), the indication information for indicating the "first strategy" and "second strategy" is sent to the repair device. In this way, the repair device can determine the optimization strategies selected by the user as "first strategy" and "second strategy" based on the indication information. In this way, the repair device can determine the target instruction in the target instruction set based on the optimization strategy selected by the user and repair it.

[0127] like Figure 4a As shown in (b) of FIG. 1 , when the user selects the option “Customize Optimization Strategy” by controlling the mouse (or keyboard), the user can control the mouse (or keyboard) to select the option “Customize Optimization Strategy”. Figure 4a In the dialog box 412 shown in (c) in the figure, the user uploads the policy that the user has pre-customized. For example, the user can first operate the mouse (or keyboard) and click the "browse" icon to find the storage directory "Aa / bb / cc / " of the custom configured policy. Then, the user can operate the mouse (or keyboard) and click the "upload" icon to upload the user's custom configured policy. In response, the repair device receives the custom configured policy uploaded by the user. In this way, the repair device can determine the target instruction in the target instruction set based on the custom configured policy and repair it.

[0128] It can be seen that by allowing users to customize configuration strategies and allowing users to freely select optimization strategies from candidate optimization strategies, the application of the method provided in the embodiment of the present application is more flexible.

[0129] It should be understood that the repair device obtains the optimization strategy configured by the user before the technical solution described in the embodiment of the present application is executed. In this way, the repair device can repair the read and write instructions of the type indicated by the optimization strategy through the configured optimization strategy during the execution of the method provided in the embodiment of the present application.

[0130] The first strategy to the fourth strategy are described below by way of example:

[0131] First strategy: the repair device may determine the read-write instructions in the target instruction set that are in the white list as the target instructions, or the repair device may determine the read-write instructions in the target instruction set except the read-write instructions in the black list as the target instructions.

[0132] The above-mentioned whitelist and blacklist may be a blacklist and whitelist of functions in the code to be repaired, or may be a blacklist and whitelist of different functional modules in the code to be repaired, and there is no limitation on this.

[0133] The following uses the above whitelist and blacklist, which are the blacklist and whitelist of functions in the code to be repaired, as an example for explanation.

[0134] The function blacklist generally includes functions such as safe functions and / or hot functions in the code to be repaired.

[0135] Here, the safe function may generally be a function that does not cause a weak memory order problem after the executable program obtained by ordinary compilation is run, or the safe function may be a function that does not include shared variables in the source code, etc., without limitation. Since the safe function generally does not cause a weak memory order problem, the repair device does not need to repair the weak memory order problem of the safe function.

[0136] Hot functions are usually functions that are frequently called by a program. For example, if the number of times function A is called by a program is greater than or equal to a preset threshold, then function A is a hot function. Since the repair of the weak memory order problem of the instruction is achieved by inserting a memory barrier instruction before the instruction. Therefore, for hot functions, since they are frequently called, when a memory barrier instruction is inserted into a hot function, the running performance of the program will be reduced. Therefore, for hot functions, the repair device does not repair the weak memory order problem.

[0137] Of course, the hot functions in the function blacklist may also be hot functions that are determined in advance through the above-mentioned method of determining safe functions and are determined not to have weak memory ordering problems.

[0138] The function whitelist usually includes functions in the code to be repaired, except for the above-mentioned hot functions and / or safe functions. For such functions, the repair device can repair the weak memory order problem.

[0139] It should be understood that the repair device may preset the above-mentioned function blacklist and / or function whitelist, and the repair device may also obtain the function blacklist and / or function whitelist pre-configured by the user, and this is not limited.

[0140] When the above-mentioned function blacklist and / or function whitelist are pre-configured by the user, the user can submit the pre-configured function blacklist and / or function whitelist to the repair device through the input and output interface of the computing device, and through any of the methods such as a graphical interactive interface, command line insertion, or setting a configuration file. In response, the repair device can obtain the function blacklist and / or function whitelist configured by the user. Here, the process of the repair device obtaining the function blacklist and / or function whitelist configured by the user can refer to the description of the process of the repair device obtaining the user-defined optimization strategy, which will not be repeated here.

[0141] The second strategy: the repair device may determine, among the read-write instructions with context dependencies in the target instruction set, only the dependent read-write instructions as target instructions.

[0142] Optionally, the repair device can analyze the instructions in the target instruction set and determine the only dependent read and write instructions according to the context dependency of the read and write instructions in the target instruction set. Here, the only dependent read and write instructions refer to instructions that do not depend on other read and write instructions in the target instruction set.

[0143] As an example, if the target instruction set includes the following instructions:

[0144] Instruction 1: ldr x0, [s1];

[0145] Instruction 2: str x0, [s2];

[0146] Among them, instruction 1 "ldr x0, [s1]" means reading register x0 from the memory address indicated by register s1. Instruction 2 "str x0, [s2]" means writing the value in register x0 to the memory address indicated by register s2. It can be seen that when instruction 1 is not executed, that is, when the value in register x0 is not read from the memory address indicated by register s1, instruction 2 cannot be executed to write the value in register x0 to the memory address indicated by register s2. In other words, instruction 1 and instruction 2 are instructions with a dependency relationship, and instruction 1 is a dependency of instruction 2. That is, the execution of instruction 2 depends on the execution of instruction 1. In this case, when the execution of instruction 1 does not depend on other read-write instructions in the target instruction set, the repair device can determine that instruction 1 is a read-write instruction that serves only as a dependency.

[0147] For read and write instructions that have context dependencies and depend on other instructions for execution, such instructions usually do not have weak memory ordering issues. Therefore, the repair device usually does not repair such instructions.

[0148] The third strategy: the repair device may determine the read and write instructions in the target instruction set, except for the read and write instructions related to the special register, as the target instructions.

[0149] Among them, a special register usually refers to a register that is only used for a specific instruction or occasion. For example, the special register can be a floating point register. Here, a floating point register is a register used to store floating point numbers.

[0150] Taking the special register as a floating point register as an example, the repair device can determine whether the register is a floating point register by identifying the name of the register in the read / write instruction. When the register in the read / write instruction is a floating point register, the repair device can determine that the read / write instruction is a read / write instruction that operates on the floating point register.

[0151] Since the special registers are usually not used to read and write global control variables, the read and write instructions operating the special registers usually do not cause the problem of weak memory order. Therefore, the repair device usually does not repair the read and write instructions operating the special registers.

[0152] Fourth strategy: The repair device may determine the read-write instructions in the target instruction set, except for the read-write instructions related to the input and output parameters, as the target instructions.

[0153] Among them, the input and output parameters include the parameters that need to be input when calling the function, as well as the return value of the function.

[0154] For example, when the general register x0 is a register for storing the return value of a function, if the instruction in the target instruction set is as follows:

[0155] B malloc;

[0156] str x11,[x0];

[0157] Among them, "B" indicates that the instruction class is an instruction for calling a function, and "malloc" is the name of the function used to apply for memory. The instruction "B malloc" means calling the function malloc. When the function "malloc" is executed, the memory address returned by "malloc" will be written to the general register x0. At this time, the instruction "Str x11, [x0]" is used to indicate that the value in the register "x11" is written to the memory address indicated by the general register x0, which is the memory address returned by "malloc". In this case, the instruction "str x11, [x0]" is a read and write instruction related to input and output parameters.

[0158] Usually, in a scenario like this, weak memory order problems will not occur for read and write instructions related to input and output parameters, so the repair device does not need to repair them.

[0159] It should be noted that when the repair device determines the target instruction based on the fourth strategy, the target instruction can also be determined based on the contextual logical relationship of the instructions in the target instruction set, which will not be elaborated herein.

[0160] It should be noted that when the optimization strategy adopted by the repair device is any combination of the first strategy to the fourth strategy, the repair device can preset the priorities of multiple strategies in the combination strategy. In this way, when the same read-write instruction produces opposite results based on two different strategies, the repair device can process the read-write instruction based on the priority by using a strategy with a higher priority. Among them, the priority is used to indicate the priority level of the strategy, and a strategy with a higher priority level is used before a strategy with a lower optimization level.

[0161] Exemplarily, when the combination strategy is the second strategy and the third strategy, if instruction 1 is only a dependent instruction, the repair device should repair instruction 1 according to the instruction of the second strategy. At the same time, if instruction 1 is an instruction for reading and writing a floating-point register, then according to the instruction of the third strategy, the repair device should not repair instruction 1. In this case, different strategies in the combination strategy produce opposite results on the same instruction. At this time, if the priority of the second strategy in the combination strategy is higher than the third strategy, the repair device determines instruction 1 as the target instruction based on the second strategy and repairs it.

[0162] S104. The repair device inserts a memory barrier instruction between the previous read / write instruction of the target instruction determined above and the target instruction.

[0163] After determining the target instruction, the repair device inserts a memory barrier instruction between the previous read / write instruction of the target instruction and the target instruction, thereby repairing the weak memory order problem of the instructions in the code to be repaired.

[0164] The memory barrier instruction is used to indicate that the target instruction should be executed after the read and write instructions before the memory barrier instruction are executed.

[0165] As an example, if the target instruction is instruction 1, and the previous read / write instruction of the target instruction is instruction 2, then the repair device inserts a memory barrier instruction between instruction 1 and instruction 2. The memory barrier instruction is used to indicate that instruction 1 is executed after instruction 2.

[0166] Thus, the embodiment of the present application provides a method for repairing weak memory ordering problems. In the process of compiling the source code of a multi-threaded program, the method classifies the instructions to be repaired to determine the target instruction set. Then, the target instructions that need to insert memory barrier instructions are further determined in the target instruction set through the optimization strategy, so that the target instructions can be executed in the order required by the program itself. Through this method, the repair device can automatically repair the weak memory ordering problem of the multi-threaded program.

[0167] Optional, reference Figure 4b In another method for repairing the weak memory order problem provided in an embodiment of the present application, the above-mentioned S102-S103 can be replaced by the following step S202.

[0168] S202: The repair device classifies the instructions in the read-write instruction set based on the optimization strategy to determine the target instruction.

[0169] The read-write instruction set is the read-write instruction set determined by the repair device in S101.

[0170] The optimization strategy is used to indicate the type of read and write instructions that need to repair the weak memory order problem. The description of the optimization strategy can refer to the description of the optimization strategy above, which will not be repeated here.

[0171] Specifically, the repair device can divide the read-write instructions in the read-write instruction set determined in step S101 into read-write instructions that need to be inserted with memory barrier instructions and read-write instructions that do not need to be inserted with memory barrier instructions according to the optimization strategy based on the above-mentioned optimization strategy. Then, the repair device determines the read-write instructions that need to be inserted with memory barrier instructions as target instructions.

[0172] In this way, during the compilation of the source code of a multi-threaded program, the method for repairing the weak memory order problem provided by the embodiment of the present application can directly classify the instructions to be repaired through the optimization strategy, thereby determining the target instructions that need to insert the memory barrier instruction, so that the target instructions can be guaranteed to be executed in the order required by the program itself. Through this method, the repair device can automatically repair the weak memory order problem of the multi-threaded program.

[0173] In order to more easily understand the method provided in the embodiment of the present application, the following is an example of applying the method for repairing the weak memory order problem provided in the embodiment of the present application in the GNU Compiler Collection (GCC) to repair the weak memory order problem of a multi-threaded program.

[0174] Among them, GCC supports the compilation of program source code developed in high-level computer languages ​​such as C, C++ or Fortran. The working process of GCC compiling program source code includes: pre-processing, compiling, assembling and linking. The method for repairing weak memory ordering problems provided in the embodiment of the present application can be applied in the compilation stage.

[0175] In the compilation phase of GCC, after compiling the preprocessed multi-threaded program source code, the compiler's intermediate language (such as register transformation language (RTL) expression) can be obtained. Then, GCC can output the optimized intermediate language as assembly code through the final module.

[0176] Usually, the final module outputs the intermediate language as assembly code in units of functions. Specifically, the final module outputs the intermediate language as assembly code through the final_start_function, final, and final_end_function interfaces.

[0177] The final_start_function interface is used to initialize the state of the function, such as analyzing the number of instructions in the function in the intermediate language and determining the number of insn statements, which will not be described in detail.

[0178] final interface is used to output the intermediate language as assembly code. The method for repairing the weak memory order problem provided by the embodiment of the present application (for example Figure 3 or Figure 4b The method for repairing the weak memory order problem shown in FIG. 100 can be executed in this stage. Specifically, the repair device can execute the method described in S101-S104 above through the final interface to insert a memory barrier instruction before the target instruction. Then, the final interface calls the output_asm_insn function to output the insn statement as assembly code.

[0179] Among them, an insn statement contains multiple assembly instructions, and the length of each assembly instruction is generally 4. Since the number of insn statements and the number of instructions are determined when the function state is initialized, the final interface usually determines the length of an insn statement.

[0180] However, when the repair device repairs the read and write instructions through the final interface, a memory barrier instruction will be inserted before the target instruction. Therefore, the repair instruction will change the length of the insn statement. In this case, before the final interface is output as assembly code, the final_start_functio interface needs to process the original process of obtaining the length of the insn statement (such as get_attr_length) accordingly to obtain the length of the insn statement after the memory barrier instruction is inserted. For example, the number of instructions in the insn statement can be reduced through function calls to control the length of the insn statement, etc., and there is no limitation on this.

[0181] Finally, final_end_function is used to clean up the resources used to output the intermediate language to assembly code.

[0182] Then, GCC continues to assemble and link the repaired assembly code, thereby outputting executable program code. Here, the specific working process of GCC is not described in detail in the embodiment of the present application. It should be understood that the executable program code finally output by GCC is the program code with the weak memory order repaired.

[0183] In summary, the embodiment of the present application provides a method for repairing the weak memory order problem. In the process of compiling the source code of a multi-threaded program, the method classifies the instructions to be repaired to determine the target instruction set. Then, the target instructions that need to insert memory barrier instructions are further determined in the target instruction set through the optimization strategy, so that the target instructions can be executed in the order required by the program itself, thereby automatically repairing the weak memory order problem of the multi-threaded program. The method provided by the embodiment of the present application can repair the weak memory order problem of the multi-threaded program, greatly improving the efficiency of repairing the weak memory order problem of the program.

[0184] In addition, in the embodiment of the present application, the weak memory order problem in the code to be repaired is identified and repaired in units of functions, so that the method provided in the embodiment of the present application can be applied to the repair of weak memory order problems in large-scale multi-threaded programs, thereby improving the practicality of the method provided in the embodiment of the present application.

[0185] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0186] The embodiment of the present application can divide the functional modules of the repair device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0187] like Figure 5 As shown, Figure 5 FIG. 5 is a schematic diagram showing the structure of a repair device 50 provided in an embodiment of the present application. The repair device 50 can be used to execute the above-mentioned method for repairing weak memory order problems, for example, to execute Figure 3 The method shown in the figure. The repairing device 50 may include a determining unit 51 and an inserting unit 52.

[0188] The determination unit 51 is used to determine a read / write instruction set in the code to be repaired; and is used to classify the instructions in the read / write instruction set to determine a target instruction. The read / write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read / write instruction set are used to access memory. The insertion unit 52 is used to insert a memory barrier instruction between the previous read / write instruction of the target instruction and the target instruction.

[0189] As an example, combining Figure 3 , the determination unit 51 can be used to execute S101-S103, and the insertion unit 52 can be used to execute S104.

[0190] Optionally, the determination unit 51 is specifically used to determine a first category of instructions in the above read / write instruction set; and to determine a target instruction based on the first category of instructions. The instructions in the first category of instructions are weakly memory-order-safe instructions, and the target instruction is an instruction in the above read / write instruction set other than the first category of instructions.

[0191] As an example, combining Figure 3 , the determination unit 51 can be used to execute S102-S103.

[0192] Optionally, the determination unit 51 is specifically configured to determine a target instruction set based on the first category of instructions, and to determine a target instruction in the target instruction set based on an optimization strategy, wherein the target instruction set includes all instructions in the read and write instruction set except the first category of instructions. The optimization strategy is used to indicate the type of read and write instructions that need to fix the weak memory ordering problem.

[0193] As an example, combining Figure 3 , the determination unit 51 can be used to execute S103.

[0194] Optionally, the determining unit 51 is specifically configured to: classify the instructions in the read / write instruction set based on an optimization strategy to determine the target instruction. The optimization strategy is used to indicate the type of read / write instruction that needs to fix the weak memory ordering problem.

[0195] Optionally, the above-mentioned optimization strategy includes at least one of the following strategies: First strategy, determine the read-write instructions in the target instruction set that are in the whitelist as the target instructions; or, determine the read-write instructions in the target instruction set except the read-write instructions in the blacklist as the target instructions. Second strategy, determine the only dependent read-write instructions among the read-write instructions with context dependencies in the target instruction set as the target instructions. Third strategy, determine the read-write instructions in the target instruction set except the read-write instructions related to special registers as the target instructions. Fourth strategy, determine the read-write instructions in the target instruction set except the read-write instructions related to input and output parameters as the target instructions.

[0196] Optionally, the repairing device 50 further includes: an acquiring unit 53, configured to acquire a fifth strategy configured by a user; and an adding unit 54, configured to add the fifth strategy to the above-mentioned optimization strategy.

[0197] Optionally, the repair device 50 further includes: a receiving unit 55, configured to receive instruction information before the determining unit 51 determines the target instruction, wherein the instruction information is used to instruct the user to select the above-mentioned optimization strategy from the candidate optimization strategies.

[0198] Optionally, the first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

[0199] Optionally, the repair device 50 further includes: an identification unit 56, which is used to identify instructions in the target function to determine the read and write instruction set. The target function is any function in the code to be repaired.

[0200] As an example, combining Figure 3 , the identification unit 56 can be used to execute S101.

[0201] Optionally, the code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program with a compiler, or the code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program with a compiler.

[0202] For the detailed description of the above optional methods, please refer to the above method embodiments, which will not be repeated here. In addition, the explanation of any of the above repair devices 50 and the description of the beneficial effects can refer to the above corresponding method embodiments, which will not be repeated here.

[0203] As an example, combining Figure 2 The determination unit 51, the insertion unit 52, the addition unit 54 and the identification unit 56 in the repair device 50 can be Figure 2 Processor 21 in the Figure 2 The acquisition unit 53 and the receiving unit 55 can be implemented by the program code in the memory 22 in the embodiment of the present invention. Figure 2 It is implemented by the input / output interface 24 or the communication interface 25.

[0204] The present application embodiment also provides a chip system 60, such as Figure 6 As shown, the chip system 60 includes at least one processor and at least one interface circuit. As an example, when the chip system 60 includes a processor and an interface circuit, the processor may be Figure 6 The processor 61 shown in the solid line frame (or the processor 61 shown in the dotted line frame) may be Figure 6 The interface circuit 62 shown in the solid line frame (or the interface circuit 62 shown in the dotted line frame) is shown in the solid line frame. When the chip system 60 includes two processors and two interface circuits, the two processors include Figure 6 The processor 61 shown in the solid line frame and the processor 61 shown in the dotted line frame, the two interface circuits include Figure 6 The interface circuit 62 shown in the solid line frame and the interface circuit 62 shown in the dotted line frame are not limited to this.

[0205] The processor 61 and the interface circuit 62 can be interconnected via a line. For example, the interface circuit 62 can be used to receive signals (such as obtaining optimization strategies, etc.). For another example, the interface circuit 62 can be used to send signals to other devices (such as the processor 61). Exemplarily, the interface circuit 62 can read instructions stored in the memory and send the instructions to the processor 61. When the instruction is executed by the processor 61, the repair device can perform the various steps in the above embodiment. Of course, the chip system 60 can also include other discrete devices, which are not specifically limited in the embodiments of the present application.

[0206] Another embodiment of the present application further provides a computer-readable storage medium, which stores instructions. When the instructions are executed on a repair device, the repair device executes each step performed by the repair device in the method flow shown in the above method embodiment.

[0207] In some embodiments, the disclosed methods may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles of manufacture.

[0208] Figure 7 A conceptual partial view of a computer program product provided by an embodiment of the present application is schematically shown, where the computer program product includes a computer program for executing a computer process on a computing device.

[0209] In one embodiment, the computer program product is provided using a signal bearing medium 70. The signal bearing medium 70 may include one or more program instructions which, when executed by one or more processors, may provide the above-described Figure 3 Thus, for example, reference to Figure 3 One or more features of S101 to S104 may be undertaken by one or more instructions associated with the signal bearing medium 70. In addition, Figure 7 The program instructions in also describe example instructions.

[0210] In some examples, the signal bearing medium 70 may include a computer readable medium 71 such as, but not limited to, a hard drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM) or a random access memory (RAM), and the like.

[0211] In some implementations, the signal bearing medium 70 may include a computer recordable medium 72 such as, but not limited to, a memory, a read / write (R / W) CD, a R / W DVD, or the like.

[0212] In some embodiments, signal bearing medium 70 may include communication medium 73 such as, but not limited to, digital and / or analog communication media (eg, fiber optic cables, waveguides, wired communication links, wireless communication links, etc.).

[0213] The signal bearing medium 70 may be communicated by a wireless form of communication medium 73 (eg, a wireless communication medium conforming to the IEEE 1902.11 standard or other transmission protocol). The one or more program instructions may be, for example, computer executable instructions or logic implemented instructions.

[0214] In some examples, such as for Figure 3 The described repair apparatus may be configured to provide various operations, functions, or actions in response to one or more program instructions via computer-readable media 71 , computer-recordable media 72 , and / or communication media 73 .

[0215] It should be understood that the arrangement described here is only for illustrative purposes. Thus, it will be appreciated by those skilled in the art that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements can be omitted together according to the desired result. In addition, many of the described elements can be implemented as discrete or distributed components, or in any appropriate combination and position to combine other components to implement functional entities.

[0216] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When executing instructions on a computer and executing a computer, a process or function according to an embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, data center, etc. that contains one or more servers that can be integrated with a medium. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0217] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for repairing a weak memory order problem, characterized in that: The method comprises: Determine a read-write instruction set in the code to be repaired, wherein the read-write instruction set includes read instructions or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used to access memory; Determining a first category of instructions in the read-write instruction set, where the instructions in the first category of instructions are weakly memory-order-safe instructions; Based on the first category of instructions, determining a target instruction set; the target instruction set includes all instructions in the read-write instruction set except the first category of instructions; Based on the optimization strategy, the target instruction is determined in the target instruction set; the optimization strategy is used to indicate the type of read and write instructions that need to repair the weak memory order problem; A memory barrier instruction is inserted between a previous read / write instruction of the target instruction and the target instruction.

2. The method according to claim 1, characterized in that: The optimization strategy includes at least one of the following strategies: The first strategy is to determine the read-write instructions in the white list in the target instruction set as the target instruction; or to determine the read-write instructions in the target instruction set except the read-write instructions in the black list as the target instruction; The second strategy is to determine, among the read-write instructions with context dependency in the target instruction set, only the dependent read-write instructions as the target instructions; A third strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to the special register, as the target instructions; A fourth strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to the input and output parameters, as the target instructions.

3. The method according to claim 2, characterized in that The method further comprises: Get the fifth policy configured by the user; The fifth strategy is added to the optimization strategy.

4. The method according to any one of claims 1 to 3, characterized in that Before determining the target instruction, the method further includes: Instruction information is received, where the instruction information is used to instruct a user to select the optimization strategy from candidate optimization strategies.

5. The method according to any one of claims 1 to 3, characterized in that: The first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

6. The method according to any one of claims 1 to 3, characterized in that The determining of the read and write instruction set specifically includes: Instructions in a target function are identified to determine the read and write instruction set; wherein the target function is any function in the code to be repaired.

7. The method according to any one of claims 1 to 3, characterized in that The code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program through a compiler; or The code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program through a compiler.

8. A device for repairing weak memory order problems, characterized in that: The device comprises: A determination unit, configured to determine a read-write instruction set in the code to be repaired, wherein the read-write instruction set includes read instructions and / or write instructions in the code to be repaired, and the instructions in the read-write instruction set are used to access memory; The determination unit is specifically used to determine a first category of instructions in the read / write instruction set, where the instructions in the first category of instructions are weakly memory-order safe instructions; and to determine a target instruction set based on the first category of instructions; the target instruction set includes all instructions in the read / write instruction set except the first category of instructions; and to determine the target instruction in the target instruction set based on an optimization strategy; the optimization strategy is used to indicate the type of read / write instructions that need to fix the weak memory-order problem; An insertion unit is used to insert a memory barrier instruction between a previous read / write instruction of the target instruction and the target instruction.

9. The device according to claim 8, characterized in that The optimization strategy includes at least one of the following strategies: The first strategy is to determine the read-write instructions in the white list in the target instruction set as the target instruction; or to determine the read-write instructions in the target instruction set except the read-write instructions in the black list as the target instruction; The second strategy is to determine, among the read-write instructions with context dependency in the target instruction set, only the dependent read-write instructions as the target instructions; A third strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to the special register, as the target instructions; A fourth strategy is to determine the read and write instructions in the target instruction set, except for the read and write instructions related to the input and output parameters, as the target instructions.

10. The device according to claim 9, characterized in that The device also includes: an acquiring unit, configured to acquire a fifth policy configured by a user; An adding unit is used to add the fifth strategy to the optimization strategy.

11. The device according to any one of claims 8 to 10, characterized in that The device also includes: The receiving unit is used to receive instruction information before the determining unit determines the target instruction, wherein the instruction information is used to instruct the user to select the optimization strategy from the candidate optimization strategies.

12. The device according to any one of claims 8 to 10, characterized in that The first category of instructions includes at least one of instructions for reading and writing non-shared variables between threads, or read and write instructions with order-preserving semantics.

13. The device according to any one of claims 8 to 10, characterized in that The device also includes: An identification unit is used to identify instructions in a target function to determine the read and write instruction set; wherein the target function is any function in the code to be repaired.

14. The device according to any one of claims 8 to 10, characterized in that The code to be repaired is an intermediate language obtained by compiling the source code of the multi-threaded program through a compiler; or The code to be repaired is an assembly code obtained by compiling the source code of the multi-threaded program through a compiler.

15. A device for repairing weak memory order problems, characterized in that: The device comprises: a memory and one or more processors, the memory is used to store computer instructions, and the processor is used to call the computer instructions to execute the method according to any one of claims 1 to 7.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 7.

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