Method and processing unit for randomly generating instruction sequences

Abstract

A method and a processing unit for randomly generating an instruction sequence are provided. The method comprises: dividing the floating-point registers of the processing unit to be tested into a plurality of groups, the plurality of groups respectively corresponding to a plurality of floating-point types supported by the instruction set of the processing unit to be tested; initializing each floating-point register using a random value according to the floating-point type corresponding to the group to which it belongs; generating an instruction sequence, wherein, when generating a floating-point instruction, a floating-point register is selected from a specific group or a specific group set in the plurality of groups as an operand of the floating-point instruction according to the floating-point type of the operand specified by the floating-point instruction. When generating a floating-point instruction, the embodiment of the present disclosure selects a floating-point register from a specific group or a specific group set as an operand of the floating-point instruction according to the specified floating-point type, so that it can be ensured that the generated floating-point instruction will not generate NaN when executed by the processing unit to be tested, thereby ensuring the correctness of the random test of the instruction.

Description

Technical Field

[0001] The disclosed embodiments belong to the field of chip testing, and in particular to a method and a processing unit for randomly generating instruction sequences. Background Art

[0002] Instruction random testing is an important part of the processor verification process. Instruction random testing refers to generating instruction sequences to test processing units. Instruction random testing can greatly reduce the burden of verification engineers to manually write a large number of test cases during chip verification, while also reducing the impact of human factors in the verification process, achieving better test results.

[0003] The processing unit is mainly composed of instruction set architecture and micro-architecture. The instruction set architecture supports multiple floating-point types, such as single-precision, multi-precision, double-precision, quad-precision, etc. The micro-architecture usually uses the maximum-width floating-point register to store any floating-point type. For example, 64-bit registers are uniformly used to store various floating-point types, and when the floating-point number width is less than the floating-point register width, the insufficient part is filled with 1 (this method is called nanbox).

[0004] However, in the random test of instructions, the inventors found that the randomly generated floating-point instructions arbitrarily use the floating-point numbers after nanbox as operands, which may cause the floating-point instructions with lower precision to use the floating-point numbers with higher precision as operands. The floating-point numbers with higher precision are illegal values ​​for the floating-point instructions with lower precision. Once this happens, the microarchitecture will refresh the floating-point numbers with higher precision to NaN (a kind of "non-number"). If a register is refreshed to NaN, any operation instruction that uses the register as an operand will also generate NaN. This cycle will continue, and a large number of NaNs will be generated. However, if there are too many NaN values, the correctness and reliability of random test of instructions will be questioned. Summary of the invention

[0005] In view of this, an embodiment of the present disclosure provides a method and a processing unit for randomly generating an instruction sequence to solve the problems existing in the prior art.

[0006] In a first aspect, an embodiment of the present disclosure provides a method for randomly generating an instruction sequence, wherein the instruction sequence is to be executed by a processing unit to be tested, comprising:

[0007] Dividing the floating-point registers of the processing unit to be tested into a plurality of groups, wherein the plurality of groups respectively correspond to a plurality of floating-point types supported by the instruction set of the processing unit to be tested;

[0008] Initialize each floating-point register with a random value according to the floating-point type of the group to which it belongs;

[0009] The instruction sequence is generated, wherein when a floating-point instruction is generated, a floating-point register is selected from a specific group or a specific group set of the multiple groups as an operand of the floating-point instruction according to a floating-point type of an operand specified by the floating-point instruction, and the operand includes a source operand and / or a target operand of the floating-point instruction.

[0010] Optionally, when a floating-point register is selected as only a source operand for the floating-point instruction, the specific group or specific group set includes:

[0011] A group of corresponding floating-point types that are the same as the floating-point types of the source operands specified by the floating-point instruction; and

[0012] A group whose corresponding floating-point type has a precision smaller than the precision of the floating-point type of the source operand specified by the floating-point instruction.

[0013] Optionally, when a floating-point register only as a target operand is selected for the floating-point instruction, the specific group or specific group set includes:

[0014] The corresponding floating-point type is the same group as the floating-point type of the target operand specified by the floating-point instruction.

[0015] Optionally, when a floating-point register is selected as both a source operand and a target operand for the floating-point instruction, the specific group or specific group set includes:

[0016] The corresponding floating-point type is the same group as the floating-point type of the source operand specified by the floating-point instruction.

[0017] Optionally, the method further includes: obtaining a floating-point type of an operand specified by the floating-point instruction, wherein the obtaining the floating-point type of the operand specified by the floating-point instruction:

[0018] The floating-point type of the source operand specified by the floating-point instruction is determined according to the instruction type of the floating-point instruction; and the floating-point type of the target operand specified by the floating-point instruction is determined according to the instruction type of the floating-point instruction and the floating-point type of the source operand specified by the floating-point instruction.

[0019] Optionally, the method further includes: obtaining the floating-point type of the operand specified by the floating-point instruction from a template file.

[0020] Optionally, the processing unit to be tested adopts the RISC-V instruction set.

[0021] Optionally, the multiple floating-point types include: single precision, multiple precision, double precision, and quadruple precision.

[0022] Optionally, the method further includes: when the instruction sequence is executed by the processing unit to be tested, outputting indication information for illegal instructions.

[0023] In a second aspect, an embodiment of the present disclosure provides a processing unit, including:

[0024] an instruction fetch unit for retrieving computer instructions from a memory external to the processing unit;

[0025] an instruction decoding unit for decoding the retrieved computer instructions;

[0026] An instruction execution unit, configured to execute the decoded computer instructions to perform:

[0027] Dividing the floating-point registers of the processing unit to be tested into a plurality of groups, wherein the plurality of groups respectively correspond to a plurality of floating-point types supported by the instruction set of the processing unit to be tested;

[0028] Initialize each floating-point register with a random value according to the floating-point type of the group to which it belongs;

[0029] The instruction sequence is generated, wherein when a floating-point instruction is generated, a floating-point register is selected from a specific group or a specific group set of the multiple groups as an operand of the floating-point instruction according to a floating-point type of an operand specified by the floating-point instruction, and the operand includes a source operand and / or a target operand of the floating-point instruction.

[0030] Optionally, when registers that are only source operands are selected for the floating-point instruction, the specific group or specific group set includes:

[0031] A group of corresponding floating-point types that are the same as the floating-point types of the source operands specified by the floating-point instruction; and

[0032] A group whose corresponding floating-point type has a precision smaller than the precision of the floating-point type of the source operand specified by the floating-point instruction.

[0033] Optionally, when a floating-point register only as a target operand is selected for the floating-point instruction, the specific group or specific group set includes:

[0034] The corresponding floating-point type is the same group as the floating-point type of the target operand specified by the floating-point instruction.

[0035] Optionally, when a floating-point register is selected as both a source operand and a target operand for the floating-point instruction, the specific group or specific group set includes:

[0036] The corresponding floating-point type is the same group as the floating-point type of the source operand specified by the floating-point instruction.

[0037] Optionally, the processing unit adopts the RISC-V instruction set.

[0038] Optionally, the multiple floating-point types include: single precision, multiple precision, double precision, and quadruple precision.

[0039] Optionally, when the instruction sequence is executed by the processing unit to be tested, indication information is output for illegal instructions.

[0040] In a third aspect, an embodiment of the present disclosure provides a computing device, comprising a memory and a processor, wherein the memory further stores computer instructions executable by the processor, and when the computer instructions are executed, the method of randomly generating an instruction sequence described in any one of the above items is implemented.

[0041] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable medium, wherein the computer-readable medium stores computer instructions executable by an electronic device, and when the computer instructions are executed, the method of randomly generating an instruction sequence described in any one of the above items is implemented.

[0042] Based on the embodiments of the present disclosure, multiple floating-point registers are divided into multiple groups. Then, when generating a floating-point instruction, a specific group or a specific group set is determined from the multiple groups based on the floating-point type of the required operand, and a floating-point register is selected from the specific group or the specific group set as the operand of the floating-point instruction. The floating-point instruction generated in this way will not generate NaN when executed by the processing unit to be tested, thereby solving the problems existing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0044] Figure 1 It is a conceptual diagram of random testing of instructions;

[0045] Figure 2 It is a structural diagram of a general computer architecture;

[0046] Figure 3 It is a schematic diagram of the structure of an embedded processor;

[0047] Figure 4 It is a flowchart of a method for randomly generating an instruction sequence according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0049] The following terms are used in this article.

[0050] Emulator: A program that simulates the functions and instruction system of a hardware processor through software, enabling a computer or other multimedia platform (handheld computer, mobile phone) to run software on other platforms.

[0051] Instruction set (instruction set architecture): is a set of instructions used to calculate and control the operation of the processor. Each new type of processor specifies a series of instruction sets that cooperate with other hardware circuits during design.

[0052] Microarchitecture: Microarchitecture, also known as microarchitecture / microprocessor architecture, is the way a given instruction set architecture is executed in a processor in computer engineering. A given instruction set can be executed in different microarchitectures. The implementation may vary depending on different design purposes and technological improvements. Usually, what we call computer architecture is a combination of microarchitecture and instruction set architecture.

[0053] NaN: A special representation used to handle error conditions that occur during calculations, such as dividing 0.0 by 0.0 or finding the square root of a negative number. The significance of using special NaN to express the above calculation errors is to avoid unnecessary termination of calculations due to these errors. For example, if a floating-point calculation method called by a loop may cause these errors due to input parameter problems, NaN makes it possible to simply continue executing the loop to perform those calculations without errors even if such an error occurs in a certain loop.

[0054] Floating-point instructions: are instructions for performing operations such as calculations, comparisons, and transfers on floating-point data. Floating-point instructions generally require 1 or 2 operands. When two operands are required, the instruction format specified by the floating-point instruction is:

[0055] Instruction type Floating point type of source operand Floating point type of destination operand;

[0056] When only one operand is required, this operand can be a source operand or a destination operand, and the instruction format specified by the floating-point instruction is:

[0057] The instruction type source operand's floating-point type, or the instruction type destination operand's floating-point type.

[0058] Application Scenario

[0059] Figure 11 is a schematic diagram of a scenario of random instruction testing. Referring to the figure, a random instruction sequence generator 1011 is used to randomly generate instruction sequences, and a simulator 1021 simulates the processor to be tested to parse and execute the instruction sequences. Computing devices 101 and 102 are used to deploy the random instruction sequence generator 1011 and the simulator 1021, respectively.

[0060] The computing devices 101 and 102 may be computer systems. The instruction set architecture of the computer system may be a complex instruction set (CISC) architecture, a reduced instruction set (RISC) architecture, a very long instruction set (VLIW) architecture, or a combination of the above instruction sets. The hardware architecture of the computer system may be, for example, Figure 2 As shown in the figure, it includes one or more processors 12 and a memory 14.

[0061] The memory 14 may be a main memory (hereinafter referred to as main memory or internal memory), which is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor 12, and may also be used to implement data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0062] In some cases, the processor 12 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed gap between the processor 12 and the memory 14, the computer system 300 also includes a cache memory 18 coupled to the bus 11, and the cache memory 18 is used to cache some program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1Cache), a second-level cache (L2Cache) and a third-level cache (L3Cache), or a cache structure of more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor 12 or integrated with the processor 12 in the same system on a chip.

[0063] The processor 12 may include an instruction fetch unit 121, an instruction decoding unit 122, an instruction execution unit 123, and the like. The instruction fetch unit 121 is used to retrieve computer instructions from an external memory. The instruction decoding unit 122 decodes the retrieved computer instructions. The instruction execution unit 123 is used to execute the decoded computer instructions to complete a specified operation.

[0064] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0065] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processor 12 needs to access the memory, it first accesses the cache memory 18 via the bus 11 to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processor 12 directly calls the content to be accessed from the cache memory 18; if the content that the processor 12 needs to access is not in the cache memory 18, the cache memory 18, the processor 12 needs to access the memory 14 via the bus 11 to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processor 12 can be significantly improved, thereby improving the performance and efficiency of the entire computer system 300.

[0066] In addition, the architecture may also include input / output devices such as a storage device 16, a display device 13, an audio device 19, and a mouse / keyboard 15. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, and other devices for information access coupled to the bus 11 through a corresponding interface. The display device 13 is, for example, coupled to the bus 11 through a corresponding graphics card, and is used to display according to a display signal provided by the bus 11.

[0067] The architecture also typically includes a communication device 17, so that it can communicate with a network or other devices in various ways. The communication device 17 may include, for example, one or more communication modules. As an example, the communication device 17 may include a wireless communication module suitable for a specific wireless communication protocol. For example, the communication device 17 may include a WLAN module for implementing Wi-FiTM communication in accordance with the 802.11 standard established by the Institute of Electrical and Electronics Engineers (IEEE); the communication device 17 may also include a WWAN module for implementing wireless wide area communication in accordance with cellular or other wireless wide area protocols; the communication device 17 may also include a communication module using other protocols such as a Bluetooth module, or other custom types of communication modules; the communication device 17 may also be a port for serial transmission of data.

[0068] Of course, the architecture may vary depending on the motherboard, operating system, and instruction set architecture, so I will not describe it here.

[0069] The computing devices 101 and 102 may be deployed with an integrated development environment, so that the R&D personnel can compile and run the random instruction sequence generator 1011 and the simulator 1021 at any time. The random instruction sequence generator 1011 and the simulator 1021 may be stored in the memory 14 as software programs, and parsed and executed by the processors of the computing devices 101 and 102. The random instruction sequence generator 1011 may randomly generate instruction sequences. The simulator 1021 simulates the behavior and function of the processing unit 1031 to be tested, that is, the instruction sequence is a computer instruction applicable to the processing unit 1031 to be tested. The processor of the computing device 102 cannot directly parse and execute the instruction sequence. The instruction sequence must be translated by the simulator 1021 before it can be parsed and executed by the processor of the computing device 102, and the test result 1 is output.

[0070] The processing unit 1031 to be tested can be various types of processing units in theory. However, with the development of ultra-large-scale integrated circuit technology and the continuous improvement of integrated circuit process level, embedded processors have been fully developed in various application systems. At present, embedded processors have been widely used in the fields of communication equipment, network equipment, transportation, Internet of Things products, etc. Moreover, instruction random testing is currently widely used in the testing and verification of embedded processors. In addition, embedded processors mostly use RISC-V, which also contributes to the widespread application of embedded processors. The following is an example of an embedded processor.

[0071] Figure 3 A block diagram showing an embedded processor.

[0072] The embedded processor 300 includes an arithmetic logic unit (ALU) 301, a register 302, and a control unit 303. The arithmetic logic unit 301 performs actual operation processing. The register 302 is used to store instructions and intermediate results in the operation processing. The control unit 303 controls access to the external RAM 304 and flash memory 305.

[0073] When executing the instruction to be executed, the arithmetic logic unit 301 moves the instruction to be executed from the RAM 304 or the flash memory 305 to the register 302, and receives the next instruction fetch address or calculates the next instruction fetch address according to the instruction fetch algorithm. The instruction fetch algorithm includes, for example: increasing the address or decreasing the address according to the instruction length.

[0074] After fetching the instruction, the arithmetic logic unit 301 enters the instruction decoding stage, in which it decodes the fetched instruction according to the predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the execution of the instruction. The operand acquisition information, for example, points to the address in the RAM 304 or the flash memory 305. After decoding, the ALU obtains the operand stored in the RAM 304 or the flash memory 305 according to the operand acquisition information and performs processing.

[0075] When executing certain instructions (such as memory access instructions), the arithmetic logic unit 301 needs to access the RAM 304 or the flash memory 305 to obtain the information stored therein or provide data that needs to be written into the RAM 304 or the flash memory 305 .

[0076] After the memory access instruction is obtained by the arithmetic logic unit 301, the arithmetic logic unit 301 can decode the memory access instruction so that the source operand of the memory access instruction can be obtained. The arithmetic logic unit 301 can perform corresponding operations on the source operand of the memory access instruction (for example, the arithmetic logic unit operates the source operand stored in the register) to obtain the address information corresponding to the memory access instruction, and initiate a corresponding request according to the address information, such as an address translation request, a write access request, etc.

[0077] When implementing random instruction testing, the processing unit 1031 to be tested usually needs to be installed on a driver device, and the driver device drives the processing unit 1031 to be tested to work, such as the demo board 103 shown in the figure. The development board 103 may have various interface units, such as I2C bus, serial peripheral interface (SPI), universal serial bus (USB), general-purpose input / output (GPIO), parallel interface, network card interface and Bluetooth UART. The processing unit 1031 to be tested is connected to other devices through the interface unit, for example, through the interface unit to connect to Figure 3 The RAM 304 and the flash memory 305 on the development board. According to the test requirements, the development board can also include software resources such as an integrated development environment and software source code, and developers can use the integrated development environment to write test cases to test the processing unit 1031 under test.

[0078] After the development board 103 and the processing unit to be tested 1031 are deployed, the processing unit to be tested 1031 can receive the instruction sequence via the interface unit of the development board 103, parse and execute the instruction sequence, and output the test result 2. When the instruction sequence is executed by the processing unit to be tested 1031, indication information can be output for illegal instructions. For example, when the processing unit to be tested 1031 executes an illegal instruction, it outputs a text message of "this type of illegal instruction" and gives a specific reason and a correct instruction, and outputs it in the test result 2.

[0079] The comparison program 104 is used to compare the test result 1 and the test result 2. The test result 1 can be used as a reference to evaluate whether the random test of the instruction for the processing unit to be tested 1031 is correct. The correct test result should include various situations to reflect the randomness of the test process.

[0080] Methods of the embodiments of the present disclosure

[0081] In order to avoid the test results from including a large number of NaNs, the present disclosure provides a method for randomly generating instruction sequences applied to the random instruction sequence generator 1011. Figure 4 As shown, the method includes steps S401-S403.

[0082] In step S401, the floating-point registers of the processing unit to be tested are divided into a plurality of groups, wherein the plurality of groups respectively correspond to a plurality of floating-point types supported by the instruction set of the processing unit to be tested.

[0083] In this step, the floating-point registers (including quantity, identification, address, etc.) used by the processing unit under test in the floating-point instructions are first determined, and then these floating-point registers are divided into multiple groups according to the floating-point types supported by the instruction set of the processing unit under test, each group corresponds to a floating-point type, and each register belongs to one group.

[0084] In step S402, each floating point register is initialized with a random value according to the floating point type corresponding to the group to which it belongs.

[0085] In this step, the floating-point registers in each group are initialized to a random value according to the floating-point type of the group to which the register belongs.

[0086] In step S403, an instruction sequence is generated, wherein when generating a floating-point instruction, a floating-point register is selected from a specific group or a specific group set in a plurality of groups as an operand of the floating-point instruction according to the floating-point type of the operand specified by the floating-point instruction. The operand of the floating-point instruction includes a source operand and / or a target operand.

[0087] In this step, the instruction sequence is usually generated according to the template file. The template file can describe information such as the instruction type, input and output, such as indicating the instruction type, the floating-point type of the source operand and the floating-point type of the target operand. Of course, some floating-point instructions have only source operands or only target operands, and some floating-point instructions have only one operand, but the operand serves as both the source operand and the target operand. When generating a floating-point instruction, the instruction type is first determined according to the template file, and then the floating-point type of the source operand or / target operand specified by the floating-point instruction is obtained. Specifically, after the instruction type is determined, if the template file does not specify the floating-point type of the source operand and the target operand, it can usually be determined according to the instruction type. For example, FADD.H represents a single-precision floating-point addition operation, that is, the source operand and the target operand specified by it are both single-precision floating-point numbers, and FADD.D represents a double-precision floating-point addition operation, that is, the source operand and the target operand specified by it are both double-precision floating-point numbers. If the instruction type is applicable to multiple floating-point types, for example, FSUB can be a subtraction operation for any one of half-precision, single-precision, double-precision, and quadruple-precision, then the template file usually specifies the floating-point type of the specified source operand and the target operation data, or, by default, the floating-point type of the source operand can be arbitrarily selected, and then the floating-point type of the target operand can be derived according to the instruction type and the floating-point type of the specified source operand. After the floating-point type of the specified source operand and / or the target operand is determined, the floating-point register is selected as the operand from the specific group or the specific group set according to the floating-point type of the specified source operand and the target operand. This requires selecting a specific group or a specific group set from the multiple groups in step S402. The simplest selection method is to compare the floating point type of the specified source operand or target operand with the floating point type corresponding to each group, and use the group with the same floating point type as the specific group for selecting the source operand or target operand.

[0088] But the disclosed embodiments are not only that. It is mentioned in the background technology that the micro-architecture uses a unified maximum bit register to store various floating-point types, and when the floating-point width is less than the floating-point register width, the insufficient part is filled with '1' in the high position (this method is called nanbox). In this way, the '1' contained in the high position of the floating-point number with higher precision is less than the floating-point number with lower precision when stored in the register. Therefore, when a floating-point number with lower precision is needed, if a floating-point number with higher precision is used instead, the micro-architecture will confirm the floating-point number with higher precision as an illegal value during execution, but a floating-point number with lower precision can be used to replace the floating-point number with higher precision. At this time, the micro-architecture will not find that the floating-point number with lower precision has more '1' in the high position than the floating-point number with higher precision, so it will not be identified as an illegal value. In other words, for floating-point instructions, with respect to source operands, if the precision of the specified source operand is K, a floating-point type with a precision equal to or less than K can actually be used as the source operand, and K is a positive integer.

[0089] Based on this, in this step, when generating a floating-point instruction, for the source operand, a floating-point register can be selected from a group whose corresponding floating-point type has a lower precision than the floating-point type of the specified source operand as the source operand of the floating-point instruction. However, this cannot be done for the target operand. For the target operand, the only selection method is to compare the floating-point type of the specified target operand with the floating-point type corresponding to each group, and use the group with the same floating-point type as the specific group for selecting the target operand.

[0090] Furthermore, when generating a floating-point instruction, if the operand is both a source operand and a target operand, in this case, the floating-point types of the source operand and the target operand specified by the floating-point instruction are the same, so the only selection method is: compare the floating-point type of the source operand specified by the floating-point instruction with the floating-point type corresponding to each group, and use the group with the same floating-point type as the specific group for selecting the operation data.

[0091] In summary, when a floating-point register is selected as only a source operand for a floating-point instruction, the specific group or specific group set selected therefrom includes: a group whose corresponding floating-point type is the same as the floating-point type of the source operand specified by the floating-point instruction, and a group whose corresponding floating-point type has a precision smaller than the precision of the floating-point type of the source operand specified by the floating-point instruction; when a register is selected as only a target operand for a floating-point instruction, the specific group or specific group set of floating-point registers selected therefrom includes: a group whose corresponding floating-point type is the same as the floating-point type of the target operand specified by the floating-point instruction; when a floating-point register is selected as both a source operand and a target operand for a floating-point instruction, the specific group or specific group set of registers selected therefrom includes: a group whose corresponding floating-point type is the same as the floating-point type of the source operand specified by the floating-point instruction.

[0092] In summary, based on the embodiments of the present disclosure, multiple floating-point registers are divided into multiple groups and an initial value is assigned to each floating-point register. Then, when generating a floating-point instruction, a specific group or a specific group set is determined from the multiple groups based on the floating-point type of the required operand, and a floating-point register is selected from the specific group or the specific group set as the operand of the floating-point instruction. The floating-point instruction generated in this way will not generate NaN when executed by the processing unit to be tested, thereby solving the problems existing in the prior art.

[0093] Further, based on the micro-architecture's processing method for register operands of floating-point instructions, the allocation of source operands is not completely limited to a group of registers, but can be extended to registers of other groups, so as to improve the processing efficiency of randomly generated instruction sequences. It should be noted that the micro-architecture-based processing method for register operands of floating-point instructions includes: the micro-architecture uses a unified maximum bit width register to store various floating-point types, and when the floating-point number width is less than the floating-point register width, the insufficient part is filled with '1' in the high position (this method is called nanbox). This processing method is a general processing method. In this way, for higher-precision floating-point instructions, lower-precision floating-point numbers can be used to replace higher-precision floating-point numbers. Therefore, the disclosed embodiments are feasible for processing units using this technology.

[0094] The present embodiment is further described below using a hypothetical example. Assume that the unit under test has 32 floating point registers. According to the precision from small to large, the floating point types include half precision (K), single precision (S), double precision (D), and quadruple precision (Q).

[0095] First, according to an embodiment of the present disclosure, the floating-point registers are divided into four groups, corresponding to half precision (K), single precision (S), double precision (D), and quadruple precision (Q), respectively.

[0096] Then, all floating-point registers are initialized with random values. The random value of each register should match the floating-point type of the group to which the register belongs.

[0097] Typically, floating-point numbers of half precision (K), single precision (S), double precision (D), and quadruple precision (Q) occupy 2 bytes, 4 bytes, 16 bytes, and 32 bytes of storage space, respectively. Of course, different instruction set architectures can give storage spaces of different lengths for the same floating-point type. For example, with the improvement of semiconductor processes and the integration of integrated circuits, single-precision floating-point types have begun to use 32-bit storage space. However, it should be understood that this difference does not affect the various embodiments of the present disclosure. Assuming that the floating-point registers are unified as 64-bit registers, when such registers are used to store the above-mentioned floating-point types, the microarchitecture will automatically fill the high bits of the registers with '1'. Of course, when initializing the registers, it is also possible to first fill each bit of all registers with '1', and then store the corresponding random floating-point numbers in the corresponding floating-point registers.

[0098] Finally, when randomly generating floating-point instructions, different groups of floating-point registers are allocated according to the instruction type and the floating-point type of the required operands. Specifically, for the source operand, if a half-precision floating-point register is required, the K register can be used. If a single-precision floating-point register is required, the K and S registers can be used. If a double-precision floating-point register is required, the K, S, and D registers can be used. If a quad-precision floating-point register is required, the K, S, D, and Q registers can be used. For the destination register or both the source and destination registers, if a half-precision floating-point register is required, only the K register can be used, if a single-precision floating-point register is required, only the S register can be used, if a double-precision floating-point register is required, only the D register can be used, and if a quad-precision floating-point register is required, only the Q register can be used.

[0099] It is mentioned above that a template file can be used to define various instructions. The following is a portion of data of an exemplary template file, as shown in Table 1.

[0100]

[0101]

[0102] The first line of data indicates the floating point instruction for adding two f32 (32-bit floating point type) floating point data, the second line of data indicates the floating point instruction for adding two f80 (80-bit floating point type) floating point data, the fourth line of data indicates the floating point instruction for dividing two f32 (32-bit floating point type) floating point data, etc. For example, the first line of data generates the following instruction:

[0103] mov eax,5;

[0104] mov ebx,6;

[0105] add eax,ebx;

[0106] The first line of instruction code indicates that the random number '5' is stored in register eax, the second line of instruction indicates that the random number '6' is stored in register ebx, and the third line of instruction indicates that the data in the two registers are added. However, it should be noted that the instructions used to implement the above operations in different programming languages ​​are not the same.

[0107] The commercial value of the disclosed embodiments

[0108] The disclosed embodiments can improve the reliability and correctness of random instruction testing. The disclosed embodiments can be implemented in various terminals and servers in the form of computer instructions and used in the test verification phase of chip R&D projects, which can help reduce the workload of testers and reduce testing costs. Therefore, the disclosed embodiments have practical value and economic value.

[0109] Those skilled in the art will appreciate that the present disclosure may be implemented as systems, methods, and computer program products. Therefore, the present disclosure may be specifically implemented in the following forms, namely complete hardware, complete software (including firmware, resident software, microcode), and may also be implemented in the form of a combination of software and hardware. In addition, in some embodiments, the present disclosure may also be implemented in the form of a computer program product in one or more computer-readable media, which contains computer-readable program code.

[0110] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination thereof. More specific examples of computer-readable storage media include: an electrical connection of one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this article, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by a processing unit, a device or a device, or used in combination with the program.

[0111] Computer readable signal media may include data signals propagated in baseband or as part of a chopped wave, which carry computer readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any other suitable combination. Computer readable signal media may also be any computer readable medium other than a computer readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction system, apparatus, or device.

[0112] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., and any suitable combination of the foregoing.

[0113] The computer program code for executing the disclosed embodiments may be written in one or more programming languages ​​or combinations. The programming languages ​​include object-oriented programming languages, such as JAVA, C++, and may also include conventional procedural programming languages, such as C. The program code may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet).

[0114] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for randomly generating an instruction sequence to be executed by a processing unit to be tested, comprising: Dividing the floating-point registers of the processing unit to be tested into a plurality of groups, wherein the plurality of groups respectively correspond to a plurality of floating-point types supported by the instruction set of the processing unit to be tested; Initialize each floating-point register with a random value according to the floating-point type of the group to which it belongs; The instruction sequence is generated, wherein when a floating-point instruction is generated, a floating-point register is selected from a specific group or a specific group set of the multiple groups as an operand of the floating-point instruction according to a floating-point type of an operand specified by the floating-point instruction, and the operand includes a source operand and / or a target operand of the floating-point instruction.

2. The method according to claim 1, wherein: When only floating-point registers as source operands are selected for the floating-point instruction, the specific group or specific group set comprises: A group of corresponding floating-point types that are the same as the floating-point types of the source operands specified by the floating-point instruction; and A group whose corresponding floating-point type has a precision smaller than the precision of the floating-point type of the source operand specified by the floating-point instruction.

3. The method according to claim 1, wherein: When only floating-point registers as target operands are selected for the floating-point instruction, the specific group or specific group set comprises: The corresponding floating-point type is the same group as the floating-point type of the target operand specified by the floating-point instruction.

4. The method according to claim 1, wherein: When a floating-point register is selected as both a source operand and a target operand for the floating-point instruction, the specific group or specific group set includes: The corresponding floating-point type is the same group as the floating-point type of the source operand specified by the floating-point instruction.

5. The method according to claim 1, further comprising: Obtaining the floating-point type of the operand specified by the floating-point instruction, wherein obtaining the floating-point type of the operand specified by the floating-point instruction: The floating-point type of the source operand specified by the floating-point instruction is determined according to the instruction type of the floating-point instruction; and the floating-point type of the target operand specified by the floating-point instruction is determined according to the instruction type of the floating-point instruction and the floating-point type of the source operand specified by the floating-point instruction.

6. The method according to claim 1, further comprising: The floating-point type of the operand specified by the floating-point instruction is obtained from the template file.

7. The method according to claim 1, wherein: The processing unit to be tested adopts the RISC-V instruction set.

8. The method according to any one of claims 1 to 7, wherein: The multiple floating point types include: single precision, multiple precision, double precision, and quadruple precision.

9. The method according to claim 1, further comprising: When the instruction sequence is executed by the processing unit to be tested, indication information is output for illegal instructions.

10. A processing unit, comprising: an instruction fetch unit for retrieving computer instructions from a memory external to the processing unit; an instruction decoding unit for decoding the retrieved computer instructions; An instruction execution unit, configured to execute the decoded computer instructions to perform: Dividing the floating-point registers of the processing unit to be tested into a plurality of groups, wherein the plurality of groups respectively correspond to a plurality of floating-point types supported by the instruction set of the processing unit to be tested; Initialize each floating-point register with a random value according to the floating-point type of the group to which it belongs; An instruction sequence is generated, wherein when a floating-point instruction is generated, a floating-point register is selected from a specific group or a specific group set of the multiple groups as an operand of the floating-point instruction according to a floating-point type of an operand specified by the floating-point instruction, and the operand includes a source operand and / or a target operand of the floating-point instruction.

11. The processing unit according to claim 10, wherein: When registers are selected as source operands only for the floating-point instruction, the specific group or specific set of groups includes: A group of corresponding floating-point types that are the same as the floating-point types of the source operands specified by the floating-point instruction; and A group whose corresponding floating-point type has a precision smaller than the precision of the floating-point type of the source operand specified by the floating-point instruction.

12. The processing unit according to claim 10, wherein: When only floating-point registers as target operands are selected for the floating-point instruction, the specific group or specific group set comprises: The corresponding floating-point type is the same group as the floating-point type of the target operand specified by the floating-point instruction.

13. The processing unit according to claim 10, wherein: When a floating-point register is selected as both a source operand and a target operand for the floating-point instruction, the specific group or specific group set includes: The corresponding floating-point type is the same group as the floating-point type of the source operand specified by the floating-point instruction.

14. The processing unit according to claim 10, wherein: The processing unit adopts the RISC-V instruction set.

15. The processing unit according to claim 10, wherein: The multiple floating point types include: single precision, multiple precision, double precision, and quadruple precision.

16. The processing unit according to claim 10, wherein: When the instruction sequence is executed by the processing unit to be tested, indication information is output for illegal instructions.

17. A computing device comprising a memory and a processor, wherein the memory further stores computer instructions executable by the processor, and when the computer instructions are executed, the method for randomly generating an instruction sequence as claimed in any one of claims 1 to 9 is implemented.

18. A computer-readable medium storing computer instructions executable by an electronic device, wherein when the computer instructions are executed, the method for randomly generating an instruction sequence as claimed in any one of claims 1 to 9 is implemented.

Images