Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure includes: a substrate having a dielectric layer thereon, the substrate including a first region; a first opening located in the dielectric layer of the first region; a first work function layer located on the bottom and sidewalls of the first opening, the top surface of the first work function layer being lower than the top surface of the dielectric layer; a second work function layer and a third work function layer located on the surface of the first work function layer in the first opening and on the sidewalls of the first opening, the top surfaces of the second work function layer and the third work function layer being lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer; a fourth work function layer located on the surface of the third work function layer in the first opening and on the sidewalls of the first opening; and a gate layer located in the first opening. The performance of the semiconductor structure provided by the embodiments of the present invention is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In the field of integrated circuit manufacturing, as the size of transistors continues to shrink, the impact of the physical limits of devices on device fabrication is becoming increasingly significant, and it has become more difficult to scale down the feature size of devices proportionally. Among them, the difficulty in the field of transistor and circuit manufacturing has also increased significantly.

[0003] In order to meet the requirements, it is necessary to form transistors with different functions on the same substrate. In the prior art, a work function layer is used to adjust the performance of transistors formed by the post-metal gate process to meet the requirements of different functional transistors.

[0004] However, the performance of existing transistors still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of transistors.

[0006] To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate having a dielectric layer thereon, the substrate including a first region; a first opening located in the dielectric layer of the first region; a first work function layer located on the bottom and sidewalls of the first opening, and the top surface of the first work function layer being lower than the top surface of the dielectric layer; a second work function layer located on the surface of the first work function layer in the first opening and on the sidewalls of the first opening, the top surface of the second work function layer being lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer; a third work function layer located on the surface of the second work function layer in the first opening, the top surface of the third work function layer being flush with the top surface of the second work function layer; a fourth work function layer located on the surface of the third work function layer in the first opening and on the sidewalls of the first opening, the top surface of the fourth work function layer being flush with the top surface of the dielectric layer; and a gate layer located in the first opening.

[0007] Optionally, the substrate further includes a second region, a third region, and a fourth region, and second openings, third openings, and fourth openings are respectively formed in the dielectric layers of the second region, the third region, and the fourth region; the second work function layer is further located on the bottom and sidewalls of the second opening; the third work function layer is further located on the bottom and sidewalls of the second opening and the third opening; the fourth work function layer is further located on the bottom and sidewalls of the second opening, the third opening, and the fourth opening; and the gate layer is further located in the second opening, the third opening, and the fourth opening.

[0008] Optionally, the height range from the top surface of the first work function layer to the top surface of the substrate is

[0009] Optionally, the height range from the top surface of the second work function layer to the top surface of the substrate is

[0010] Optionally, the materials of the first work function layer, the second work function layer, and the third work function layer are P-type work function materials; or, the materials of the first work function layer, the second work function layer, and the third work function layer are N-type work function materials; the P-type work function materials include titanium nitride; the N-type work function materials include titanium aluminum.

[0011] Optionally, the work function type of the fourth work function layer is opposite to that of the first work function layer, the second work function layer, and the third work function layer, and the material of the fourth work function layer is an N-type work function material; or, the fourth work function layer is a P-type work function material.

[0012] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, a dielectric layer is formed on the substrate, and the substrate includes a first region; forming a first opening in the dielectric layer in the first region; forming a first work function layer on the bottom and part of the side walls of the first opening, the top surface of the first work function layer is lower than the top surface of the dielectric layer; forming a second work function layer on the surface of the first work function layer in the first opening and on the side walls of the first opening, the top surface of the second work function layer is lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer; forming a third work function layer on the surface of the second work function layer in the first opening, the top surface of the third work function layer is flush with the top surface of the second work function layer; forming a fourth work function layer on the surface of the third work function layer in the first opening and on the side walls of the first opening; forming a gate layer in the first opening.

[0013] Optionally, the substrate further includes a second region, a third region, and a fourth region; forming a second opening, a third opening, and a fourth opening in the dielectric layer in the second region, the third region, and the fourth region respectively; when forming the first work function layer on the bottom and part of the side walls of the first opening, it further includes: forming the first work function layer on the bottom and part of the side walls of the second opening, the third opening, and the fourth opening.

[0014] Optionally, the method for forming a first work function layer on the bottoms and partial sidewalls of the first opening, second opening, third opening, and fourth opening includes: forming a first work function material layer on the bottoms and sidewalls of the first opening, second opening, third opening, and fourth opening, and on the dielectric layer; forming a first sacrificial material layer on the first work function material layer, with the top surface of the first sacrificial material layer being higher than the top surface of the dielectric layer; etching the first sacrificial material layer until the top surface of the first sacrificial material layer is lower than the top surface of the dielectric layer, forming a first sacrificial layer; etching the first work function material layer until the top surface of the first work function material layer is flush with the top surface of the first sacrificial layer, forming a first work function layer; removing the first sacrificial layer.

[0015] Optionally, after forming the first work function layer on the bottoms and partial sidewalls of the first opening, second opening, third opening, and fourth opening, further included are: removing the first work function layer in the second opening; forming a second work function material layer on the bottoms and sidewalls of the first opening, second opening, third opening, and fourth opening; removing the second work function material layer and the first work function layer in the third opening; forming a third work function material layer on the bottoms and sidewalls of the first opening, second opening, third opening, and fourth opening; removing the third work function material layer, the second work function material layer, and the first work function layer in the fourth opening.

[0016] Optionally, the method for forming the second work function layer and the third work function layer includes: after removing the third work function material layer, the second work function material layer, and the first work function layer in the fourth opening, forming a second sacrificial material layer in the first opening, second opening, third opening, and fourth opening, with the top surface of the second sacrificial material layer being higher than the top surface of the dielectric layer; etching the second sacrificial material layer until the top surface of the second sacrificial material layer is lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer, forming a second sacrificial layer; etching the second work function material layer and the third work function material layer until the top surfaces of the second work function material layer and the third work function material layer are flush with the top surface of the second sacrificial layer, forming the second work function layer and the third work function layer.

[0017] Optionally, before forming the first work function material layer on the bottoms and sidewalls of the first opening, second opening, third opening, and fourth opening, further included are: forming a gate dielectric layer on the bottoms and sidewalls of the first opening, second opening, third opening, and fourth opening; forming a barrier layer on the gate dielectric layer; forming an etch stop layer on the barrier layer, and the first work function material layer is located on the etch stop layer.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] The forming method provided by the embodiment of the present invention, on the one hand, forms a first work function layer with a top surface lower than the top surface of the dielectric layer, increasing the width at the top of the first opening and enlarging the process window; on the other hand, forms a second work function layer and a third work function layer in the first opening with top surfaces lower than the dielectric layer and higher than the top surface of the first work function layer, providing space for forming a gate layer in the first opening, thereby reducing the resistance of the formed semiconductor structure and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1 to 8 is a schematic structural diagram of a forming method of a semiconductor structure in an embodiment;

[0021] Figures 9 to 25 is a schematic structural diagram corresponding to each step of the forming method of the semiconductor structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] As described in the background art, the performance of existing transistors still needs to be improved. Specific embodiments are now combined for analysis and explanation.

[0023] Figures 1 to 8 is a schematic structural diagram of a forming method of a semiconductor structure in an embodiment.

[0024] Referring to Figure 1 , a substrate 100 is provided, a dielectric layer 101 is formed on the substrate 100, and the substrate includes a first region I, a second region II, a third region III, and a fourth region IV; first openings 102, second openings 103, third openings 104, and fourth openings 105 are respectively formed in the dielectric layer 101 in the first region I, the second region II, the third region III, and the fourth region IV; a gate dielectric layer 106, a barrier layer 107, an etch stop layer 108, and a first work function material layer 109 are sequentially formed on the sidewalls and top surfaces of the first openings 102, second openings 103, third openings 104, and fourth openings 105; a first sacrificial layer 110 is formed in the first openings 102, second openings 103, third openings 104, and fourth openings 105; a first photoresist layer 111 is formed on the first sacrificial layer 110, and the first photoresist layer 111 exposes the second region II.

[0025] Referring to Figure 2 , using the first photoresist layer 111 as a mask, the first sacrificial layer 110 and the first work function material layer 109 in the second region II are etched away.

[0026] Referring to Figure 3, the first photoresist layer 111 and the first sacrificial layer 110 are removed; a second work function material layer 112 is formed on the bottoms and sidewalls of the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105; a second sacrificial layer 113 is formed within the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105; a second photoresist layer 114 is formed on the second sacrificial layer 113, and the second photoresist layer 114 exposes the third region III.

[0027] Reference Figure 4 , using the second photoresist layer 114 as a mask, the second sacrificial layer 113, the second work function material layer 112, and the first work function material layer 109 in the third region III are etched away.

[0028] Reference Figure 5 , the second photoresist layer 114 and the second sacrificial layer 113 are removed; a third work function material layer 115 is formed on the bottoms and sidewalls of the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105; a third sacrificial layer 116 is formed within the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105; a third photoresist layer 117 is formed on the third sacrificial layer 116, and the third photoresist layer 117 exposes the fourth region IV.

[0029] Reference Figure 6 , using the third photoresist layer 117 as a mask, the third sacrificial layer 116 in the fourth region IV is etched away.

[0030] Reference Figure 7 , the third work function material layer 115, the second work function material layer 112, and the first work function material layer 109 in the fourth region IV are etched away; the third photoresist layer 117 and the third sacrificial layer 116 are removed.

[0031] Reference Figure 8 , a fourth work function material layer 118 is formed on the bottoms and sidewalls of the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105; a gate layer 119 is formed within the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105.

[0032] The first region I, the second region II, the third region III, and the fourth region IV of the semiconductor structure need to form devices with different threshold voltages to meet the diverse requirements of device performance. Therefore, work function structures with different thicknesses need to be formed on the first region I, the second region II, the third region III, and the fourth region IV. However, as the size of the transistor continues to shrink and the feature size of the device becomes smaller and smaller, when forming work function structures with different thicknesses using the above method, due to the limited gate size, the widths of the first opening 102, the second opening 103, the third opening 104, and the fourth opening 105 formed are small. The gate dielectric layer 106, the barrier layer 107, and the etch stop layer 108 formed in the gate opening will all occupy the space of the gate opening. Subsequently, multiple work function layers will be deposited in the gate opening, further reducing the process window of the gate opening. Therefore, when removing the third sacrificial layer 116 in the fourth opening 105, since the first work function material layer 109, the second work function material layer 112, and the third work function material layer 115 are sequentially deposited in the fourth opening 105, it is very difficult to remove the third sacrificial layer 116 at the bottom of the fourth opening 105, resulting in the third sacrificial layer 116 in the fourth opening 105 not being completely removed, and there is a residue of the third sacrificial layer 116 at the bottom (as shown by the Figure 6 dotted circle). Subsequently, when removing the first work function material layer 109, the second work function material layer 112, and the third work function material layer 115 in the fourth opening 105, due to the residue of the third sacrificial layer 116, the first work function material layer 109, the second work function material layer 112, and the third work function material layer 115 are left behind, resulting in a threshold voltage drift (Vt shift) of the device formed in the fourth region IV, which is not conducive to the performance of the device.

[0033] In addition, after forming the fourth work function material layer 118, since the first work function material layer 109, the second work function material layer 112, the third work function material layer 115, and the fourth work function material layer 118 have been deposited in the first opening 102, the space of the first opening 102 is completely occupied. When filling the gate layer 119 subsequently, the gate layer 119 cannot be formed in the first opening 102, resulting in an increase in the resistance of the semiconductor structure, which is not conducive to the performance of the semiconductor structure.

[0034] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure. A first work function layer is formed in a first opening, and the top surface of the first work function layer is lower than the top surface of the dielectric layer, so that the first work function layer does not occupy the space at the top of the first opening. A second work function layer is formed on the first work function layer, and a third work function layer is formed on the second work function layer. The top surfaces of the second work function layer and the third work function layer are both lower than the dielectric layer, also avoiding the second work function layer and the third work function layer from occupying the space at the top of the first opening. Thus, the process window of the first opening is expanded. After forming a fourth work function layer, there is still space in the first opening to form a gate layer, reducing the resistance of the semiconductor structure and being beneficial to improving the performance of the semiconductor structure.

[0035] Moreover, when forming the first work function layer in the first opening, the first work function layer is also formed in a fourth opening. The first work function layer exposes the top space of the fourth opening, increasing the process window. When removing the sacrificial layer in the fourth opening subsequently, the problem of the sacrificial layer remaining in the fourth opening is solved, avoiding the threshold voltage drift of the device formed in the fourth region.

[0036] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0037] Figures 9 to 25 It is a schematic structural diagram corresponding to each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0038] Refer to Figure 9 , a substrate 200 is provided, and a dielectric layer 201 is formed on the substrate 200. The substrate 200 includes a first region I.

[0039] In this embodiment, the substrate 200 further includes a second region II, a third region III, and a fourth region IV.

[0040] The first region I, the second region II, the third region III, and the fourth region IV are subsequently used to form devices with different threshold voltages.

[0041] In this embodiment, the material of the substrate 200 is single crystal silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, or silicon on insulator.

[0042] In this embodiment, the substrate 200 has a plurality of fin portions (not shown) arranged discretely, and the dielectric layer 201 covers the surfaces of the fin portions.

[0043] In this embodiment, the material of the fin portions is single crystal silicon; in other embodiments, the material of the fin portions may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, or silicon on insulator.

[0044] Continue to refer to Figure 9 , first openings 301, second openings 302, third openings 303, and fourth openings 304 are respectively formed in the dielectric layer 201 of the first region I, the second region II, the third region III, and the fourth region IV.

[0045] The first openings 301, second openings 302, third openings 303, and fourth openings 304 are used to provide space for subsequent formation of the gate structure.

[0046] The formation method of the first openings 301, second openings 302, third openings 303, and fourth openings 304 includes: forming a dummy gate structure (not shown) on the first region I, the second region II, the third region III, and the fourth region IV; forming sidewalls (not shown) on the sidewalls of the dummy gate structure; forming a dielectric layer 201 on the substrate 200, the dielectric layer 201 exposing the top surface of the dummy gate structure; removing the dummy gate structure, forming the first opening 301 in the first region I, forming the second opening 302 in the second region II, forming the third opening 303 in the third region III, and forming the fourth opening 304 in the fourth region IV.

[0047] The dummy gate structure straddles the fin, and the dummy gate structure includes a dummy gate dielectric layer (not shown) and a dummy gate layer (not shown) located on the dummy gate dielectric layer.

[0048] In this embodiment, the material of the dummy gate dielectric layer includes silicon oxide; the material of the dummy gate layer includes polysilicon.

[0049] The method of forming the dielectric layer 201 includes: forming a dielectric material layer (not shown) on the top surface of the dummy gate structure and the sidewall surfaces of the sidewalls; planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed, forming the dielectric layer 201.

[0050] The material of the dielectric layer 201 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 201 includes silicon oxide.

[0051] The process of forming the dielectric material layer includes a chemical vapor deposition process or an atomic layer deposition process; in this embodiment, the process of forming the dielectric material layer includes a chemical vapor deposition process, and the chemical vapor deposition process can rapidly form a dielectric material layer with a relatively thick thickness and a dense structure.

[0052] Refer to Figure 10, a gate dielectric layer 202 is formed on the bottom and sidewall surfaces of the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304, and the gate dielectric layer 202 also covers the surface of the dielectric layer 201; a barrier layer 203 is formed on the gate dielectric layer 202; an etch stop layer 204 is formed on the barrier layer 203.

[0053] The barrier layer 203 is used to prevent atoms in the subsequently formed gate layer from diffusing into the dielectric layer 201; the etch stop layer 204 is used as a stop layer during the subsequent etching of the first work function material layer, the second work function material layer, and the third work function material layer, to avoid over-etching and damaging the underlying gate dielectric layer 202.

[0054] The material of the gate dielectric layer 202 is a high-K (relative permittivity greater than 3.9) material, and the high-K material includes hafnium oxide or aluminum oxide; in this embodiment, the material of the gate dielectric layer 202 includes hafnium oxide.

[0055] The process for forming the gate dielectric layer 202 includes atomic layer deposition process or chemical vapor deposition process; in this embodiment, the atomic layer deposition process is used to form the gate dielectric layer 202, and the atomic layer deposition process can form a gate dielectric layer 202 with a dense structure and a relatively thin thickness.

[0056] The material of the barrier layer 203 includes titanium nitride or titanium nitride silicon; in this embodiment, the material of the barrier layer 203 is titanium nitride.

[0057] The process for forming the barrier layer 203 includes atomic layer deposition process or chemical vapor deposition process; in this embodiment, the atomic layer deposition process is used to form the barrier layer 203, and the atomic layer deposition process can form a barrier layer 203 with a dense structure and a relatively thin thickness.

[0058] In this embodiment, the material of the etch stop layer 204 is tantalum nitride, and the material of the etch stop layer 204 has a large etch selectivity ratio with the materials of the first work function material layer, the second work function material layer, and the third work function material layer, which can stop the etching at the etch stop layer 204 and avoid damaging the barrier layer 203 and the gate dielectric layer 202 due to over-etching.

[0059] The process for forming the etch stop layer 204 includes atomic layer deposition process or chemical vapor deposition process; in this embodiment, the atomic layer deposition process is used to form the etch stop layer 204, and the atomic layer deposition process can form an etch stop layer 204 with a dense structure and a relatively thin thickness.

[0060] After forming the etch stop layer 204, a first work function layer is formed on the bottom and part of the sidewalls of the first opening 301, and the top surface of the first work function layer is lower than the top surface of the dielectric layer 201.

[0061] In this embodiment, a first work function layer is further formed on the bottom and part of the sidewalls of the second opening 302, the third opening 303, and the fourth opening 304.

[0062] The specific steps of forming the first work function layer include:

[0063] Continuing to refer to Figure 10 , a first work function material layer 205 is formed on the bottom and sidewalls of the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304, and the first work function material layer 205 also covers the surface of the dielectric layer 201.

[0064] It should be noted that the "surface" here only represents a spatial relationship and is not limited to direct contact.

[0065] In this embodiment, specifically, the first work function material layer 205 is formed on the etch stop layer 204.

[0066] In this embodiment, the material of the first work function material layer 205 is a P-type work function material layer, and the P-type work function material includes titanium nitride; in other embodiments, the material of the first work function material layer 205 can also be an N-type work function material layer, and the N-type work function material includes titanium aluminum.

[0067] In this embodiment, the atomic layer deposition process is used to form the first work function material layer 205, and the atomic layer deposition process can form a first work function material layer 205 with a dense structure and a relatively thin thickness; in other embodiments, the chemical vapor deposition process can also be used to form the first work function material layer 205.

[0068] Referring to Figure 11 , a first sacrificial material layer 401 is formed on the first work function material layer 205, and the top surface of the first sacrificial material layer 401 is higher than the top surface of the dielectric layer 201.

[0069] The first sacrificial material layer 401 includes a bottom antireflection layer or a carbon-containing organic layer.

[0070] In this embodiment, the first sacrificial material layer 401 is a bottom antireflection layer.

[0071] The process of forming the first sacrificial material layer 401 is a deposition process or a spin coating process; in this embodiment, the spin coating process is used to form the first sacrificial material layer 401.

[0072] Reference Figure 12 , etch the first sacrificial material layer 401 until the top surface of the first sacrificial material layer 401 is lower than the top surface of the dielectric layer 201 to form a first sacrificial layer 410.

[0073] In this embodiment, the process of etching the first sacrificial material layer 401 is a dry etching process; in other embodiments, a wet etching process can also be used to etch the first sacrificial material layer 401.

[0074] In this embodiment, the first sacrificial layer 410 serves as a mask for subsequent etching of the first work function material layer 205.

[0075] Reference Figure 13 , etch the first work function material layer 205 until the top surface of the first work function material layer 205 is flush with the top surface of the first sacrificial layer 410 to form a first work function layer 250.

[0076] In this embodiment, it further includes etching the etch stop layer 204 and the barrier layer 203 until the top surfaces of the etch stop layer 204 and the barrier layer 203 are flush with the top surface of the first sacrificial layer 210.

[0077] In this embodiment, the gate dielectric layer 202 remains, and its function is to protect the dielectric layer 201 in subsequent processes.

[0078] In this embodiment, the process of etching the first sacrificial material layer 401 is a dry etching process; in other embodiments, a wet etching process can also be used to etch the first sacrificial material layer 401.

[0079] The height H1 of the top surface of the first work function layer 250 from the top surface of the substrate 200 ranges from If the height is greater than the process window is still too small, which is not conducive to the subsequent processes; if the height is less than it may damage the first work function layer 250 located on the fin, thus affecting the performance of the semiconductor structure.

[0080] In this embodiment, by etching the first work function material layer 205, the etch stop layer 204, and the barrier layer 203, the multi-layer material layers on the sidewalls above the first opening 301 to the fourth opening 304 are removed, expanding the width of the top of each opening, increasing the process window, which is conducive to subsequent processes such as depositing other material layers or removing other material layers in the first opening 301 to the fourth opening 304. When depositing other material layers, there is more space for forming the material layer; when removing other material layers, due to the expansion of the process window, the material layer at the bottom of the opening is more easily removed, avoiding residue.

[0081] Reference Figure 14 After forming the first work function layer 250, the first sacrificial layer 410 is removed.

[0082] In this embodiment, an ashing process is used to remove the first sacrificial layer 410.

[0083] Continue to refer to Figure 14 A third sacrificial layer 403 is formed in the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304. The top surface of the third sacrificial layer 403 is higher than the top surface of the dielectric layer 201. A first patterned layer 501 is formed on the third sacrificial layer 403. The first patterned layer 501 has a first patterned opening 510 that exposes the surface of the third sacrificial layer 403 in the second region II.

[0084] In this embodiment, the material and formation process of the third sacrificial layer 403 are the same as those of the first sacrificial material layer 401, and will not be elaborated here.

[0085] In this embodiment, the first patterned layer 501 is a patterned photoresist layer.

[0086] The process of forming the first patterned layer 501 includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0087] Reference Figure 15 Using the first patterned layer 501 as a mask, the third sacrificial layer 403 in the second region II is etched until the surface of the first work function layer 250 is exposed. The first work function layer 250 in the second opening 302 is removed.

[0088] In this embodiment, the process of removing the first work function layer 250 is a plasma dry etching process. The etching atmosphere of the plasma dry etching process includes chlorine gas and boron trichloride gas.

[0089] Reference Figure 16 The first patterned layer 501 and the third sacrificial layer 403 are removed. A second work function material layer 206 is formed on the bottom and sidewalls of the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304. The second work function material layer 206 also covers the surface of the dielectric layer 201.

[0090] The work function type of the second work function material layer 206 is the same as that of the first work function material layer 205. In this embodiment, the material of the second work function material layer 206 is a P-type work function material; in other embodiments, the material of the second work function material layer 206 may also be an N-type work function material.

[0091] In this embodiment, an ashing process is used to remove the first patterned layer 501 and the third sacrificial layer 403.

[0092] Continue to refer to Figure 16 , a fourth sacrificial layer 404 is formed on the second work function material layer 206, and the top surface of the fourth sacrificial layer 404 is higher than the top surface of the dielectric layer 201; a second patterned layer 502 is formed on the fourth sacrificial layer 404, and the second patterned layer 502 has a second patterned opening 520, and the second patterned opening 520 exposes the surface of the fourth sacrificial layer 404 in the third region III.

[0093] In this embodiment, the material and formation process of the fourth sacrificial layer 404 are the same as those of the first sacrificial material layer 401, and will not be elaborated here.

[0094] In this embodiment, the material and formation process of the second patterned layer 502 are the same as those of the first patterned layer 501, and will not be elaborated here.

[0095] Refer to Figure 17 , using the second patterned layer 502 as a mask, etch the fourth sacrificial layer 404 in the third region III until the surface of the second work function material layer 206 is exposed; remove the second work function material layer 206 and the first work function layer 250 in the third region III.

[0096] In this embodiment, the process for removing the second work function material layer 206 and the first work function layer 250 is a plasma dry etching process. The etching atmosphere of the plasma dry etching process includes chlorine gas and boron trichloride gas.

[0097] Refer to Figure 18 , remove the second patterned layer 502 and the fourth sacrificial layer 404; form a third work function material layer 207 on the bottom and sidewalls of the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304, and on the dielectric layer 201.

[0098] The third work function material layer 207 has the same type of work function as the first work function material layer 205. In this embodiment, the material of the third work function material layer 207 is a P-type work function material; in other embodiments, the material of the third work function material layer 207 may also be an N-type work function material.

[0099] In this embodiment, an ashing process is used to remove the second patterned layer 502 and the fourth sacrificial layer 404.

[0100] Continue to refer to Figure 18 , a fifth sacrificial layer 405 is formed on the third work function material layer 207, and the top surface of the fifth sacrificial layer 405 is higher than the top surface of the dielectric layer 201; a third patterned layer 503 is formed on the fifth sacrificial layer 405, and the third patterned layer 503 has a third patterned opening 530, and the third patterned opening 530 exposes the surface of the fifth sacrificial layer 405 in the fourth region IV.

[0101] In this embodiment, the material and formation process of the fifth sacrificial layer 405 are the same as those of the first sacrificial material layer 401, and will not be described herein again.

[0102] In this embodiment, the material and formation process of the third patterned layer 503 are the same as those of the first patterned layer 501, and will not be described herein again.

[0103] Refer to Figure 19 , using the third patterned layer 503 as a mask, etch and remove the fifth sacrificial layer 405 in the fourth region IV until the surface of the third work function material layer 207 is exposed; remove the third work function material layer 207, the second work function material layer 206, and the first work function layer 250 in the fourth region IV.

[0104] In this embodiment, the process of removing the third work function material layer 207, the second work function material layer 206, and the first work function layer 250 is a plasma dry etching process. The etching atmosphere of the plasma dry etching process includes chlorine gas and boron trichloride gas.

[0105] In this embodiment, before forming the second work function material layer 206 and the third work function material layer 207, the first work function material layer 205, the etch stop layer 204, and the barrier layer 203 are etched first, so that the top surfaces of the formed first work function layer 250, the etch stop layer 204, and the barrier layer 203 are lower than the top surface of the dielectric layer 201, releasing the space above the first opening 301 to the fourth opening 304, increasing the process window. When removing the fifth sacrificial layer 405 in the fourth opening 304, since the width of the top of the fourth opening 304 is enlarged, it is more conducive to removing the fifth sacrificial layer 405 at the bottom of the fourth opening 304, avoiding the residue of the fifth sacrificial layer 405 at the bottom of the fourth opening 304, thereby avoiding the residue of the third work function material layer 207, the second work function material layer 206, and the first work function layer 250 at the bottom of the fourth opening 304, and preventing the phenomenon of threshold voltage shift in the device formed in the fourth region IV.

[0106] Reference Figure 20 , the third patterned layer 503 and the fifth sacrificial layer 405 are removed.

[0107] In this embodiment, an ashing process is used to remove the third patterned layer 503 and the fifth sacrificial layer 405.

[0108] Reference Figure 21 , a second sacrificial material layer 402 is formed in the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304, and the top surface of the second sacrificial material layer 402 is higher than the top surface of the dielectric layer 201.

[0109] In this embodiment, the material and formation method of the second sacrificial material layer 402 are the same as those of the first sacrificial material layer 401, and will not be elaborated here.

[0110] Reference Figure 22 , the second sacrificial material layer 402 is etched until the top surface of the second sacrificial material layer 402 is lower than the top surface of the dielectric layer 201 and higher than the top surface of the first work function layer 250, forming a second sacrificial layer 420.

[0111] In this embodiment, the second sacrificial layer 420 serves as a mask for subsequent etching of the third work function material layer 207 and the second work function material layer 206.

[0112] In this embodiment, the process of etching the second sacrificial material layer 402 is a dry etching process; in other embodiments, a wet etching process can also be used to etch the second sacrificial material layer 402.

[0113] Continue to refer to Figure 22, etch the third work function material layer 207 and the second work function material layer 206 until the top surfaces of the third work function material layer 207 and the second work function material layer 206 are flush with the top surface of the second sacrificial layer 420, forming a third work function layer 270 and a second work function layer 260, where the third work function layer 270 is located on the second work function layer 260.

[0114] In this embodiment, it further includes etching the gate dielectric layer 202 until the top surface of the gate dielectric layer 202 is flush with the top surface of the second sacrificial layer 420.

[0115] The height H2 of the top surfaces of the third work function layer 270 and the second work function layer 260 from the top surface of the substrate 200 ranges from If the height is greater than it may cause the inability to form a gate layer in the first opening 301 subsequently; it is sufficient that the height of the top surfaces of the third work function layer 270 and the second work function layer 260 from the top surface of the substrate 200 is greater than the height of the top surface of the first work function layer 250 to the top surface of the substrate 200.

[0116] In this embodiment, by etching the third work function material layer 207 and the second work function material layer 206, the top surfaces of the third work function material layer 207 and the second work function material layer 206 are lower than the top surface of the dielectric layer 201 and higher than the top surface of the first work function layer 250, further releasing the space above the first opening 301 to the fourth opening 304, increasing the opening width, providing space for forming a gate layer in the first opening 301 subsequently, thereby reducing the resistance of the formed semiconductor structure and improving the performance of the semiconductor structure.

[0117] Refer to Figure 23 , remove the second sacrificial layer 420; form a fourth work function material layer 208 on the bottoms and sidewalls of the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304.

[0118] In this embodiment, the second sacrificial layer 420 is removed by an ashing process.

[0119] The work function type of the fourth work function material layer 208 is opposite to that of the first work function material layer 205, the second work function material layer 206, and the third work function material layer 207. In this embodiment, the material of the fourth work function material layer 208 is an N-type work function material, and the N-type work function material includes titanium aluminum; in other embodiments, the material of the fourth work function material layer 208 can also be a P-type work function material.

[0120] In this embodiment, the fourth work function material layer 208 is formed by an atomic layer deposition process, which can form a fourth work function material layer 208 with a dense structure and a relatively thin thickness; in other embodiments, the fourth work function material layer 208 can also be formed by a chemical vapor deposition process.

[0121] The fourth work function material layer 208 has a work function type opposite to that of the first work function material layer 205, the second work function material layer 206, and the third work function material layer 207. The fourth work function material layer 208 is used to adjust the threshold voltages of the formed first work function layer 250, second work function layer 260, and third work function layer 270, so that the threshold voltages of the devices in the first region, the second region, and the third region meet different requirements.

[0122] Reference Figure 24 , a gate material layer 601 is formed in the first opening 301, the second opening 302, the third opening 303, and the fourth opening 304, and the top surface of the gate material layer 601 is higher than the top surface of the dielectric layer 201.

[0123] The material of the gate material layer 601 is a metal, and the metal includes tungsten.

[0124] In this embodiment, the method for forming the gate material layer 601 is an electrochemical plating process.

[0125] Reference Figure 25 , the gate material layer 601 and the fourth work function material layer 208 are planarized until the surface of the dielectric layer 201 is exposed, forming the gate layer 610 and the fourth work function layer 280.

[0126] In the forming method provided by the embodiment of the present invention, on the one hand, after the first work function material layer 205 is formed, the first work function material layer 205 is etched to form a first work function layer 250 with a top surface lower than the top surface of the dielectric layer 201, expanding the width of the first opening 301 to the top of the fourth opening 302, increasing the process window, and avoiding the fifth sacrificial layer 405 remaining at the bottom of the fourth opening 302 when the fifth sacrificial layer 405 in the fourth opening 302 is removed later; on the other hand, when the second work function layer 260 and the third work function layer 270 are formed, the top surfaces of the second work function layer 260 and the third work function layer 270 are lower than the top surface of the dielectric layer 201 and higher than the top surface of the first work function layer 250, providing space for forming the gate layer 610 in the first opening 301 later, reducing the resistance of the formed semiconductor structure, and improving the performance.

[0127] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above forming method.

[0128] Referring to Figure 25 , the semiconductor structure includes: a substrate 200, a dielectric layer 201 is disposed on the substrate 200, and the substrate 200 includes a first region I; a first opening 301, which is located in the dielectric layer 201 of the first region I; a first work function layer 250, which is located on the bottom and sidewalls of the first opening 301, and the top surface of the first work function layer 250 is lower than the top surface of the dielectric layer 201; a second work function layer 260, which is located on the surface of the first work function layer 250 in the first opening 301 and on the sidewalls of the first opening 301, and the top surface of the second work function layer 260 is lower than the top surface of the dielectric layer 201 and higher than the top surface of the first work function layer 250; a third work function layer 270, which is located on the surface of the second work function layer 260 in the first opening 301, and the top surface of the third work function layer 270 is flush with the top surface of the second work function layer 260; a fourth work function layer 280, which is located on the surface of the third work function layer 270 in the first opening 301 and on the sidewalls of the first opening 301, and the top surface of the fourth work function layer 280 is flush with the top surface of the dielectric layer 201; a gate layer 610, which is located in the first opening 301.

[0129] In this embodiment, the substrate 200 further includes a second region II, a third region III, and a fourth region IV. Second openings 302, third openings 303, and fourth openings 304 are respectively formed in the dielectric layers 201 of the second region II, the third region III, and the fourth region IV; the second work function layer 260 is further located on the bottom and sidewalls of the second opening 302; the third work function layer 270 is further located on the bottom and sidewalls of the second opening 302 and the third opening 303; the fourth work function layer 280 is further located on the bottom and sidewalls of the second opening 302, the third opening 303, and the fourth opening 304; the gate layer 610 is further located in the second opening 302, the third opening 303, and the fourth opening 304.

[0130] The height H1 of the top surface of the first work function layer 250 from the top surface of the substrate 200 ranges from

[0131] The height H2 of the top surface of the second work function layer 260 from the top surface of the substrate 200 ranges from

[0132] In this embodiment, the work function types of the first work function layer 250, the second work function layer 260, and the third work function layer 270 are the same. The materials of the first work function layer 250, the second work function layer 260, and the third work function layer 270 are P-type work function materials, and the P-type work function materials include titanium nitride. In other embodiments, the materials of the first work function layer 250, the second work function layer 260, and the third work function layer 270 may also be N-type work function materials, and the N-type work function materials include titanium aluminide.

[0133] In this embodiment, the work function type of the fourth work function layer 280 is opposite to that of the first work function layer 250, the second work function layer 260, and the third work function layer 270. The fourth work function layer 280 is an N-type work function material, and the N-type work function materials include titanium aluminide. In other embodiments, the material of the fourth work function layer 280 may also be a P-type work function material, and the P-type work function materials include titanium nitride.

[0134] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate having a dielectric layer thereon, the substrate including a first region; A first opening located within the dielectric layer of the first region; A first work function layer located on the bottom and sidewalls of the first opening, and a top surface of the first work function layer being lower than a top surface of the dielectric layer; A second work function layer located on a surface of the first work function layer within the first opening and on the sidewalls of the first opening, a top surface of the second work function layer being lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer; A third work function layer located on a surface of the second work function layer within the first opening, a top surface of the third work function layer being flush with the top surface of the second work function layer; A fourth work function layer located on a surface of the third work function layer within the first opening and on the sidewalls of the first opening, a top surface of the fourth work function layer being flush with the top surface of the dielectric layer; A gate layer located within the first opening.

2. The semiconductor structure according to claim 1, wherein, The substrate further includes a second region, a third region, and a fourth region, and second openings, third openings, and fourth openings are respectively formed within the dielectric layers of the second region, the third region, and the fourth region; the second work function layer is further located on the bottom and sidewalls of the second opening; the third work function layer is further located on the bottom and sidewalls of the second opening and the third opening; the fourth work function layer is further located on the bottom and sidewalls of the second opening, the third opening, and the fourth opening; the gate layer is further located within the second opening, the third opening, and the fourth opening.

3. The semiconductor structure according to claim 1, wherein The height range from the top surface of the first work function layer to the top surface of the substrate is 4. The semiconductor structure according to claim 1, wherein, The height range from the top surface of the second work function layer to the top surface of the substrate is 5. The semiconductor structure according to claim 1, wherein The materials of the first work function layer, the second work function layer, and the third work function layer are P-type work function materials; or, the materials of the first work function layer, the second work function layer, and the third work function layer are N-type work function materials; the P-type work function materials include titanium nitride; the N-type work function materials include titanium aluminum.

6. The semiconductor structure according to claim 5, wherein The fourth work function layer has a work function type opposite to that of the first work function layer, the second work function layer, and the third work function layer, and the material of the fourth work function layer is an N-type work function material; or, the fourth work function layer is a P-type work function material.

7. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate having a dielectric layer formed thereon, the substrate including a first region; Forming a first opening within the dielectric layer of the first region; Forming a first work function layer on the bottom and a partial sidewall of the first opening, a top surface of the first work function layer being lower than a top surface of the dielectric layer; Forming a second work function layer on a surface of the first work function layer within the first opening and on the sidewalls of the first opening, a top surface of the second work function layer being lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer; Forming a third work function layer on a surface of the second work function layer within the first opening, a top surface of the third work function layer being flush with the top surface of the second work function layer; Forming a fourth work function layer on a surface of the third work function layer within the first opening and on the sidewalls of the first opening; Forming a gate layer within the first opening.

8. The method for forming a semiconductor structure as described in claim 7, wherein, The substrate further includes a second region, a third region, and a fourth region; second openings, third openings, and fourth openings are respectively formed in the dielectric layers in the second region, the third region, and the fourth region; when forming a first work function layer on the bottom and part of the sidewalls of the first opening, it further includes: forming a first work function layer on the bottom and part of the sidewalls of the second opening, the third opening, and the fourth opening.

9. The method for forming a semiconductor structure according to claim 8, wherein, The method for forming a first work function layer on the bottom and part of the sidewalls of the first opening, the second opening, the third opening, and the fourth opening includes: forming a first work function material layer on the bottom and sidewalls of the first opening, the second opening, the third opening, and the fourth opening, and on the dielectric layer; forming a first sacrificial material layer on the first work function material layer, the top surface of the first sacrificial material layer being higher than the top surface of the dielectric layer; etching the first sacrificial material layer until the top surface of the first sacrificial material layer is lower than the top surface of the dielectric layer, forming a first sacrificial layer; etching the first work function material layer until the top surface of the first work function material layer is flush with the top surface of the first sacrificial layer, forming a first work function layer; removing the first sacrificial layer.

10. The method for forming a semiconductor structure as claimed in claim 8, wherein, After forming a first work function layer on the bottom and part of the sidewalls of the first opening, the second opening, the third opening, and the fourth opening, it further includes: removing the first work function layer in the second opening; forming a second work function material layer on the bottom and sidewalls of the first opening, the second opening, the third opening, and the fourth opening; removing the second work function material layer and the first work function layer in the third opening; forming a third work function material layer on the bottom and sidewalls of the first opening, the second opening, the third opening, and the fourth opening; removing the third work function material layer, the second work function material layer, and the first work function layer in the fourth opening.

11. The method for forming a semiconductor structure according to claim 10, wherein The method for forming a second work function layer and a third work function layer includes: After removing the third work function material layer, the second work function material layer, and the first work function layer in the fourth opening, forming a second sacrificial material layer in the first opening, the second opening, the third opening, and the fourth opening, the top surface of the second sacrificial material layer being higher than the top surface of the dielectric layer; etching the second sacrificial material layer until the top surface of the second sacrificial material layer is lower than the top surface of the dielectric layer and higher than the top surface of the first work function layer, forming a second sacrificial layer; etching the second work function material layer and the third work function material layer until the top surfaces of the second work function material layer and the third work function material layer are flush with the top surface of the second sacrificial layer, forming a second work function layer and a third work function layer.

12. The method for forming a semiconductor structure according to claim 9, wherein Before forming a first work function material layer on the bottom and sidewalls of the first opening, the second opening, the third opening, and the fourth opening, it further includes: forming a gate dielectric layer on the bottom and sidewalls of the first opening, the second opening, the third opening, and the fourth opening; forming a barrier layer on the gate dielectric layer; forming an etch stop layer on the barrier layer, and the first work function material layer is located on the etch stop layer.

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