Isolation trench with trap-rich layer enhancement

Abstract

The present application relates to isolation trenches enhanced with trap-rich layers, and discloses a semiconductor structure with electrical isolation and a method of forming a semiconductor structure with electrical isolation. A shallow trench isolation region comprising a dielectric material is disposed in a semiconductor substrate. A trench extends through the shallow trench isolation region and to a trench bottom in the semiconductor substrate below the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polysilicon region disposed in the semiconductor substrate includes a portion disposed below the trench bottom.

Description

Technical Field

[0001] This invention relates to the manufacture of semiconductor devices and integrated circuits, and more particularly to a semiconductor structure having electrical isolation and a method for forming a semiconductor structure having electrical isolation. Background Technology

[0002] Semiconductor structures (such as semiconductor devices designed to operate at radio frequency) are susceptible to performance degradation due to various mechanisms. For example, during radio frequency operation, harmonic generation and high parasitic losses can degrade device performance due to poor device isolation.

[0003] There is a need for improved electrically isolated semiconductor structures and methods for forming electrically isolated semiconductor structures. Summary of the Invention

[0004] In one embodiment of the present invention, a structure includes a semiconductor substrate, a shallow trench isolation region composed of a dielectric material located in the semiconductor substrate, a trench extending through the shallow trench isolation region and extending to a trench bottom in the semiconductor substrate located below the shallow trench isolation region, and a dielectric layer at least partially filling the trench. A polycrystalline region disposed in the semiconductor substrate includes a portion disposed below the trench bottom.

[0005] In one embodiment of the invention, a method includes forming a shallow trench isolation region composed of a dielectric material in a semiconductor substrate, forming a trench extending through the shallow trench isolation region and extending to a trench bottom in the semiconductor substrate located below the shallow trench isolation region, and filling the trench at least partially with a dielectric layer. The method further includes forming a polycrystalline region in the semiconductor substrate. The polycrystalline region includes a portion disposed below the trench bottom. Attached Figure Description

[0006] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the foregoing general description of the invention and the following detailed description of these embodiments, serve to explain these embodiments of the invention. In these drawings, similar reference numerals denote similar features in different views.

[0007] Figures 1-5 A cross-sectional view showing a structure in the continuous manufacturing stage of a processing method according to an embodiment of the present invention.

[0008] Figures 6-10 A cross-sectional view showing a structure according to an alternative embodiment of the present invention. Detailed Implementation

[0009] Please refer to Figure 1According to embodiments of the present invention, a semiconductor substrate 10 comprising a single-crystal semiconductor material, such as single-crystal silicon, is provided. The semiconductor substrate 10 may be a bulk substrate (i.e., a non-insulator-on-silicon or non-SOI substrate) comprising a single-crystal semiconductor material (e.g., single-crystal silicon), which may be a crystal having a crystalline structure but may also have a limited degree of defects. Non-SOI substrates used herein do not have a buried oxide layer. In one embodiment, the semiconductor substrate 10 may be a high-resistivity bulk substrate comprising single-crystal silicon having a resistivity greater than or equal to 1000 ohm-cm. In another embodiment, the semiconductor substrate 10 may be a high-resistivity bulk substrate comprising single-crystal silicon having a resistivity in the range of 1000 ohm-cm to 50000 ohm-cm. In yet another embodiment, the semiconductor substrate 10 may comprise a single-crystal semiconductor material lightly doped with a p-type dopant (e.g., boron) to provide p-type conductivity.

[0010] A shallow trench isolation region 14 is formed, extending from the top surface 12 of the semiconductor substrate 10 to a shallow depth d1 into the semiconductor substrate 10. The shallow trench isolation region 14 may contain a dielectric material deposited in patterned trenches in the semiconductor substrate 10 by chemical vapor deposition, followed by polishing and deglazing. The dielectric material contained in the shallow trench isolation region 14 may include silicon dioxide, silicon nitride, silicon carbide, silicon-rich silicon dioxide, low-KSiCOH, or two or more combinations of these materials. The shallow trench isolation region 14 surrounds a portion of the semiconductor substrate 10 to define a device region 16.

[0011] Polycrystalline layers 18 and 19 may be disposed in the semiconductor substrate 10 below device region 16. Polycrystalline layer 18 may extend together with shallow trench isolation region 14, and polycrystalline layer 19 may be located at a greater depth in semiconductor substrate 10 than polycrystalline layer 18, such that polycrystalline layer 18 is disposed between polycrystalline layer 19 and top surface 12 of semiconductor substrate 10, and between polycrystalline layer 19 and polycrystalline layer 18. Polycrystalline layers 18 and 19 may extend in a plane that is horizontally parallel or substantially parallel to top surface 12.

[0012] Compared to the single-crystal semiconductor material disposed between, above, and below the polycrystalline layers 18 and 19, the polycrystalline layers 18 and 19 have different crystallinity. In one embodiment, the polycrystalline layers 18 and 19 may contain grains of the polycrystalline semiconductor material layer with a resistivity greater than that of the single-crystal semiconductor material of the semiconductor substrate 10. In one embodiment, the polycrystalline layers 18 and 19 may have a resistivity greater than or equal to 1000 ohm-cm. In another embodiment, the resistivity of the polycrystalline layers 18 and 19 may be in the range of about 10,000 ohm-cm to about 1,000,000 ohm-cm. In one embodiment, the single-crystal semiconductor material of the semiconductor substrate 10 may have a resistivity of about 1,000 ohm-cm to about 10,000 ohm-cm, and the polycrystalline layers 18 and 19 may have a larger resistivity of about 10 times to about 100 times (that is, in the range of about 10,000 ohm-cm to about 1,000,000 ohm-cm).

[0013] In one embodiment, polycrystalline layers 18 and 19 can be formed by forming a damaged or amorphous semiconductor material in the semiconductor substrate 10 located below the top surface 12 of the semiconductor substrate 10, and converting at least a portion of the damaged semiconductor material into a polycrystalline semiconductor material. The damaged or amorphous semiconductor material can be formed in the semiconductor substrate 10 by an ion implantation process, such as implanting argon ions, under a given set of implantation conditions. The conversion from the damaged or amorphous semiconductor material to the polycrystalline semiconductor material can be accomplished by performing a thermal treatment (i.e., an annealing process). In one embodiment, the thermal treatment may include rapid thermal processing, for example, at 1000°C for less than 10 seconds. In one embodiment, the thermal treatment recrystallizes the semiconductor surface, retaining individual polycrystalline silicon layers embedded below the top surface 12 as polycrystalline layers 18 and 19. In one embodiment, the thickness of polycrystalline layer 18 below the shallow trench isolation region 14 may be greater than its thickness below the device region 16. In one embodiment, the polycrystalline layer 19 can be omitted by adjusting, for example, the distribution of damaged or amorphous semiconductor material formed in the semiconductor substrate 10 by the ion implantation process.

[0014] A field-effect transistor 20 can be formed as a semiconductor device structure in device region 16 of semiconductor substrate 10 using a bulk (i.e., non-SOI) substrate complementary metal-oxide-semiconductor (CMOS) process. The field-effect transistor 20 may include a gate electrode 22 composed of a conductor (e.g., doped polysilicon or a work function metal) and a gate dielectric 24 composed of an electrically insulating material (e.g., silicon dioxide or hafnium oxide). The gate electrode 22 and gate dielectric 24 can be formed by depositing layers and patterning the layer stack using photolithography and etching processes. The field-effect transistor 20 may also include a halo region, a lightly doped drain extension region, a semiconductor body 26 provided by a portion of the semiconductor material of semiconductor substrate 10 located in device region 16, a source / drain region 28, and sidewalls on the gate electrode 22. In one embodiment, the field-effect transistor 20 may be a switching field-effect transistor designed for radio frequency operation.

[0015] The source / drain regions 28 are doped to have a conductivity type opposite to that of the semiconductor substrate 10 and the semiconductor body 26. In one embodiment, the field-effect transistor 20 may be an n-type field-effect transistor. In this case, the source / drain regions 28 may comprise a semiconductor material doped with an n-type dopant (e.g., arsenic, antimony, and / or phosphorus) to provide n-type conductivity, and the semiconductor substrate 10 and the semiconductor body 26 may comprise a semiconductor material doped with a p-type dopant (e.g., boron or indium) to provide p-type conductivity. The polarity of these dopant types can be interchanged so that the field-effect transistor 20 is a p-type field-effect transistor instead of an n-type field-effect transistor.

[0016] Please refer to Figure 2 In which similar reference numerals indicate Figure 1 Similar features are found in the process, and in the next manufacturing stage of this process, a silicide layer 29 is formed via a silicide process, which includes a segment located on the source / drain region 28, and optionally, a segment located on the gate electrode 22. After forming the silicide layer 29, a dielectric layer 30 is formed over the shallow trench isolation region 14, the device region 16, and the field-effect transistor 20. The dielectric layer 30 may include a conformal layer comprising silicon nitride and a dielectric layer comprising borosilicate glass or silicon dioxide, which is deposited as a blanket layer over the conformal layer and then planarized by chemical mechanical polishing to remove topography.

[0017] A trench 34 is formed, extending through the dielectric layer 30 and the shallow trench isolation region 14 and into a portion of the semiconductor substrate 10 located below the shallow trench isolation region 14. For this purpose, a sacrificial mask 32 is formed over the dielectric layer 30. The sacrificial mask 32 may include a photosensitive material layer, such as photoresist, which is laid by a spin-coating process, pre-baked, exposed to light projected through the photomask, post-baked, and developed with a chemical developer to define an opening disposed over the area to be etched to define the trench 34.

[0018] Trench 34 may be surrounded by side surfaces or sidewalls 38, 40 extending to the trench bottom 36. Similar to shallow trench isolation region 14, trench 34 may surround device region 16 and may also surround a portion of semiconductor substrate 10 located below device region 16. A portion of trench 34 may be disposed within shallow trench isolation region 14, and a portion of trench 34 may be disposed in semiconductor substrate 10 located below shallow trench isolation region 14. Polycrystalline layer 18 may completely separate the portion of semiconductor substrate 10 surrounded by shallow trench isolation region 14 from the portion of semiconductor substrate 10 surrounded by trench 34. Trench bottom 36 may be relative to top surface 12 ( Figure 1 The trench 34 is located at a depth d2 in the semiconductor substrate 10, which is greater than the depth d1 of the shallow trench isolation region 14. For example, the trench 34 may extend from the top surface 12 to a depth of approximately 80 micrometers to approximately 100 micrometers at the trench bottom 36. The trench 34 may also extend completely through the two polycrystalline layers 18 and 19 in a vertical direction.

[0019] Sidewalls 38, 40 may have any variety of different profiles. In this representative embodiment, sidewalls 38, 40 are planar and oriented perpendicularly or substantially perpendicularly to the top surface 12. In an alternative embodiment, sidewalls 38, 40 may include scallops formed by a Bosch etching process. In an alternative embodiment, a sidewall smoothing process may be used after the Bosch etching process to remove the scallops from sidewalls 38, 40. In an alternative embodiment, sidewalls 38, 40 may be inclined relative to the top surface 12 and converge with increasing distance from the trench bottom 36. In an alternative embodiment, sidewalls 38, 40 may be inclined relative to the top surface 12 and diverge with increasing distance from the trench bottom 36.

[0020] Please refer to Figure 3 In which similar reference numerals indicate Figure 2Similar features are present in the next manufacturing stage of this process, and an implantation region 44 containing damaged or amorphous semiconductor material is formed in the portion of the semiconductor substrate 10 adjacent to the bottom 36 of the trench and below it, and in the portion of the semiconductor substrate 10 adjacent to the sidewalls 38, 40 of the trench 34. The sacrificial mask 32 used to pattern the trench 34 can also act as an implantation mask to prevent implantation of the semiconductor substrate 10 in the device region 16.

[0021] The implantation region 44 is formed by an ion implantation process that introduces energetic ions whose trajectories are guided to the trench bottom 36 and the sidewalls 38, 40 of the trench 34. Through random scattering events with atomic nuclei and electrons in the semiconductor material it passes through, these energetic ions lose energy along their path in the semiconductor substrate 10. The energy lost in nuclear collisions causes the target atoms of the semiconductor substrate 10 to deviate from their original lattice positions, thereby damaging its lattice structure. Compared to undamaged areas of the single-crystal semiconductor material of the semiconductor substrate 10 that are masked during the implantation process or are outside the ion range relative to the trench bottom 36 and sidewalls 38, 40, the lattice structure of the semiconductor substrate 10 is damaged or amorphized within the implantation region 44.

[0022] The ions can be generated from a suitable source gas and implanted into the semiconductor substrate 10 surrounding the trench 34 using an ion implantation tool under given implantation conditions. The implantation conditions (e.g., ion species, dose, energy, tilt angle) of the ion implantation process can be selected to adjust the characteristics of the implanted region 44. In one embodiment, the ion species is electrically inactive in the semiconductor material of the semiconductor substrate 10. In one embodiment, the ions can be generated from an inert gas, such as argon or helium. In one embodiment, the dose of argon ions can be greater than or equal to 1 x 10⁻⁶. 14 Ions / square centimeter. In one embodiment, the dose of argon ions can be from approximately 1 x 10⁻⁶. 14 ions / cm² to approximately 5 x 10 15 The ion-to-square-centimeter ratio varies. In one embodiment, the energy of the argon ions can vary from about 30 keV to about 1000 keV. The dose and energy of other injected inert gas ion species may be similar to or different from the dose and energy of the argon ions. The ion implantation conditions may include single implantation, multiple implantation, multiple implantation performed at different tilt angles, different energies, segmented implantation, etc. In one embodiment, the implantation zone 44 can be formed by at least one implantation, which can be performed with perpendicular incidence and at least one implantation performed with a tilt angle.

[0023] In one embodiment, if the sidewalls 38, 40 are inclined relative to the top surface 12 and diverge with increasing distance from the trench bottom 36, the thickness of the implantation region 44 adjacent to the sidewalls 38, 40 of the trench 34 can be increased. This sidewall inclination can improve the coverage of the implantation used to form the implantation region 44 in that portion of the semiconductor substrate 10 adjacent to the sidewalls 38, 40 of the trench 34 by increasing the accessibility of ion trajectories.

[0024] Please refer to Figure 4 In which similar reference numerals indicate Figure 3 Similar characteristics are found in the process, and in the next manufacturing stage of this process, the sacrificial mask 32 is removed, and the damaged or amorphous semiconductor material in the implantation region 44 is converted into a polycrystalline region 48 by performing a heat treatment (i.e., an annealing process). In one embodiment, the heat treatment used to heat the implantation region 44 and form the polycrystalline region 48 may be a rapid thermal annealing. In one embodiment, the rapid thermal annealing may be performed using, for example, a row of flash lamps to heat the semiconductor substrate 10 to a peak temperature in the range of 900°C to 1125°C, and have a dwell time of 30 milliseconds to 5 seconds at the peak temperature, and in a particular embodiment, the peak temperature may be 1000°C, and it may be held for a dwell time of less than or equal to 1 second. Alternatively, the heat treatment may include one or more furnace annealings performed in the temperature range of 900°C to 1100°C.

[0025] Polycrystalline region 48 comprises polycrystalline semiconductor material (e.g., polycrystalline silicon), particularly grains of polycrystalline semiconductor material. In addition to the polycrystalline grains, polycrystalline region 48 may also contain defects as residual damage, and these defects may contain trapped atoms of an implantation type (e.g., argon or xenon). Compared to polycrystalline region 48, the semiconductor material of the semiconductor substrate 10 arranged around trench 34 and polycrystalline region 48 has a lattice structure and is grainless.

[0026] Polycrystalline region 48 is disposed in semiconductor substrate 10 adjacent to trench 34. More specifically, a portion of polycrystalline region 48 is disposed in semiconductor substrate 10 adjacent to sidewalls 38, 40 and trench bottom 36 of trench 34. In one embodiment, this portion of polycrystalline region 48 adjacent to trench bottom 36 extends together with trench bottom 36 (i.e., shares a boundary with trench bottom 36). In one embodiment, this portion of polycrystalline region 48 adjacent to sidewalls 38, 40 extends together with sidewalls 38, 40. In one embodiment, this portion of polycrystalline region 48 adjacent to trench bottom 36 extends together with trench bottom 36, and this portion of polycrystalline region 48 adjacent to sidewalls 38, 40 extends together with sidewalls 38, 40. In one embodiment, these different portions of polycrystalline region 48 adjacent to sidewalls 38, 40 and trench bottom 36 are continuous and not separate. In one embodiment, the portion of the polycrystalline region 48 adjacent to the sidewalls 38, 40 may extend from the shallow trench isolation region 14 to the portion of the polycrystalline region 48 located at and below the trench bottom 36. Polycrystalline layers 18, 19 may extend completely below the device region 16 to the polycrystalline region 48 to define respective horizontal stripes composed of polycrystalline semiconductor material. In one embodiment, due to local differences in implantation depth, the portion of the polycrystalline region 48 located at and below the trench bottom 36 may be thicker than the portion of the polycrystalline region 48 adjacent to the sidewalls 38, 40.

[0027] The polycrystalline region 48 may be characterized as a trap-rich material having a resistivity greater than or equal to that of the semiconductor material of the semiconductor substrate 10. In one embodiment, the polycrystalline region 48 may have a resistivity greater than or equal to 1000 ohm-cm. In another embodiment, the resistivity of the polycrystalline region 48 may be in the range of about 10,000 ohm-cm to about 1,000,000 ohm-cm. In one embodiment, the resistivity of the polycrystalline layers 18, 19 may be equal to or substantially equal to the resistivity of the polycrystalline region 48.

[0028] Please refer to Figure 5 In which similar reference numerals indicate Figure 4 Similar features are present in the next manufacturing stage of this process, where a dielectric layer 50 may be deposited over the dielectric layer 30 and planarized by chemical mechanical polishing to remove the topography. A portion of the dielectric layer 50 may at least partially fill the trench 34 to define a deep trench isolation region 54 in the semiconductor substrate 10. The dielectric layer 50 may include a dielectric material, such as borosilicate glass or silicon dioxide, and may contain voids (not shown) defining air gaps. Intermediate and back-end processing are then performed, including forming contacts, vias, and lines for interconnect structures coupled to the field-effect transistor 20.

[0029] Polycrystalline region 48 enhances the electrical isolation of field-effect transistor 20 during operation. The high-resistivity polycrystalline region 48 reduces harmonic generation and parasitic losses of field-effect transistor 20 during operation. Polycrystalline region 48 effectively extends the depth of deep trench isolation region 54 beyond the depth of trench 34, and is positioned along potential current leakage paths.

[0030] Please refer to Figure 6 In which similar reference numerals indicate Figure 5 Similar features are present in the semiconductor substrate 10, and according to an alternative embodiment, the semiconductor substrate 10 can be thinned by backside grinding. This thinning of the semiconductor substrate 10 can result in the backside surface 13 of the semiconductor substrate 10 extending across and together with the portion of the polycrystalline region 48 located below the trench bottom 36 of the trench 34.

[0031] Please refer to Figure 7 In which similar reference numerals indicate Figure 5 Similar features are present in the example, and according to an alternative embodiment, the semiconductor substrate 10 can be thinned by back-side grinding, and an implantation layer 60 can be formed between the back-side surface 13 and the portion of the polycrystalline region 48 located below the trench bottom 36 of the trench 34. The implantation layer 60 located between the polycrystalline region 48 and the back-side surface 13 can traverse and extend with the portion of the polycrystalline region 48 located below the trench bottom 36 of the trench 34.

[0032] Please refer to Figure 8 In which similar reference numerals indicate Figure 5 Similar features are present in the example, and according to an alternative embodiment, the semiconductor substrate 10 may be thinned by back-side grinding and etched to define a trench 62 on the back-side surface 13. The trench 62 traverses and extends along with a portion of the polycrystalline region 48 located below the trench bottom 36 of the trench 34. The trench 62 may be filled by a layer 64 comprising an electrically insulating material (e.g., silicon dioxide) or comprising polycrystalline silicon.

[0033] Please refer to Figure 9 In which similar reference numerals indicate Figure 3 Similar features are present in the trench 34, and according to an alternative embodiment, the trench 34 may be laterally disposed in the shallow trench isolation region 14, closer to the interface between the shallow trench isolation region 14 and the semiconductor material in the device region 16. The polycrystalline region 48 may overlap and merge adjacent to the trench bottom 36 of the trench 34, which has sidewalls 38, 40 that are inclined relative to the top surface 12 and converge with increasing distance from the trench bottom 36. The polycrystalline region 48 may extend below this portion of the semiconductor substrate 10 surrounded by the shallow trench isolation region 14 and below this portion of the semiconductor substrate surrounded by the trench 34. This overlap and merging of the polycrystalline region 48 eliminates the need for measures to modify the back surface 13.

[0034] Please refer to Figure 10 In which similar reference numerals indicate Figure 2 Similar features are present in the trench 34, and according to an alternative embodiment, the sidewalls 38, 40 of the trench 34 may include recesses 70 formed in the semiconductor substrate 10 adjacent to the shallow trench isolation region 14. The recesses 70 may be formed by an etching process prior to the formation of the implantation region 44. The recesses 70 locally widen the trench 34 adjacent to the bottom of the shallow trench isolation region 14. This local widening can improve the coverage of the implantation for forming the implantation region 44 in this portion of the semiconductor substrate 10 adjacent to the trench bottom 36 and sidewalls 38, 40 of the trench 34 by increasing the accessibility of ion tracks. A portion of the dielectric layer 50 may fill the recesses 70 when the trench 34 is at least partially filled to define the deep trench isolation region 54.

[0035] The method described above is used for the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as bare chips, or in package form. In the latter case, the chip is housed in a single-chip package (e.g., a plastic carrier with pins attached to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects or embedded interconnects, or both). In any case, the chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0036] The terms used herein, modified by approximate language such as “approximately,” “roughly,” and “substantially,” are not limited to the specified precise values. This approximate language may correspond to the accuracy of the instrument used to measure the value, and may represent + / - 10% of the value unless otherwise dependent on the accuracy of that instrument.

[0037] The terms "vertical" and "horizontal" are used in this document as examples to establish a reference framework and are not intended to be limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as defined above. The term "lateral" refers to a direction within that horizontal plane.

[0038] A feature "connected" or "coupled" to another feature may be directly connected or coupled to that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be "directly connected" or "directly coupled" to another feature. If at least one intermediate feature exists, the feature may be "indirectly connected" or "indirectly coupled" to another feature. A feature "on" or "in contact" with another feature may be directly on or in direct contact with that other feature, or one or more intermediate features may exist. If no intermediate features exist, the feature may be directly "on" or in direct contact with that other feature. If at least one intermediate feature exists, the feature may not be "directly" on or in direct contact with that other feature.

[0039] The descriptions of various embodiments of the invention are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements upon technical techniques known in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: Semiconductor substrate, having a top surface; A shallow trench isolation region is located in the semiconductor substrate, and the shallow trench isolation region is composed of a first dielectric material; The first polycrystalline layer is located in the semiconductor substrate; The second polycrystalline layer is located in the semiconductor substrate, and the first polycrystalline layer is disposed between the second polycrystalline layer and the top surface of the semiconductor substrate; The first trench extends through the shallow trench isolation region, the first polycrystalline layer, and the second polycrystalline layer, and extends to the bottom of the trench in the semiconductor substrate located below the shallow trench isolation region. A dielectric layer, at least partially filling the first trench; as well as A polycrystalline region is located in the semiconductor substrate, the polycrystalline region including a first portion disposed below the bottom of the trench.

2. The semiconductor structure as described in claim 1, wherein, The first trench includes a first sidewall and a second sidewall extending to the bottom of the trench, the polycrystalline region includes a second portion disposed adjacent to the first sidewall, and the polycrystalline region includes a third portion disposed adjacent to the second sidewall.

3. The semiconductor structure as described in claim 2, wherein, The first, second, and third portions of the polycrystalline region are continuous.

4. The semiconductor structure as described in claim 2, wherein, The shallow trench isolation region extends to a first depth in the semiconductor substrate, and the bottom of the trench is located at a second depth in the semiconductor substrate, the second depth being greater than the first depth.

5. The semiconductor structure as described in claim 2, wherein, The second portion of the polycrystalline region extends from the shallow trench isolation region toward the first portion of the polycrystalline region adjacent to the first sidewall, and the third portion of the polycrystalline region extends from the shallow trench isolation region toward the first portion of the polycrystalline region adjacent to the second sidewall.

6. The semiconductor structure as claimed in claim 1, wherein, The polycrystalline region has a resistivity in the range of about 10,000 ohm-cm to about 1,000,000 ohm-cm.

7. The semiconductor structure as claimed in claim 1, wherein, The shallow trench isolation region surrounds a first portion of the semiconductor substrate and also includes: A field-effect transistor, including a source / drain region located in the first portion of the semiconductor substrate.

8. The semiconductor structure as claimed in claim 1, wherein, The shallow trench isolation region extends to a first depth in the semiconductor substrate, the bottom of the trench is located at a second depth in the semiconductor substrate, the second depth is greater than the first depth, and the first portion of the polycrystalline region extends together with the bottom of the trench.

9. The semiconductor structure as claimed in claim 1, wherein, The first polycrystalline layer extends laterally in the semiconductor substrate to traverse the polycrystalline region.

10. The semiconductor structure as claimed in claim 9, wherein, The first polycrystalline layer extends together with the shallow trench isolation region.

11. The semiconductor structure of claim 10, wherein, The shallow trench isolation region surrounds a first portion of the semiconductor substrate, the first trench surrounds a second portion of the semiconductor substrate, and the first polycrystalline layer extends laterally below the second portion of the semiconductor substrate, separating the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

12. The semiconductor structure of claim 10, wherein, The second polycrystalline layer extends laterally in the semiconductor substrate to traverse the polycrystalline region, and the first polycrystalline layer is separated from the second polycrystalline layer by the crystalline semiconductor material of the semiconductor substrate.

13. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate includes a top surface and a back side opposite the top surface, the back side of the semiconductor substrate extending together with the first portion of the polycrystalline region.

14. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate includes a top surface and a back side opposite the top surface, and also includes: A second trench is located on the back side of the semiconductor substrate that extends together with the first portion of the polycrystalline region, and the second trench contains a second dielectric material.

15. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate includes a top surface and a back side opposite the top surface, and also includes: An implantation layer is located between the back side of the semiconductor substrate and the first portion of the polycrystalline region, and the implantation layer extends together with the first portion of the polycrystalline region.

16. The semiconductor structure as claimed in claim 1, wherein, The shallow trench isolation region surrounds a first portion of the semiconductor substrate, the first trench surrounds a second portion of the semiconductor substrate, and the first portion of the polycrystalline region extends below the first and second portions of the semiconductor substrate.

17. The semiconductor structure as claimed in claim 1, wherein, The trench includes a first sidewall and a second sidewall extending to the bottom of the trench, and the trench also includes a groove located in the first sidewall, and the groove is disposed adjacent to the shallow trench isolation area.

18. A method for forming a semiconductor structure, the method comprising: A shallow trench isolation region composed of dielectric material is formed in a semiconductor substrate; A first polycrystalline layer is formed in the semiconductor substrate; A second polycrystalline layer is formed in the semiconductor substrate, wherein the first polycrystalline layer is disposed between the second polycrystalline layer and the top surface of the semiconductor substrate; A trench is formed that extends through the shallow trench isolation region, the first polycrystalline layer, and the second polycrystalline layer and extends to the bottom of the trench in the semiconductor substrate located below the shallow trench isolation region; Fill at least a portion of the trench with a dielectric layer; and A polycrystalline region is formed in the semiconductor substrate; The polycrystalline region includes a first portion disposed below the bottom of the trench.

19. The method of claim 18, wherein, The trench includes a first sidewall and a second sidewall extending to the bottom of the trench, the polycrystalline region includes a second portion disposed adjacent to the first sidewall, and the polycrystalline region includes a third portion disposed adjacent to the second sidewall.

20. The method of claim 19, wherein, The second portion of the polycrystalline region extends from the shallow trench isolation region toward the first portion of the polycrystalline region adjacent to the first sidewall, and the third portion of the polycrystalline region extends from the shallow trench isolation region toward the first portion of the polycrystalline region adjacent to the second sidewall.

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