Memory cell, mask, and SRAM device

Abstract

A memory cell, a mask and an SRAM device, the memory cell comprising: a substrate, the substrate comprising a power supply region, a bit line region and a ground region arranged in parallel along a first direction, and in a second direction, the bit line region is between the power supply region and the ground region, the second direction is perpendicular to the first direction; a bit line metal layer in the bit line region, and the bit line metal layer extends along the first direction; a plurality of discrete ground metal layers arranged in the ground region along the first direction; a plurality of discrete power supply metal layers arranged in the power supply region along the first direction. In the embodiment of the application, in the first direction, the plurality of power supply metal layers are arranged at intervals, the power supply metal layer is island-shaped, and the space between the power supply metal layer and the bit line metal layer is larger, so that the capacitive coupling effect of the plurality of power supply metal layers arranged at intervals and the bit line metal layer is weaker, and when the memory cell is working, the RC delay of the memory cell can be reduced, and the reading performance of the memory cell can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a memory cell, a photomask, and an SRAM device. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory, and analog circuits, with memory devices accounting for a significant proportion. With the development of semiconductor technology and the wider application of memory devices, it is necessary to integrate these memory devices with other components onto a single chip to form embedded semiconductor memory devices. For example, if the memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility between the memory device and the embedded CPU platform while maintaining the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the memory device needs to be compatible with embedded standard logic devices. Embedded semiconductor devices are typically divided into a logic region and a memory region. The logic region usually includes logic devices, while the memory region includes storage devices. With the development of storage technology, various types of semiconductor memories have emerged, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash memory. Due to its advantages such as low power consumption and fast operating speed, SRAM and its fabrication methods have received increasing attention.

[0004] SRAM cells have the advantage of storing data without requiring refresh. As the speed requirements of integrated circuits increase, the read and write speeds of SRAM cells become increasingly important. Furthermore, sufficient read and write margins are needed respectively to ensure reliable read and write operations. However, as already very small SRAM cells continue to shrink, these requirements become increasingly demanding. Summary of the Invention

[0005] The problem addressed by the embodiments of this application is to provide a memory cell, a mask, and an SRAM device that improves the electrical performance of the device.

[0006] To address the aforementioned issues, this application provides a storage cell comprising: a substrate, the substrate including a power region, a bit line region, and a ground region arranged in parallel along a first direction, wherein the bit line region is located between the power region and the ground region in a second direction, and the second direction is perpendicular to the first direction; a bit line metal layer located in the bit line region and extending along the first direction; a plurality of discrete ground metal layers arranged along the first direction in the ground region; and a plurality of discrete power metal layers arranged along the first direction in the power region.

[0007] Accordingly, this application also provides a photomask for forming a memory cell, the memory cell including a semiconductor structure, the semiconductor structure including: a substrate, the substrate including a power region, a bit line region and a ground region arranged in parallel along a first direction, and in a second direction, the bit line region being located between the power region and the ground region, the second direction being perpendicular to the first direction; the photomask is characterized in that it includes: a bit line metal pattern for forming a bit line metal layer extending along the first direction in the bit line region; a plurality of spaced-apart ground metal patterns for forming a plurality of discrete ground metal layers along the first direction in the ground region; and a plurality of spaced-apart power metal patterns for forming a plurality of discrete power metal layers along the first direction in the power region.

[0008] Accordingly, this application also provides a photomask for forming a memory cell, the memory cell including a semiconductor structure, the semiconductor structure including: a substrate, the substrate including a power region, a bit line region and a ground region arranged in parallel along a first direction, and the bit line region located between the power region and the ground region in a second direction, the second direction being perpendicular to the first direction; a ground metal layer located in the ground region and extending along the first direction; a bit line metal layer located in the bit line region and extending along the first direction; a plurality of discrete power metal layers arranged along the first direction in the power region; a first via interconnect structure located on the ground metal layer, the bit line metal layer and the plurality of discrete power metal layers; a first metal layer located on the first via interconnect structure; a second via interconnect structure located on the first metal layer; the photomask is characterized in that it includes: an interconnect pattern for forming a second metal layer, and the second metal layer is located on the second via interconnect structure in the power region, the second metal layer being simultaneously connected to the plurality of second via interconnect structures.

[0009] Accordingly, this application also provides an SRAM device, including the memory cell described in this application embodiment.

[0010] Compared with the prior art, the technical solution of this application has the following advantages:

[0011] The memory cell provided in this application includes: a substrate, the substrate including a power region, a bit line region, and a ground region arranged in parallel along a first direction, and the bit line region located between the power region and the ground region in a second direction, the second direction being perpendicular to the first direction; a bit line metal layer located in the bit line region and extending along the first direction; a plurality of discrete ground metal layers arranged along the first direction in the ground region; and a plurality of discrete power metal layers arranged along the first direction in the power region. Compared with the case where the power metal layers in the power region are continuous metal layers, in this application embodiment, the plurality of power metal layers are spaced apart in the first direction, the power metal layers are island-shaped, and the space between them and the bit line metal layers is larger. Therefore, the capacitive coupling effect between the plurality of spaced power metal layers and the bit line metal layers is weaker, which can reduce the RC delay of the memory cell and improve the read performance of the memory cell when it is working.

[0012] In an optional configuration, the power supply area, bit line area, and junction area are designated as unit areas. The substrate comprises multiple unit areas arranged in a matrix, with the power supply areas in adjacent unit areas being adjacent in the second direction, and the power metal layers in two power supply areas being staggered in the first direction; furthermore, the power metal layers in two power supply areas are spaced apart in the second direction. Compared to the case where the power metal layers in the power supply areas are continuous, because the multiple power metal layers in the power supply areas are spaced apart along the first direction, the space between a power metal layer in one power supply area and the bit line metal layer in its adjacent power supply area is larger. Consequently, the capacitive coupling effect between a power metal layer in one power supply area and the power metal layer in its adjacent power supply area is weaker. This reduces the RC latency of the memory cell and improves its read performance during operation. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a storage unit structure;

[0014] Figure 2 yes Figure 1 Cross-sectional view at point aa;

[0015] Figure 3 This is a schematic diagram of the structure of a storage unit according to an embodiment of this application;

[0016] Figure 4 yes Figure 3 Cross-sectional view at point AA;

[0017] Figure 5 This is a schematic diagram of a semiconductor structure according to an embodiment of the present application;

[0018] Figure 6 yes Figure 5 Cross-sectional view at BB;

[0019] Figure 7 This is a schematic diagram of the structure of a mask template according to an embodiment of this application;

[0020] Figure 8 This is a schematic diagram of another embodiment of the semiconductor structure of this application;

[0021] Figure 9 for Figure 8 Cross-sectional view at CC;

[0022] Figure 10 This is a schematic diagram of yet another embodiment of the mask template of this application. Detailed Implementation

[0023] The devices currently being developed still suffer from performance issues. This paper analyzes the reasons for these performance problems using the structure of a memory cell as an example.

[0024] refer to Figure 1 and Figure 2 This is a schematic diagram of the structure of a storage unit.

[0025] like Figure 1 As shown, the memory cell includes: a substrate 1, which includes a power supply region i, a bit line region ii, and a grounding region iii arranged in parallel along a first direction x, and the bit line region ii is located between the power supply region i and the grounding region iii in a second direction y, wherein the second direction y is perpendicular to the first direction x; a bit line metal layer 10 located in the bit line region ii and extending along the first direction x; a ground metal layer 11 located in the grounding region iii and spaced apart along the first direction x; and a power supply metal layer 12 arranged in the power supply region i along the first direction x.

[0026] like Figure 2 As shown, Figure 2 for Figure 1 In the cross-sectional view at aa, the memory cell includes: a gate structure (not shown in the figure) located between the bit line region ii and the junction region iii, and between the power supply region i and the bit line region ii; a source / drain doped layer 2 located on the substrate 1 on both sides of the gate structure; a source / drain plug 3 located on the source / drain doped layer 2; and a plug interconnect structure 4 located on the source / drain plug 3.

[0027] The power metal layer 12 in power area i penetrates power area i in a first direction. With the development of storage technology, the integration of storage cells is getting higher and higher, and the read and write speeds of storage cells are getting faster and faster.

[0028] However, the increased integration density of memory cells leads to a corresponding decrease in the spacing between adjacent devices within the memory cell, for example... Figure 1 In the second direction y, the spacing between the bit line metal layer 10 and the power supply metal layer 12 becomes smaller and smaller. When the memory cell is working, the capacitive coupling effect between the bit line metal layer 10 and the power supply metal layer 12 becomes stronger and stronger, resulting in a large RC delay of the memory cell and a slow SRAM read speed.

[0029] To address the aforementioned technical problem, this application proposes a storage cell comprising: a substrate, the substrate including a power region, a bit line region, and a ground region arranged in parallel along a first direction, wherein the bit line region is located between the power region and the ground region in a second direction, and the second direction is perpendicular to the first direction; a bit line metal layer located in the bit line region and extending along the first direction; a plurality of discrete ground metal layers arranged along the first direction in the ground region; and a plurality of discrete power metal layers arranged along the first direction in the power region.

[0030] The memory cell provided in this application includes: a substrate, the substrate including a power region, a bit line region, and a ground region arranged in parallel along a first direction, and the bit line region located between the power region and the ground region in a second direction, the second direction being perpendicular to the first direction; a bit line metal layer located in the bit line region and extending along the first direction; a plurality of discrete ground metal layers arranged along the first direction in the ground region; and a plurality of discrete power metal layers arranged along the first direction in the power region. Compared with the case where the power metal layers in the power region are continuous metal layers, in this application embodiment, the plurality of power metal layers are spaced apart in the first direction, the power metal layers are island-shaped, and the space between them and the bit line metal layers is larger. Therefore, the capacitive coupling effect between the plurality of spaced power metal layers and the bit line metal layers is weaker, which can reduce the RC delay of the memory cell and improve the read performance of the memory cell when it is working.

[0031] To make the above-mentioned objectives, features and advantages of the embodiments of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0032] Accordingly, refer to Figure 3 and Figure 4 In this embodiment of the invention, a storage unit is also provided. Figure 3 This is a schematic diagram of the semiconductor structure embodiment of this application. Figure 4 for Figure 3 Cross-sectional view at point AA.

[0033] The memory cell includes a semiconductor structure comprising: a substrate, the substrate including a power region i, a bit line region ii, and a ground region iii arranged in parallel along a first direction x, and the bit line region ii located between the power region i and the ground region iii in a second direction y, the second direction y being perpendicular to the first direction x; a bit line (BL) metal layer 302 located in the bit line region ii and extending along the first direction x; a plurality of discrete ground metal layers 301 (VSS power wiring) arranged along the first direction in the ground region iii; and a plurality of discrete power metal layers 303 (VDD power wiring) arranged along the first direction x in the power region i.

[0034] In the semiconductor structure provided by the embodiments of the present invention, compared with the case where the power metal layer in the power region i is a continuous metal layer, in the embodiments of this application, multiple power metal layers 303 are arranged at intervals in the first direction x. The power metal layers are island-shaped, and the space between them and the bit line metal layer 302 is larger. As a result, the capacitive coupling effect between the multiple spaced power metal layers 303 and the bit line metal layer 302 is weaker. When the memory cell is working, the RC delay of the memory cell can be reduced and the read performance of the memory cell can be improved.

[0035] This embodiment uses a FinFET (Fin Field-Effect Transistor) as an example of a transistor in a memory cell. The substrate includes a substrate 100 and fins 101 located on the substrate 100. In other embodiments, the transistor in the memory cell can also be a gate-to-all-around (GAA) transistor, and the corresponding substrate includes a substrate and a plurality of channel layers arranged with dangling spaces in the normal direction of the substrate surface.

[0036] In this embodiment, a six-transistor static random access memory (6T-SRAM) is used as an example. The corresponding memory cell includes a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG).

[0037] Specifically, the pull-up transistor is composed of a P-type metal oxide semiconductor (PMOS) transistor, while the pull-down transistor and the transmission transistor are composed of an N-type metal oxide semiconductor (NMOS) transistor.

[0038] In this embodiment, the substrate 100 provides a process platform for the subsequent formation of memory cells.

[0039] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0040] It should be noted that the power supply area i, bit line area ii, and junction area iii are referred to as unit areas.

[0041] In this embodiment, the fin 101 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0042] When the semiconductor structure is in operation, the gate structure 108 (e.g.) Figure 3 (As shown) is used to control the opening and closing of the channel.

[0043] Specifically, the gate structure 108 spans the fin 101 and covers part of the sidewall and top wall of the fin 101.

[0044] In this embodiment, the gate structure 108 is a metal gate structure, including a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer. In other embodiments, the gate structure may also be a polysilicon gate structure.

[0045] When the transistor is an NMOS, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the transistor is a PMOS, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon nitride, titanium silicon nitride, and tantalum carbide.

[0046] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer may also include W.

[0047] Specifically, the semiconductor structure further includes a gate dielectric layer (not shown) located between the gate structure 108 and the fin.

[0048] The gate dielectric layer is used to electrically isolate the gate structure 108 and the fin 101. It should be noted that the material of the gate dielectric layer is a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide.

[0049] The gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer may also be made of one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0050] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0051] The pull-up transistor is composed of a P-type metal oxide semiconductor (PMOS) transistor. When the semiconductor structure is working, the source and drain doping layers 102 apply compression stress to the channel below the gate. Compression of the channel can improve the hole mobility. Accordingly, the source and drain doping layers 102 of the pull-up transistor are doped with P-type ions, which include one or more of B, Ga and In.

[0052] The pull-down transistor and the transfer transistor are composed of N-type metal oxide semiconductor (NMOS) transistors. When the semiconductor structure is operating, the source and drain doping layers 102 apply tensile stress to the channel below the gate structure. Stretching the channel can improve the electron migration rate. Accordingly, the source and drain doping layers 102 of the pull-down transistor and the transfer transistor are doped with N-type ions, including one or more of P, As, and Sb.

[0053] The semiconductor structure further includes an interlayer dielectric layer 105 located on the sidewall of the gate structure 108, wherein the top surface of the interlayer dielectric layer 105 is lower than or flush with the top surface of the gate structure 108.

[0054] The interlayer dielectric layer 105 is used for electrical isolation of adjacent devices. In this embodiment, the material of the interlayer dielectric layer 105 is an insulating material.

[0055] Specifically, the material of the interlayer dielectric layer 105 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 105.

[0056] The semiconductor structure further includes a first dielectric layer 106, located on the gate structure 108 and the interlayer dielectric layer 105.

[0057] The first dielectric layer 106 and the interlayer dielectric layer 105 are used to electrically isolate adjacent devices.

[0058] In this embodiment, the material of the first dielectric layer 106 is an insulating material. Specifically, the material of the first dielectric layer 106 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric layer 106.

[0059] The source / drain plug 103 penetrates the first dielectric layer 106 and the interlayer dielectric layer 105 and is connected to the source / drain doped layer 102.

[0060] Specifically, the power metal layer 303 located in the power region i is connected to the drain in the source-drain doped layer 102 through the source-drain plug 103, and the ground metal layer 301 located in the ground region iii is connected to the drain in the source-drain doped layer 102 of the pull-down transistor through the source-drain plug 103.

[0061] In this embodiment, the source / drain plug 103 is made of a conductive material. Specifically, the conductive material includes W or Co. In this embodiment, the source / drain plug 103 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0062] The semiconductor structure further includes a second dielectric layer 107 located on the source / drain plug 103 and the first dielectric layer 106.

[0063] In this embodiment, the material of the second dielectric layer 107 is an insulating material. Specifically, the material of the second dielectric layer 107 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the second dielectric layer 107.

[0064] The semiconductor structure further includes a plug interconnect structure 104, which penetrates the second dielectric layer 107 and is connected to the source / drain plug 103.

[0065] In this embodiment, the material of the plug interconnect structure 104 is a conductive material. Specifically, the conductive material includes one or more of W, Co, and Cu. In this embodiment, the material of the plug interconnect structure 104 is Cu. Cu has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0066] In this embodiment, the semiconductor structure further includes a third dielectric layer 109, located on the plug interconnect structure 104 and the second dielectric layer 107.

[0067] In this embodiment, the material of the third dielectric layer 109 is an insulating material. Specifically, the material of the third dielectric layer 109 includes silicon oxide.

[0068] The power metal layer 303 penetrates the third dielectric layer 109 in the power region i and is connected to the plug interconnect structure 104.

[0069] The power metal layer 303 is for the VDD power supply wiring of the storage device.

[0070] Specifically, the material of the power supply metal layer 303 includes one or more of Cu, W, and Co. In this embodiment, the material of the power supply metal layer 303 includes Cu.

[0071] Specifically, the power metal layer 303 in power region i is connected to the drain of the pull-up transistor in the 6T-SRAM. In this embodiment, only three power metal layers 303 are shown. In other embodiments, the number of power metal layers is not limited to three.

[0072] The bit line metal layer 302 penetrates the third dielectric layer 109 in the bit line region ii and is connected to the drain of the transmission gate transistor through the plug interconnect structure 104.

[0073] The bit line metal layer 302 serves as a read port bit line (BL) or a complementary read port bit line (BLB).

[0074] Specifically, the material of the bit line metal layer 302 includes one or more of Cu, W, and Co. In this embodiment, the material of the bit line metal layer 302 includes Cu.

[0075] The ground metal layer 301 penetrates the third dielectric layer 109 in the bit line region ii and is connected to the plug interconnect structure 104.

[0076] The grounding metal layer 301 is the VSS power supply wiring for the storage unit.

[0077] Specifically, the material of the grounding metal layer 301 includes one or more of Cu, W, and Co. In this embodiment, the material of the grounding metal layer 301 includes Cu.

[0078] It should be noted that the ground metal layer 301 and the power metal layer 303 correspond to each other in the second direction y.

[0079] It should be noted that the storage unit includes: a plurality of discrete word line metal layers 304, arranged along the first direction x in the ground area iii, wherein the word line metal layers 304 are spaced apart from the ground metal layer 301.

[0080] The word line metal layer 304 penetrates the third dielectric layer 109 in the junction area iii and is connected to the plug interconnect structure 104.

[0081] The word line metal layer 304 is used to connect to the gate structure 108 of the transmission gate transistor.

[0082] Specifically, the material of the word line metal layer 304 includes one or more of Cu, W, and Co. In this embodiment, the material of the word line metal layer 304 includes Cu.

[0083] It should be noted that, in the first direction x, the ratio of the spacing between adjacent power metal layers 303 to the size of the power metal layer 303 should not be too large or too small. If the ratio is too large, that is, if the size of the formed power metal layer 303 in the first direction x is too small, as the size of the memory cell becomes smaller, even a small overlay error during the formation of the power metal layer 303 may cause the power metal layer 303 to only contact a portion of the plug interconnect structure 104, or in extreme cases, not at all. This results in a large contact resistance or open circuit between the power metal layer 303 and the plug interconnect structure 104, leading to poor current performance of the memory cell. If the numerical ratio is too small, the corresponding power metal layer 303 will have an excessively large size in the first direction x, and the spacing between adjacent power metal layers in the first direction x will be small. Compared to the case where the power metal layer 303 continuously penetrates the power region i, the capacitive coupling between the power metal layer 303 and the bit line metal layer 302 will not be significantly reduced, making it difficult to alleviate the RC delay of the memory cell, resulting in a slower read rate of the memory cell. In this embodiment, the numerical ratio of the spacing between adjacent power metal layers 303 to the size of the power metal layer 303 in the first direction x is 1 to 1.5.

[0084] In this embodiment, the power supply area i, bit line area ii, and grounding area iii are used as unit areas. The substrate includes a plurality of unit areas arranged in a matrix. The power supply areas i in adjacent unit areas are adjacent in the second direction y, and the power metal layers 303 in two power supply areas i are staggered in the first direction x. The power metal layers 303 in two power supply areas i are spaced apart in the second direction y. Alternatively, the grounding metal layers 301 in adjacent unit areas are adjacent in the second direction y.

[0085] Compared to the case where the power metal layer in the power region is a continuous metal layer, because multiple discrete power metal layers 303 are arranged along the first direction x in the power region i, the space between the power metal layer 303 in one power region i and the bit line metal layer 302 in the adjacent power region i is larger. Correspondingly, the capacitive coupling effect between the power metal layer 303 in one power region i and the power metal layer 303 in the adjacent power region i is weaker. When the memory cell is working, the RC delay of the memory cell can be reduced and the read performance of the memory cell can be improved.

[0086] It should be noted that in two adjacent cell regions, the bit line metal layer 302 in one cell region is a read port bit line (BL), and the bit line metal layer 302 in the other cell region is a complementary read port bit line (BLB).

[0087] It should be noted that, in the second direction y, the spacing between the power metal layers 303 in two adjacent power regions i should not be too large or too small. If the spacing between the power metal layers 303 in adjacent cell regions is too large, it is not conducive to improving the integration density of the memory cells, resulting in high power consumption of the memory cells. If the spacing between the power metal layers 303 in adjacent cell regions is too small, the capacitive coupling effect between the power metal layers 303 in adjacent cell regions is large, the RC delay of the corresponding memory cells is more severe, and the read rate of the memory cells is too slow; and if the spacing between the power metal layers 303 in adjacent cell regions is too small, the power metal layers 303 in adjacent cell regions are easily bridged, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the second direction y, the spacing between the power metal layers 303 in two adjacent power regions i is the minimum spacing in the process platform.

[0088] The storage unit includes a first via interconnect structure 110 located on the bit line metal layer 302, multiple discrete ground metal layers 301, power metal layer 303, and word line metal layer 304.

[0089] The first through-hole interconnect structure 110 is used to connect the bit line metal layer 302, multiple discrete ground metal layers 301, power metal layer 303 and word line metal layer 304 to the subsequent metal.

[0090] In this embodiment, the material of the first through-hole interconnect structure 110 includes one or more of W, Co and Cu.

[0091] The memory cell includes a fourth dielectric layer 111, located on the bit line metal layer 302, the third dielectric layer 109, a plurality of discrete ground metal layers 301, power metal layers 303, and word line metal layers 304 exposed on the first via interconnect structure 110.

[0092] The fourth dielectric layer 111 is used to electrically isolate the first via interconnect structure 110.

[0093] In this embodiment, the material of the fourth dielectric layer 111 is an insulating material. Specifically, the material of the fourth dielectric layer 111 includes silicon oxide.

[0094] The memory cell includes a first metal layer 113 located on the first via interconnect structure 110 and a portion of the fourth dielectric layer 111.

[0095] The first metal layer 113 is used to connect the first through-hole interconnect structure 110 to the subsequent metal layer.

[0096] In this embodiment, the material of the first metal layer 113 includes one or more of W, Co and Cu.

[0097] The memory cell includes a fifth dielectric layer 112 located on the fourth dielectric layer 111 exposed above the first metal layer 113. The fifth dielectric layer 112 is used to electrically isolate the first metal layer 113.

[0098] In this embodiment, the material of the fifth dielectric layer 112 is an insulating material. Specifically, the material of the fifth dielectric layer 112 includes silicon oxide.

[0099] The storage cell includes a second through-hole interconnect structure 114 located on the first metal layer 113.

[0100] The second through-hole interconnect structure 114 is used to connect the first metal layer 113 to the subsequent metal.

[0101] In this embodiment, the material of the second through-hole interconnect structure 114 includes one or more of W, Co and Cu.

[0102] The memory cell includes a sixth dielectric layer 115, located on the first metal layer 113 and the fifth dielectric layer 112 exposed by the second via interconnect structure 114. The sixth dielectric layer 115 is used to electrically isolate the second via interconnect structure 114.

[0103] In this embodiment, the material of the sixth dielectric layer 115 is an insulating material. Specifically, the material of the sixth dielectric layer 115 includes silicon oxide.

[0104] The memory cell includes: a second metal layer 116 located on the second via interconnect structure 114 of the power supply region i and on the sixth dielectric layer 115 on the side portion of the second via interconnect structure 114.

[0105] Compared to the case where the power metal layers in the power region are connected to external circuits (periphery) respectively, in this embodiment of the application, the second metal layer 116 is used to connect multiple second via interconnect structures 114 to external circuits simultaneously, so that multiple power metal layers 303 in the power region i can be connected to external circuits simultaneously, which helps to simplify the structure of the memory cell, improve the integration of the memory cell, and enable the memory cell to be better driven by the external circuit.

[0106] In this embodiment, the material of the second metal layer 116 includes one or more of W, Co and Cu.

[0107] In this embodiment, the substrate includes a plurality of cell regions arranged in a matrix at intervals. Correspondingly, the second metal layer 116 is simultaneously connected to the second via interconnect structure 114 of the power supply region i in two adjacent cell regions.

[0108] It should be noted that the second metal layer 116 is also located on the second via interconnect structure 114 of the grounding area iii and on the sixth dielectric layer 115 on the side portion of the second via interconnect structure 114.

[0109] The second metal layer 116 is also used to connect the word line metal layer 304 and the ground metal layer 301 in the grounding area iii to the external circuit at the same time, which helps to simplify the structure of the memory cell, improve the integration of the memory cell, and enable the memory cell to be better driven by the external circuit.

[0110] The storage cell includes a seventh dielectric layer 117 located on the sixth dielectric layer 115 exposed above the second metal layer 116.

[0111] The seventh dielectric layer 117 is used to electrically isolate the second metal layer 116.

[0112] In this embodiment, the material of the seventh dielectric layer 117 is an insulating material. Specifically, the material of the seventh dielectric layer 117 includes silicon oxide.

[0113] This application also provides a structure for an SRAM device. In this embodiment, the SRAM device includes a plurality of memory cells according to embodiments of this application. The SRAM device has low RC latency and high-speed read performance.

[0114] In this embodiment, the storage unit is widely used in PCs, personal communications, consumer electronics products (smart cards, digital cameras, multimedia players) and other fields.

[0115] This invention also provides a photomask. Combined with... Figures 5 to 7 A detailed explanation of photomasks will be provided. Figure 5 This is a schematic diagram of the semiconductor structure of this application. Figure 6 for Figure 5 Cross-sectional view at point BB. Figure 7 This is a schematic diagram of the structure of an embodiment of the photomask of this application.

[0116] The mask is used to form a memory cell, the memory cell including a semiconductor structure, the semiconductor structure including: a substrate, the substrate including a power region i, a bit line region ii and a junction region iii arranged in parallel along a first direction x, and in a second direction y, the bit line region ii is located between the power region i and the junction region iii, the second direction y is perpendicular to the first direction x;

[0117] The mask includes: a bit line metal pattern 201 for forming a bit line (BL) metal layer extending along a first direction x in the bit line region ii; a plurality of spaced-apart ground metal patterns 202 for forming a plurality of discrete ground metal layers (VSS power lines) along the first direction x in the ground region iii; and a plurality of spaced-apart power metal patterns 203 for forming a plurality of discrete power metal layers (VDD power lines) along the first direction x in the power region i.

[0118] The substrate includes a power region i, a bit line region ii, and a ground region iii arranged in parallel along a first direction x. In a second direction y, the bit line region ii is located between the power region i and the ground region iii. The second direction y is perpendicular to the first direction x. A bit line metal pattern 201 is used to form a bit line metal layer extending along the first direction x in the bit line region ii. A plurality of spaced-apart ground metal patterns 202 are used to form a plurality of discrete ground metal layers along the first direction x in the ground region iii. A plurality of spaced-apart power metal patterns 203 are used to form a plurality of discrete power metal layers along the first direction x in the power region i. Compared to the case where the power metal layers in the power region are continuous metal layers, in this embodiment of the application, in the power region i, multiple power metal layers are arranged at intervals along the first direction x. The power metal layers are island-shaped, and the space between them and the bit line metal layers is larger. As a result, the capacitive coupling effect between the multiple spaced power metal layers and the bit line metal layers is weaker. When the memory cell is working, the RC delay of the memory cell can be reduced, and the read performance of the memory cell can be improved.

[0119] The memory cell further includes: a gate structure 108 located between the bit line region ii and the junction region iii, and between the power supply region i and the bit line region ii; a source / drain doped layer 102 located on the substrate on both sides of the gate structure 108; a source / drain plug 103 located on the source / drain doped layer 102; and a plug interconnect structure 104 located on the source / drain plug 103.

[0120] This embodiment uses a FinFET (Fin Field-Effect Transistor) as an example of a transistor in a memory cell. The substrate includes a substrate 100 and fins 101 located on the substrate 100. In other embodiments, the transistor in the memory cell can also be a gate-to-all-around (GAA) transistor, and the corresponding substrate includes a substrate and a plurality of channel layers arranged with dangling spaces in the normal direction of the substrate surface.

[0121] In this embodiment, a six-transistor static random access memory (6T-SRAM) is used as an example. The corresponding memory cell includes a pull-up transistor (PU), a pull-down transistor (PD), and a pass-gate transistor (PG).

[0122] Specifically, the pull-up transistor is composed of a P-type metal oxide semiconductor (PMOS) transistor, while the pull-down transistor and the transmission transistor are composed of an N-type metal oxide semiconductor (NMOS) transistor.

[0123] In this embodiment, the substrate 100 provides a process platform for the subsequent formation of memory cells.

[0124] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium phosphate, and may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0125] It should be noted that the power supply area i, bit line area ii, and junction area iii are considered as unit areas.

[0126] In this embodiment, the fin 101 is made of silicon. In other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0127] When the semiconductor structure is in operation, the gate structure 108 (e.g.) Figure 6 (As shown) is used to control the opening and closing of the channel.

[0128] Specifically, the gate structure 108 spans the fin 101 and covers part of the sidewall and top wall of the fin 101.

[0129] In this embodiment, the gate structure 108 is a metal gate structure, including a work function layer (not shown in the figure) and a metal gate layer (not shown in the figure) located on the work function layer. In other embodiments, the gate structure may also be a polysilicon gate structure.

[0130] When the transistor is an NMOS, the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum, or titanium carbide; when the transistor is a PMOS, the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon nitride, titanium silicon nitride, and tantalum carbide.

[0131] In this embodiment, the material of the metal gate layer includes a magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer may also include W.

[0132] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0133] The pull-up transistor is composed of a P-type metal oxide semiconductor (PMOS) transistor. When the semiconductor structure is working, the source and drain doping layers 102 apply compression stress to the channel below the gate. Compression of the channel can improve the hole mobility. Accordingly, the source and drain doping layers 102 of the pull-up transistor are doped with P-type ions, which include one or more of B, Ga and In.

[0134] The pull-down transistor and the transfer transistor are composed of N-type metal oxide semiconductor (NMOS) transistors. When the semiconductor structure is operating, the source and drain doping layers 102 apply tensile stress to the channel below the gate structure. Stretching the channel can improve the electron migration rate. Accordingly, the source and drain doping layers 102 of the pull-down transistor and the transfer transistor are doped with N-type ions, including one or more of P, As, and Sb.

[0135] The semiconductor structure further includes an interlayer dielectric layer 105 located on the sidewall of the gate structure 108, wherein the top surface of the interlayer dielectric layer 105 is lower than or flush with the top surface of the gate structure 108.

[0136] The interlayer dielectric layer 105 is used for electrical isolation of adjacent devices. In this embodiment, the material of the interlayer dielectric layer 105 is an insulating material. Specifically, the material of the interlayer dielectric layer 105 includes silicon oxide.

[0137] The semiconductor structure further includes a first dielectric layer 106, located on the gate structure 108 and the interlayer dielectric layer 105.

[0138] The first dielectric layer 106 and the interlayer dielectric layer 105 are used to electrically isolate adjacent devices.

[0139] In this embodiment, the material of the first dielectric layer 106 is an insulating material. Specifically, the material of the first dielectric layer 106 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the first dielectric layer 106.

[0140] The source / drain plug 103 penetrates the first dielectric layer 106 and the interlayer dielectric layer 105 and is connected to the source / drain doped layer 102.

[0141] Specifically, the power metal layer formed according to the power metal pattern 203 in the power region i is connected to the drain in the source-drain doped layer 102 through the source-drain plug 103, and the ground metal layer formed according to the ground metal pattern 202 in the ground region iii is connected to the drain in the source-drain doped layer 102 of the pull-down transistor through the source-drain plug 103.

[0142] In this embodiment, the source / drain plug 103 is made of a conductive material. Specifically, the conductive material includes W or Co. In this embodiment, the source / drain plug 103 is made of W. W has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0143] The semiconductor structure further includes a second dielectric layer 107 located on the source / drain plug 103 and the first dielectric layer 106.

[0144] In this embodiment, the material of the second dielectric layer 107 is an insulating material. Specifically, the material of the second dielectric layer 107 includes silicon oxide.

[0145] The semiconductor structure further includes a plug interconnect structure 104, which penetrates the second dielectric layer 107 and is connected to the source / drain plug 103.

[0146] In this embodiment, the material of the plug interconnect structure 104 is a conductive material. Specifically, the conductive material includes one or more of W, Co, and Cu. In this embodiment, the material of the plug interconnect structure 104 is Cu. Cu has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure.

[0147] In this embodiment, the semiconductor structure further includes a third dielectric layer 109, located on the plug interconnect structure 104 and the second dielectric layer 107.

[0148] In this embodiment, the material of the third dielectric layer 109 is an insulating material. Specifically, the material of the third dielectric layer 109 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material.

[0149] The mask includes: a bit line metal pattern 201 for forming a bit line metal layer extending along a first direction x in the bit line region ii; a plurality of spaced-apart ground metal patterns 202 for forming a plurality of discrete ground metal layers along the first direction x in the ground region iii; and a plurality of spaced-apart power metal patterns 203 for forming a plurality of discrete power metal layers along the first direction in the power region i.

[0150] The power metal pattern 203 is used to form a power metal layer that penetrates the third dielectric layer 109 in the power region i and is connected to the plug interconnect structure 104.

[0151] The power metal layer is for the VDD power supply wiring of the memory cell.

[0152] The power metal layer formed according to the power metal pattern 203 is used to connect to the pull-up transistor. Specifically, the power metal layer is connected to the drain of the pull-up transistor.

[0153] The bit line metal pattern 201 is used to form a bit line metal layer, which penetrates the third dielectric layer 109 in the bit line region ii and is connected to the plug interconnect structure 104.

[0154] The bit line metal layer is used as a read port bit line (BL) or a complementary read port bit line (BLB). The bit line metal pattern 201 is used to connect to the drain of the source / drain doped layer 102.

[0155] The grounding metal pattern 202 is used to form a grounding metal layer that penetrates the third dielectric layer 109 in the grounding area iii and is connected to the plug interconnect structure 104.

[0156] The grounding metal layer is the VSS power supply wiring of the storage unit.

[0157] In this embodiment, the ground metal pattern 202 and the power metal pattern 203 correspond to each other in a direction perpendicular to the bit line metal pattern 201.

[0158] The mask further includes: a word line metal pattern 204, spaced apart from the ground metal pattern 202, for forming a plurality of discrete word line metal layers along the first direction x in the grounding region iii, and spaced apart from the ground metal layer. The word line metal layers penetrate the third dielectric layer 109 in the grounding region iii and are connected to the plug interconnect structure 104.

[0159] The word line metal layer is used to connect to the gate structure 108.

[0160] It should be noted that, in the mask, the ratio of the spacing between adjacent power metal patterns 203 to the size of the power metal pattern 203 in the extension direction of the bit line metal pattern 201 should not be too large or too small. If the ratio is too large, that is, if the power metal pattern 203 is too small in the extension direction of the bit line metal pattern 201, the size of the power metal layer formed in the first direction x will be too small. As the size of the memory cell becomes smaller and smaller, during the etching of the third dielectric layer 109 using the mask to form an opening, even if there is a slight overlay error in the mask, the opening may expose part of the plug interconnect structure 104, or in extreme cases, the plug interconnect structure 104 may not be exposed at all. Consequently, the contact resistance between the power metal layer formed in the opening and the plug interconnect structure 104 will be large or open, resulting in poor current performance of the semiconductor structure. If the numerical ratio is too small, the power metal pattern 203 will be too large in the extension direction of the bit line metal pattern 201. Consequently, the size of the power metal layer in the first direction x will be too large, and the spacing between adjacent power metal layers in the first direction x will be small. Compared with the case where the power metal layer continuously penetrates the power region i, the capacitive coupling between the power metal layer and the bit line metal layer will not be significantly reduced, making it difficult to alleviate the RC delay of the memory cell, resulting in a slower read rate of the memory cell. In this embodiment, in the extension direction of the bit line metal pattern 201, the numerical ratio of the spacing between adjacent power metal patterns 203 to the size of the power metal pattern 203 is 1 to 1.5.

[0161] In this embodiment, the bit line metal pattern 201, the multiple spaced ground metal patterns 202, and the multiple spaced power metal patterns 203 serve as unit patterns. The mask includes multiple unit patterns arranged in a matrix. In the extension direction perpendicular to the bit line metal pattern 201, the power metal patterns 203 in two unit patterns are spaced apart. In the extension direction of the bit line metal pattern 201, the power metal patterns 203 in two unit patterns are staggered.

[0162] Accordingly, based on the mask configuration, in the memory cell, the power metal layers formed in the two power regions i are staggered in the first direction x, and the power metal layers in the two power regions i are spaced apart in the second direction y. Compared with the case where the power metal layers in the power regions are continuous metal layers, because the multiple power metal layers in the power regions i are spaced apart along the first direction, the space between the power metal layer in one power region i and the bit line metal layer in its adjacent power region i is larger. Consequently, the capacitive coupling effect between the power metal layer in one power region i and the power metal layer in its adjacent power region i is weaker. When the memory cell is working, the RC delay of the memory cell can be reduced, and the read performance of the memory cell can be improved.

[0163] It should be noted that in two adjacent cell regions, the bit line metal layer in one cell region is a read port bit line (BL), and the bit line metal layer in the other cell region is a complementary read port bit line (BLB).

[0164] refer to Figures 8 to 10 This application also provides another photomask, in which the film layer formed by the photomask is located above the power metal layer, bit line metal layer and ground metal layer mentioned in the previous embodiment. Figure 8 This is a schematic diagram of an embodiment of the semiconductor structure of this application. Figure 9 for Figure 8 Cross-sectional view at CC Figure 10 This is a schematic diagram of yet another embodiment of the mask template of this application.

[0165] A photomask is used to form a memory cell, the memory cell including a semiconductor structure, the semiconductor structure including: a substrate, the substrate including a power region i, a bit line region ii and a ground region iii arranged in parallel along a first direction x, and in a second direction y, the bit line region ii being located between the power region i and the ground region iii, the second direction y being perpendicular to the first direction x; a ground metal layer 301 located in the ground region iii and extending along the first direction x; a bit line metal layer 302 located in the bit line region ii and extending along the first direction x; a plurality of discrete power metal layers 303 arranged along the first direction x in the power region i; a first via interconnect structure 110 located on the bit line metal layer 302, the plurality of discrete ground metal layers 301, the power metal layer 303 and the word line metal layer 304; a first metal layer 113 located on the first via interconnect structure 110; and a second via interconnect structure 114 located on the first metal layer 113.

[0166] The mask includes: interconnect pattern 400 (such as...) Figure 10As shown), it is used to form a second metal layer, and the second metal layer is located on the second via interconnect structure 114 of the power supply area i. The second metal layer is simultaneously connected to a plurality of second via interconnect structures 114.

[0167] In this embodiment, multiple discrete power metal layers 303 are arranged at intervals along a first direction x. In the first direction, there is no metal between the power metal layers 303. Therefore, the capacitive coupling effect between the multiple power metal layers 303 arranged at intervals along the first direction x and the bit line metal layer 302 is weak, which can reduce the RC delay of the memory cell and improve the read performance of the memory cell. Because the power metal layers 303 are multiple discrete layers, the first via interconnect structure 110 is located on the power metal layer 303, the first metal layer 113 is located on the first via interconnect structure 110, and the second via interconnect structure 114 is located on the first metal layer 113. The interconnect pattern 400 in the mask is used to form the second metal layer. The second metal layer is simultaneously connected to the multiple power metal layers 303 in the power region i through the second via interconnect structure 114, the first metal layer 113, and the first via interconnect structure 110. Compared with the case where the power metal layers in the power region i are individually connected to external circuits, in this embodiment, the multiple power metal layers 303 in the power region i can be simultaneously connected to external circuits, which helps to simplify the structure of the memory cell, improve the integration of the memory cell, and enable the memory cell to be better driven by external circuits.

[0168] The bit line region ii, the junction region iii, and the power region i are used as unit regions. The substrate includes a plurality of unit regions arranged in a matrix. The power regions i in adjacent unit regions are adjacent in the second direction y, or the junction regions iii in adjacent unit regions are adjacent in the second direction y. The power metal layers 303 in two power regions i are staggered in the first direction x, and the power metal layers 303 in two power regions i are spaced apart in the second direction y. The mask is configured to connect the second metal layer formed by the interconnect pattern to the second via interconnect structure 114 in two adjacent power regions i.

[0169] The power supply regions i in the adjacent cell regions are adjacent in the second direction y. The second metal layer formed according to the interconnect pattern is located on the two power supply regions i. The second metal layer is simultaneously connected to the multiple power supply metal layers 303 in the power supply region i through the second via interconnect structure 114, the first metal layer 113, and the first via interconnect structure 110. Compared with the case where the power supply metal layers in the power supply region i are connected to external circuits respectively, in the embodiment of this application, the multiple power supply metal layers 303 in the power supply region i can be connected to external circuits simultaneously, which is beneficial to simplify the structure of the memory cell, improve the integration of the memory cell, and enable the memory cell to be better driven by external circuits.

[0170] In this embodiment, the substrate includes a plurality of cell regions arranged in a matrix at intervals. Correspondingly, the second metal layer formed according to the interconnect pattern is connected to the second via interconnect structure 114 of the power supply region i in two adjacent cell regions.

[0171] It should be noted that the second metal layer formed according to the interconnect pattern is also used to connect the word line metal layer 304 and the ground metal layer 301 in the ground area iii to the external circuit at the same time, which helps to simplify the structure of the memory cell, improve the integration of the memory cell, and enable the memory cell to be better driven by the external circuit.

[0172] The semiconductor structure further includes: a gate structure 108 located between the bit line region ii and the junction region iii, and between the power supply region i and the bit line region ii; a source / drain doped layer 102 located on the substrate on both sides of the gate structure; a source / drain plug 103 located on the source / drain doped layer 102; and a plug interconnect structure 104 located on the source / drain plug 103.

[0173] Correspondingly, the ground metal layer 301 is located on the plug interconnect structure 104 of the ground region iii, the bit line metal layer 302 is located on the plug interconnect structure 104 of the bit line region ii, and a plurality of discrete power metal layers 303 are located on the plug interconnect structure 104 of the power region i.

[0174] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, include: The substrate includes a power region, a bit line region, and a ground region arranged in parallel along a first direction, and in a second direction, the bit line region is located between the power region and the ground region, and the second direction is perpendicular to the first direction; A bit line metal layer is located in the bit line region, and the bit line metal layer extends along the first direction; Multiple discrete grounding metal layers are arranged along a first direction in the grounding area; Multiple discrete power metal layers are arranged along a first direction in the power region; In the first direction, the spacing between adjacent power metal layers is in a numerical ratio of 1 to 1.5 to the size of the power metal layer.

2. The storage unit as claimed in claim 1, characterized in that, The power region, bit line region, and junction region are used as unit regions. The substrate includes a plurality of unit regions arranged in a matrix. The power regions in adjacent unit regions are adjacent in the second direction. The power metal layers in two power regions are staggered in the first direction. The power metal layers in two power regions are spaced apart in the second direction.

3. The storage unit as described in claim 1, characterized in that, The memory cell further includes: a gate structure located between the bit line region and the ground region, and between the power supply region and the bit line region; Source and drain doped layers are located on the substrate on both sides of the gate structure; Source / drain plugs are located on the source / drain doped layer; A plug interconnect structure is located on the source / drain doped layer.

4. The storage unit as described in claim 1 or 3, characterized in that, The memory cell includes: a first via interconnect structure located on the ground metal layer, the bit line metal layer, and a plurality of discrete power metal layers; A first metal layer is located on the first through-hole interconnect structure; The second via interconnect structure is located on the first metal layer; The second metal layer is located on the second via interconnect structure of the power supply area.

5. The storage unit as claimed in claim 1, characterized in that, The storage unit further includes: a plurality of discrete word line metal layers arranged along a first direction in the ground area, wherein the word line metal layers are spaced apart from the ground metal layer.

6. The storage unit as claimed in claim 1, characterized in that, The memory unit includes: a pull-up transistor, a pull-down transistor, and a transmission gate transistor; The power metal layer is used to connect to the pull-up transistor.

7. A photomask for forming a memory cell, the memory cell comprising a semiconductor structure, the semiconductor structure comprising: The substrate includes a power region, a bit line region, and a ground region arranged in parallel along a first direction, and in a second direction, the bit line region is located between the power region and the ground region, and the second direction is perpendicular to the first direction; The photomask is characterized in that it comprises: Bit line metal pattern, used to form a bit line metal layer extending in a first direction in the bit line region; Multiple spaced-apart grounding metal patterns are used to form multiple discrete grounding metal layers along a first direction in the grounding area; Multiple spaced power metal patterns are used to form multiple power metal layers discrete along a first direction in the power region. In the mask, the ratio of the spacing between adjacent power metal patterns to the size of the power metal pattern is 1 to 1.5 in the extending direction of the bit line metal pattern.

8. The photomask as described in claim 7, characterized in that, The bit line metal pattern, multiple spaced ground metal patterns, and multiple spaced power metal patterns serve as unit patterns, and the mask includes multiple such unit patterns arranged in a matrix. In the extension direction perpendicular to the bit line metal pattern, the power supply metal patterns in the two unit patterns are spaced apart; In the extending direction of the bit line metal pattern, the power metal patterns in the two unit patterns are staggered.

9. The photomask as described in claim 7, characterized in that, The power supply area, bit line area, and junction area are used as unit areas, and the substrate includes a plurality of the unit areas arranged in a matrix at intervals. The power supply areas in adjacent unit areas are adjacent in the second direction, or the grounding areas in adjacent unit areas are adjacent in the second direction; The mask is configured in the memory cell such that the power metal layers formed in the two power regions are staggered in the first direction and the power metal layers in the two power regions are spaced apart in the second direction.

10. The photomask as described in claim 7, characterized in that, The mask further includes: word line metal patterns, spaced apart from the ground metal patterns, for forming a plurality of word line metal layers discrete along a first direction in the ground area, and spaced apart from the ground metal layers.

11. The photomask as described in claim 7, characterized in that, The semiconductor structure further includes: a gate structure located between the bit line region and the ground region, and between the power supply region and the bit line region; Source and drain doped layers are located on the substrate on both sides of the gate structure; Source / drain plugs are located on the source / drain doped layer; A plug interconnection structure is located on the source-drain plug.

12. The photomask as described in claim 7, characterized in that, The semiconductor structure includes: a pull-up transistor, a pull-down transistor, and a transmission gate transistor; The power metal layer, formed according to the power metal pattern, is used to connect to the pull-up transistor.

13. A photomask for forming a memory cell, the memory cell comprising a semiconductor structure, the semiconductor structure comprising: The substrate includes a power region, a bit line region, and a ground region arranged in parallel along a first direction, and in a second direction, the bit line region is located between the power region and the ground region, and the second direction is perpendicular to the first direction; A grounding metal layer is located in the grounding area and extends along the first direction; Bit line metal layer, located in the bit line region and extending along the first direction; Multiple discrete power metal layers are arranged along a first direction in the power region; Wherein, in the first direction, the spacing between adjacent power metal layers is in a numerical ratio of 1 to 1.5 to the size of the power metal layer; The first via interconnect structure is located on the ground metal layer, the bit line metal layer, and multiple discrete power metal layers; A first metal layer is located on the first through-hole interconnect structure; The second via interconnect structure is located on the first metal layer; The photomask is characterized in that it comprises: An interconnect pattern is used to form a second metal layer, and the second metal layer is located on the second via interconnect structure of the power supply area, and the second metal layer is simultaneously connected to a plurality of second via interconnect structures.

14. The photomask as described in claim 13, characterized in that, The bit line region, the junction region, and the power region are used as unit regions, and the substrate includes a plurality of the unit regions arranged in a matrix at intervals. The power supply regions in adjacent unit regions are adjacent in the second direction, the power supply metal layers in the two power supply regions are staggered in the first direction, and the power supply metal layers in the two power supply regions are spaced apart in the second direction; The mask is configured to simultaneously connect the second metal layer formed by the interconnect pattern and the second via interconnect structure in the two adjacent power regions.

15. An SRAM device, characterized in that, include: The storage unit as described in any one of claims 1 to 6.

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