True random number generator circuit

Abstract

The present invention discloses a true random number random source generating circuit, including a plurality of ring oscillators and a plurality of random source receivers, each ring oscillator is connected to a corresponding random source receiver; each ring oscillator includes a ring selector and a plurality of inverters; the output end of the ring selector is connected to an inverter, and each inverter is connected in series in sequence; the output end of the inverter is set to be also connected to the input end of the ring selector; each random source receiver includes a logic mixer, at least two D flip-flops, a comparator and an unstable counter; the output end of the logic mixer is respectively connected to the input end of each D flip-flop, the output end of each D flip-flop is connected to the input end of the corresponding comparator, and the output end of the comparator is connected to the input end of the unstable counter. The present invention can reduce the time for designing the ring oscillator before and after the tape-out, and can achieve the best randomness by adjusting the oscillator frequency after the tape-out; at the same time, the chip of the present invention can achieve the best randomness in different working environments.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits and relates to a random source generating circuit, in particular to a true random number random source generating circuit. Background Art

[0002] Due to the booming development of the Internet of Things, more and more devices can be connected to the Internet. Traditional devices that do not connect to the Internet often have lower security requirements, because unless the device is physically connected to the intruder, it is generally not easy to leak user data. In contrast, IoT devices do not require physical contact to connect, and it is easy to steal data when transmitting data through the air as a medium. In order to protect the security of user data, data encryption transmission is a necessary function of IoT devices. Encryption security is based on the strength of the key. And high-strength keys are generated by true random number generators.

[0003] The common architecture of a true random number generator is composed of a random source generator and a random number generator. Since there is a public protocol standard for random number generators (NIST 800-90A), it is sufficient to design them according to the protocol. However, the protocol standard (NIST 800-90B) for random source generators only defines the method for testing performance, but does not specify the design method. It is sufficient to design a random source generator that is sufficiently random to pass the protocol test.

[0004] In the open literature, there are discussions about using static random access memory (SRAM), analog-to-digital converter (ADC), or double data rate synchronous dynamic random access memory (DDR) as a noise source. The noise source quality of these methods is very good, but the area cost is very high. They are rarely seen in actual mass-produced products. The common practice in mass-produced products is to use a ring-oscillator as a noise source generator. Figure 1 shown.

[0005] The loop is composed of an odd number of inverters, and the end of the loop is connected to a D flip-flop. The output of the D flip-flop is used as the output of the chaos source generator. The timing of the D and CK ends of the D flip-flop is as follows: Figure 2 , Figure 3 shown.

[0006] Because the clock (CK) frequency of the D flip-flop is different from the frequency of the ring oscillator, when the clock does not meet the D flip-flop setup time at t1, t5, and t9, the data tapped will become unstable. By utilizing this unstable characteristic, the data obtained each time is random, so it can be used as a random source for the random number generator.

[0007] To increase randomness, you can use n ring oscillators (chain_0~n), and then connect the outputs of the D flip-flops together with XOR gates as the output of the random source generator, such as Figure 4shown.

[0008] Taking n=2 as an example, the D flip-flop clock will hit an unstable state at t1, t2, t5, t9, and t10. Compared with the original ring oscillator, the probability of hitting an unstable state increases. Figure 5 shown.

[0009] This approach has the following disadvantages:

[0010] (1) By Figure 5 It can be seen that during the time period from t0 to t10, although the clock will hit unstable data at t1, t2, t5, t9, and t10, it will hit stable data at most times t0, t3, t4, t6, t7, and t8, which is not random. Therefore, the overall randomness of the ring oscillator is not good.

[0011] (2) Since the ring oscillator has only one bit output, each clock can only obtain one bit random source, the throughput is very low, which prolongs the time to generate the key;

[0012] (3) To achieve high randomness and throughput, more ring oscillators must be added, which will generate additional area and power consumption, which is inconsistent with the low power consumption requirements of IoT products.

[0013] (4) The randomness of the random source generator can only be tested after tape-out, and the number of inverters in the ring oscillator cannot be changed once it is taped out. If the random source is not random enough during testing after tape-out, there is no way to improve it.

[0014] In view of this, there is an urgent need to design a new random number source generation method to overcome at least some of the above-mentioned defects of the existing random number source generation method. Summary of the invention

[0015] The present invention provides a true random number random source generation circuit, which can reduce the time of designing a ring oscillator before and after tape-out, and can achieve the best randomness by adjusting the oscillator frequency after tape-out; thereby achieving the best randomness in different working environments.

[0016] In order to solve the above technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0017] A true random number random source generating circuit, the true random number random source generating circuit comprising: a plurality of ring oscillators and a plurality of random source receivers, each ring oscillator being connected to a corresponding random source receiver;

[0018] Each ring oscillator includes a ring selector and a plurality of inverters; the output end of the ring selector is connected to an inverter, and the inverters are connected in series in sequence; the output end of the inverter is set to be also connected to the input end of the ring selector;

[0019] Each random source receiver includes a logic mixer, at least two D flip-flops, a comparator and an astable counter; the output end of the logic mixer is respectively connected to the input end of each D flip-flop, the output end of each D flip-flop is connected to the input end of the corresponding comparator, and the output end of the comparator is connected to the input end of the astable counter.

[0020] As an implementation mode of the present invention, the true random number source generation circuit includes n+1 ring oscillators, each ring oscillator includes m+1 inverters; wherein n is a positive integer and m is an even number;

[0021] In ring oscillator i, the output of the jth inverter is defined as cij, and the ring selector serves as the input end of the ring oscillator; wherein, 0≤i≤n, 0≤j≤m; when j is an even number, the output end of the jth inverter is connected to the input end of the corresponding ring selector.

[0022] As an implementation mode of the present invention, the true random number random source generation circuit includes n+1 random source receivers; the inverter output cij of the previous ring oscillator is used as the input of the corresponding random source receiver;

[0023] The logic mixer selects any number of cij and combines them into 1 bit using logic gates, and the output of the logic mixer is simultaneously connected to the input of at least two D flip-flops;

[0024] Each random source receiver includes two D flip-flops, namely a first D flip-flop and a second D flip-flop; the output of the first D flip-flop is the random source generator output, which can provide a random source for the random number generator. Since there are a total of n+1 random source receivers, each clock cycle can provide n+1 random source bits; the second D flip-flop is used to detect whether the random source is in an unstable state;

[0025] The outputs of the two D flip-flops are connected together using a comparator, and the output result of the comparator is transmitted to an unstable counter. Whenever the output results of the two D flip-flops are different, the comparator outputs 1 and the unstable counter increases by 1. The unstable counter counts within a configured unit time, and the counting result is the number of times the unstable state occurs within the unit time, which is used to evaluate the performance of this chaotic source.

[0026] As an implementation mode of the present invention, a random source generator is designed according to the above architecture during the chip design stage. When the chip is taped out, the random source is adjusted according to the following steps when it is turned on for the first time:

[0027] (1) Initialize n, wn, u to 0 and s to 2;

[0028] (2) Configure the ring n selector to s;

[0029] (3) Read the value of the ring n unstable counter to u;

[0030] (4) If the current u is greater than u' in the previous round, then wn is equal to s. Otherwise, wn is not updated. Then s is updated to s' plus 2 and steps (1) to (3) are repeated until s is equal to m.

[0031] (5) Record the value of wn, n is equal to n' plus 1, repeat steps (1) to (4) to obtain the values ​​of all w0 to wn, and store the value of wn in the non-volatile memory;

[0032] (6) After the subsequent power-on, the value of wn is read from the non-volatile memory and configured to chain_n_select, and the random source generator can be used normally without repeating steps (1) to (5).

[0033] The beneficial effects of the present invention are as follows: the true random number source generation circuit proposed by the present invention contains a ring selector, which can change the frequency of the ring oscillator through configuration, so there is no need to determine the frequency of the ring oscillator before tape-out; compared with common practices, the present invention can reduce the time for designing the ring oscillator before and after tape-out, and can achieve the best randomness by adjusting the oscillator frequency after tape-out. At the same time, due to this feature, the chip of the present invention can achieve the best randomness under different working environments (temperature, voltage, humidity, manufacturing).

[0034] The present invention uses a logic mixer to collect the inverter outputs of the ring oscillator together, and utilizes this characteristic to collect the random characteristics of different ring oscillators, which can greatly improve the throughput of randomness and chaotic sources at a slightly increased cost.

[0035] The present invention can use two or more D flip-flops to be directly connected to the logic mixer at the same time. The principle is that when two or more D flip-flops receive data, because their physical characteristics are very close, if their results are different, it means that the gate voltage of the D flip-flop at that time point is in a critical state, and it is inferred that there is randomness at this time. The conventional practice is to use the output of the D flip-flop to determine whether there is randomness, because the output of the flip-flop is the result after sampling, and there is no way to know the conditions at the time of sampling. By checking whether there is a specific pattern in the output of the D flip-flop, it can only be roughly estimated. If a complete test is required, a large number of mathematical tests in the protocol standard (NIST 800-90B) are required to obtain the results, which is very costly.

[0036] The present invention can evaluate the randomness of each ring oscillator through a random source receiver after tape-out, and optimize the randomness of the random source generator by configuring a random source selector. The present invention can generate n bits of random sources at a time, and the throughput is n times that of the traditional throughput architecture.

[0037] Compared with the traditional architecture, the present invention can achieve the same randomness by using fewer ring oscillators, thereby reducing the area and power consumption of the oscillator.

[0038] The present invention uses a pure digital circuit. Since the standard logic gate level used by the digital circuit is small and the bottom metal layer can be used for wiring, it is difficult to locate the position of the chaos source generator from the layout, so it can effectively resist hacker cover opening attacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 The figure is a circuit diagram of a chaos source generating circuit in the prior art.

[0040] Figure 2 for Figure 1 The timing diagram of the D-terminal and CK-terminal of the D-type flip-flop.

[0041] Figure 3 for Figure 2 The timing diagram of the D and CK ends of the D flip-flop is enlarged.

[0042] Figure 4 A schematic diagram of a random number source generating circuit in the prior art

[0043] Figure 5 for Figure 4 The timing diagram of the D-terminal and CK-terminal of the D-type flip-flop.

[0044] Figure 6 FIG. 4 is a schematic diagram of the composition of a true random number source generating circuit in one embodiment of the present invention.

[0045] Figure 7 FIG. 4 is a circuit diagram of a ring oscillator according to an embodiment of the present invention.

[0046] Figure 8 FIG. 4 is a circuit diagram of a random source receiver according to an embodiment of the present invention.

[0047] Fig. 9 FIG. 4 is a circuit diagram of a ring oscillator according to an embodiment of the present invention.

[0048] Fig.10 FIG. 4 is a circuit diagram of a random source receiver according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0050] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0051] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0052] The description of the steps in each embodiment in the specification is only for the convenience of explanation, and the implementation method of the present application is not limited by the order of implementation of the steps.

[0053] The term "connection" as used in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0054] The present invention discloses a true random number source generating circuit. Figure 6 This is a schematic diagram of the composition of the true random number source generation circuit of the present invention; please refer to Figure 6 The true random number random source generating circuit includes: a plurality of ring oscillators 1 and a plurality of random source receivers 2, and each ring oscillator 1 is connected to a corresponding random source receiver 2.

[0055] Figure 7 is a circuit diagram of a ring oscillator in one embodiment of the present invention; please refer to Figure 7 , each ring oscillator 1 includes a ring selector 11 and a plurality of inverters 12; the output end of the ring selector is connected to an inverter, and each inverter is connected in series in sequence; the output end of the inverter is set to be also connected to the input end of the ring selector;

[0056] Figure 8 is a circuit diagram of a random source receiver in one embodiment of the present invention; please refer to Figure 8 Each random source receiver 2 includes a logic mixer 21, at least two D flip-flops 22, a comparator 23 and an unstable counter 24; the output end of the logic mixer 21 is respectively connected to the input end of each D flip-flop 22, the output end of each D flip-flop 22 is connected to the input end of the corresponding comparator 23, and the output end of the comparator 23 is connected to the input end of the unstable counter 24.

[0057] In one embodiment of the present invention, the true random number source generation circuit includes n+1 ring oscillators 1, and each ring oscillator 1 includes m+1 inverters 12; wherein n is a positive integer and m is an even number.

[0058] In ring oscillator i, the output of the jth inverter is defined as cij, and the ring selector serves as the input end of the ring oscillator; wherein, 0≤i≤n, 0≤j≤m; when j is an even number, the output end of the jth inverter is connected to the input end of the corresponding ring selector.

[0059] In one embodiment of the present invention, the true random number random source generation circuit includes n+1 random source receivers 2; the inverter output cij of the previous ring oscillator is used as the input of the corresponding random source receiver. The logic mixer selects a number of random numbers from cij and uses logic gates to collect them into 1 bit, and the output of the logic mixer is simultaneously connected to at least two D flip-flop inputs.

[0060] like Figure 7 As shown, in one embodiment, each random source receiver 2 includes two D flip-flops, namely a first D flip-flop 221 and a second D flip-flop 222. The output of the first D flip-flop 221 is a random source generator output, which can provide a random source for a random number generator. Since there are a total of n+1 random source receivers 2, each clock cycle can provide n+1 random source bits; the second D flip-flop 222 is used to detect whether the random source is in an unstable state.

[0061] The outputs of the two D flip-flops 22 are connected together using a comparator, and the output result of the comparator is transmitted to an unstable counter. Whenever the output results of the two D flip-flops are different, the comparator outputs 1, and the unstable counter increases by 1. The unstable counter counts within a configured unit time, and the counting result is the number of unstable states occurring within a unit time, which is used to evaluate the performance of this chaotic source.

[0062] In one embodiment of the present invention, the random source generator is designed according to the above architecture during the chip design stage. When the chip is taped out, the random source is adjusted according to the following steps when it is first powered on:

[0063] (1) Initialize n, wn, u to 0 and s to 2;

[0064] (2) Configure the ring n selector to s;

[0065] (3) Read the value of the ring n unstable counter to u;

[0066] (4) If the current u is greater than u' in the previous round, then wn is equal to s. Otherwise, wn is not updated. Then s is updated to s' plus 2 and steps (1) to (3) are repeated until s is equal to m.

[0067] (5) Record the value of wn, n is equal to n' plus 1, repeat steps (1) to (4) to obtain the values ​​of all w0 to wn, and store the value of wn in the non-volatile memory;

[0068] (6) After the subsequent power-on, the value of wn is read from the non-volatile memory and configured to chain_n_select, and the random source generator can be used normally without repeating steps (1) to (5).

[0069] The present invention is further described below by taking m equal to 6 and n equal to 2 as an example.

[0070] M is 6, which means there are 7 inverters on each ring oscillator. n is 2, which means there are 3 ring oscillators in total. The input of Ring 0 oscillator is a Ring 0 selector, which can select c02, c04, and c06 as input, and so on for Ring 1 oscillator and Ring 2 oscillator.

[0071] Since n is 2, it means there are 3 random source receivers in total. Each random source receiver is composed of a logic mixer, two D flip-flops, a comparator, and an unstable counter. The logic mixers are c02, c13, and c26 connected together with an XOR gate. The output of the first D flip-flop is the output of the random source generator, which can provide a random source for the random number generator. Since there are 3 random source receivers in total, 3 random source bits can be provided for each clock cycle. The second D flip-flop is used to detect the instability of the random source. The outputs of the two D flip-flops are connected together using a comparator (XOR gate), and the output results are given to the unstable counter. Whenever the output results of the two D flip-flops are different, the unstable counter will increase by 1 and count the number of unstable states occurring per unit time within the configured time to evaluate the performance of this random source.

[0072] When the chip is taped out, adjust the source of noise according to the following steps when starting up for the first time:

[0073] (1) Initialize n, wn, u to 0 and s to 2;

[0074] (2) Configure the ring n selector to s;

[0075] (3) Read the value of the ring n unstable counter to u;

[0076] (4) If the current u is greater than the previous round u', then wn is equal to s. Otherwise, wn is not updated. Then s is updated to s' plus 2 and steps (2) to (3) are repeated until s is equal to 6.

[0077] (5) Record the value of wn, n is equal to n' plus 1, repeat steps 1 to 4 to obtain all the values ​​of w0 to w2, and store the values ​​of w0 to w2 in the non-volatile memory;

[0078] (6) After the power is turned on, the values ​​of w0~w2 are read out from the non-volatile memory and configured to chain_0_select~chain_2_select, and the random source generator can be used normally.

[0079] In one usage scenario of the present invention, the ring n selector can select the inverter output cnm on the ring n as the input signal for adjusting the operating frequency of the ring.

[0080] The logic mixer randomly selects several bits from the cnm and combines them into 1 bit using logic gates. This feature can greatly increase randomness and improve throughput without adding a ring oscillator.

[0081] The second or more D flip-flops of the random source receiver are connected to the mixer output to detect the instability of the random source and give the output result to the instability counter. Whenever the output results of the two D flip-flops are different, the instability counter will increase by 1 and count the number of instabilities occurring per unit time within the configured time to evaluate the performance of this random source.

[0082] Steps (1) to (6) of adjusting the random source can obtain the best randomness through real measurement. Due to this characteristic, the present invention can achieve the best randomness in various extreme environments (temperature, voltage, manufacturing).

[0083] In summary, the true random number source generation circuit proposed by the present invention contains a ring selector, which can change the frequency of the ring oscillator through configuration, so there is no need to determine the frequency of the ring oscillator before tape-out; compared with the common practice, the present invention can reduce the time for designing the ring oscillator before and after tape-out, and can achieve the best randomness by adjusting the oscillator frequency after tape-out. At the same time, due to this feature, the chip of the present invention can achieve the best randomness under different working environments (temperature, voltage, humidity, manufacturing).

[0084] The present invention uses a logic mixer to collect the inverter outputs of the ring oscillator together, and utilizes this characteristic to collect the random characteristics of different ring oscillators, which can greatly improve the throughput of randomness and chaotic sources at a slightly increased cost.

[0085] The present invention can use two or more D flip-flops to be directly connected to the logic mixer at the same time. The principle is that when two or more D flip-flops receive data, because their physical characteristics are very close, if their results are different, it means that the gate voltage of the D flip-flop at that time point is in a critical state, and it is inferred that there is randomness at this time. The conventional practice is to use the output of the D flip-flop to determine whether there is randomness, because the output of the flip-flop is the result after sampling, and there is no way to know the conditions at the time of sampling. By checking whether there is a specific pattern in the output of the D flip-flop, it can only be roughly estimated. If a complete test is required, a large number of mathematical tests in the protocol standard (NIST 800-90B) are required to obtain the results, which is very costly.

[0086] The present invention can evaluate the randomness of each ring oscillator through a random source receiver after tape-out, and optimize the randomness of the random source generator by configuring a random source selector. The present invention can generate n bits of random sources at a time, and the throughput is n times that of the traditional throughput architecture.

[0087] Compared with the traditional architecture, the present invention can achieve the same randomness by using fewer ring oscillators, thereby reducing the area and power consumption of the oscillator.

[0088] The present invention uses a pure digital circuit. Since the standard logic gate level used by the digital circuit is small and the bottom metal layer can be used for wiring, it is difficult to locate the position of the chaos source generator from the layout, so it can effectively resist hacker cover opening attacks.

[0089] It should be noted that the present application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium; for example, a RAM memory, a magnetic or optical drive or a floppy disk and the like. In addition, some steps or functions of the present application can be implemented in hardware; for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0090] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A true random number source generating circuit, characterized in that: The true random number random source generation circuit comprises: a plurality of ring oscillators and a plurality of random source receivers, each ring oscillator being connected to a corresponding random source receiver; Each ring oscillator includes a ring selector and a plurality of inverters; the output end of the ring selector is connected to an inverter, and the inverters are connected in series in sequence; the output end of the inverter is set to be also connected to the input end of the ring selector; Each random source receiver includes a logic mixer, at least two D flip-flops, a comparator and an unstable counter; the output end of the logic mixer is respectively connected to the input end of each D flip-flop, the output end of each D flip-flop is connected to the input end of the corresponding comparator, and the output end of the comparator is connected to the input end of the unstable counter; During the chip design phase, the random source generation circuit is designed according to the above architecture. When the chip is taped out, the random source is adjusted according to the following steps when it is turned on for the first time: (1) Initialize i, wi, u to 0, and s to 2; (2) Set the selector of ring i to s; (3) Read the unstable counter value of ring i to u; (4) If the current u is greater than the previous round's u', then wi is equal to s. Otherwise, wi is not updated. Then s is updated to s' plus 2 and steps (1) to (3) are repeated until s is equal to m. (5) Record the value of wi, i equals i' plus 1, repeat steps (1) to (4) until i = n, obtain all values ​​of w0~wn, and store the value of wi in non-volatile memory; (6) After the subsequent boot, read the value of wi from the non-volatile memory and configure it to chain_i_select, the random source generator can be used normally without repeating steps (1) to (5); The true random number source generation circuit includes n+1 ring oscillators, each ring oscillator includes m+1 inverters; wherein n is a positive integer and m is an even number; In ring oscillator i, the output of the jth inverter is defined as cij, and the ring selector serves as the input end of the ring oscillator; wherein, 0≤i≤n, 0≤j≤m; when j is an even number, the output end of the jth inverter is connected to the input end of the corresponding ring selector.

2. The true random number source generating circuit according to claim 1, characterized in that: The true random number random source generation circuit includes n+1 random source receivers; the inverter output cij of the previous ring oscillator is used as the input of the corresponding random source receiver; The logic mixer selects a number of bits from cij at random and combines them into 1 bit using logic gates. The output of the logic mixer is simultaneously connected to the inputs of two D flip-flops. Each random source receiver includes two D flip-flops, namely a first D flip-flop and a second D flip-flop; the output of the first D flip-flop is the random source generator output, which can provide a random source for the random number generator. Since there are a total of n+1 random source receivers, each clock cycle can provide n+1 random source bits; the second D flip-flop is used to detect whether the random source is in an unstable state; The outputs of the two D flip-flops are connected together using a comparator, and the output result of the comparator is transmitted to an unstable counter. Whenever the output results of the two D flip-flops are different, the comparator outputs 1, and the unstable counter increases by 1. The unstable counter counts within a configured unit time, and the result of the counting is the number of times the unstable state occurs within a unit time, which is used to evaluate the performance of this chaotic source.

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