Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Abstract

In one embodiment, the method is used to produce an optoelectronic semiconductor chip (1) and comprises: A) growing an AlInGaAsP semiconductor layer sequence (3) on a growth substrate (2) along a growth direction (G), wherein the semiconductor layer sequence (3) comprises an active region (33) for generating radiation, and the active region (33) consists of a plurality of quantum well layers (61) and barrier layers (62) that alternate with one another; B) producing a structured mask layer (5, 34); C) locally mixing the quantum well layers (61) and the barrier layers (62) in at least one mixing region (51) by applying a mixing auxiliary material (55) through an opening (50) in the mask layer (5, 34) into the active region (33); and D) dividing the semiconductor layer sequence (3) into subregions (39) for the semiconductor chip (1), wherein the barrier layers (62) are formed in step A) from [(AlInGaAsP)]. x Ga 1‑x ) y In 1‑y ] z P 1‑z Growth, where x ≥ 0.5.

Description

Technical Field

[0001] A method for producing an optoelectronic semiconductor chip is specified. Furthermore, an optoelectronic semiconductor chip is specified. Summary of the invention

[0002] The object to be achieved is to specify a method for producing a relatively small optoelectronic semiconductor chip having a high efficiency.

[0003] The object is achieved in particular by a method for producing an optoelectronic semiconductor chip. Preferred developments are the subject matter of the following description.

[0004] According to at least one embodiment, the method is used to produce an optoelectronic semiconductor chip. The produced semiconductor chip is in particular a light emitting diode chip, LED chip for short. Alternatively, a laser diode chip, for example a surface emitting laser diode chip or also an edge emitting laser diode chip, can be produced. It is also possible that the optoelectronic semiconductor chip is a detector chip, in particular a photodiode.

[0005] According to at least one embodiment, the method comprises the step of growing a semiconductor layer sequence, in particular growing the semiconductor layer sequence along a growth direction on a growth substrate, in particular a GaAs substrate.

[0006] The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. Particularly preferably, the semiconductor layer sequence is based on the phosphide material system AlInGaAsP. In this case, the semiconductor layer sequence includes not only Al but also In, Ga and P. As forms an optional component of the semiconductor layer sequence. In this case, the semiconductor layer sequence can have doping materials and additional components. However, for the sake of simplicity, only the main components of the crystal lattice of the semiconductor layer sequence are described, namely Al, As, Ga, In or P, even if the main components can also be partially replaced and / or supplemented by small amounts of other materials.

[0007] As an alternative to AlInGaAsP or AlInGaP, the semiconductor layer sequence can also be based on AlInGaN or AlInGaAs. The following descriptions of AlInGaAsP or AlInGaP can apply correspondingly to AlInGaN or AlInGaAs, wherein N or As then replaces P in each case.

[0008] According to at least one embodiment, the semiconductor layer sequence comprises an active region. The active region is preferably set up for generating radiation, but can alternatively be configured for detecting radiation. The active region is in particular a multi-quantum well structure, English: multiquantum well structure or MQW for short. In the active region, quantum well layers and barrier layers are arranged alternately with each other. In particular, the active region is composed of quantum well layers and barrier layers arranged alternately.

[0009] According to at least one embodiment, the method comprises the step of generating a structured mask layer. The mask layer can be part of the semiconductor layer sequence and can thus still be present in the finished semiconductor chip. Alternatively, the mask layer is a layer manufactured specifically for the purpose, for example a soft mask, such as a photoresist layer, or a hard mask, such as an oxide layer.

[0010] According to at least one embodiment, the method comprises the step of locally mixing the quantum well layer and the barrier layer. The mixing is performed by applying a mixing aid material. The mixing aid material, in particular zinc, is introduced into the active region through an opening in the mask layer so that the mixing aid material is located in at least one mixing region. The mixing aid material causes mixing of the crystal components of the semiconductor layer sequence, in particular Al, Ga and / or In. During the mixing, a temperature significantly above room temperature and also above the subsequent normal operating temperature of the manufactured semiconductor chip is preferably applied.

[0011] Mixing can be performed uniformly over all quantum well layers. Alternatively, mixing is performed inhomogeneously. The mixing region preferably extends completely through the active region into the n-doped region. More specifically, preferably, only a single mixing region is present in each active region or on each side of the active region, but multiple mixing regions may also be present in each active region or on each side, which may be interrupted by unmixed regions along the growth direction.

[0012] According to at least one embodiment, the method comprises the step of singulating the semiconductor layer sequence into partial regions for the semiconductor chips. The singulation is performed, for example, by etching, but alternatively can also be performed by sawing or scratching and breaking.

[0013] According to at least one embodiment, the growth of [(Al x Ga 1-x ) y In 1-y ] z P 1-z Here, x≥0.5 or x≥0.6 or x≥0.7 or x≥0.8 or x≥0.9 preferably applies. It is possible for x=1 to apply, so that the barrier layer, as grown, contains no or essentially no Ga.

[0014] In at least one embodiment, the method serves to produce an optoelectronic semiconductor chip and comprises the following steps, particularly preferably in the order specified:

[0015] A) growing an AlInGaAsP semiconductor layer sequence along a growth direction on a growth substrate, wherein the semiconductor layer sequence comprises an active region for generating radiation, and the active region consists of a plurality of quantum well layers and barrier layers that alternate with each other;

[0016] B) generating a structured mask layer;

[0017] C) locally mixing the quantum well layers and the barrier layers in at least one mixing region by applying a mixing aid material through an opening in the mask layer into the active region; and

[0018] D) Segmentation of the semiconductor layer sequence into sub-regions for semiconductor chips, wherein the barrier layer is formed in step A) from [(Al x Ga 1-x ) y In 1-y ] z P 1-z Growth, where x ≥ 0.5, or preferably x ≥ 0.6.

[0019] The method described here makes it possible to reduce or eliminate non-radiative charge carrier recombination, in particular in LED chips with small side lengths at the sides of the semiconductor layer sequence, and thus to reduce or eliminate loss paths. As a result, semiconductor chips with small lateral dimensions and high efficiency can be produced.

[0020] The local diffusion of impurities and the subsequent mixing of quantum wells, also known as Quantum Well Intermixing, is a possible method for improving the low-current performance of optoelectronic semiconductor chips in particular. This applies in particular to light-emitting diode chips with small dimensions, also known as μLEDs, in particular with emission in the red spectral range. In this case, sufficiently long diffusion times should be maintained, especially in MOVPE reactors, in order to achieve a significant degree of mixing on a wafer with densely packed μLEDs.

[0021] However, the degree of mixing depends not only on the diffusion time, but also on the packing factor of the μLED. Here, the degree of mixing tends to decrease as the packing factor increases. With the method described here, it is possible to reduce the time expenditure during production, in particular the diffusion time, and / or to achieve an increased degree of mixing in the active region in the case of densely packed, in particular red-emitting μLEDs on a wafer.

[0022] The local diffusion of impurities, such as zinc, is combined with the impurity-induced mixing of quantum wells and barrier layers to improve the efficiency in μLEDs based on the AlInGaAsP material system. In conventional LED structures, the barrier layers have an aluminum content of approximately 50%, which is determined by the [(Al x Ga 1-x ) y In 1-y ] z P 1-z The reason for this relatively low aluminum content is that the starting voltage generally increases with a higher aluminum content, especially in active regions with dozens of barrier layers and quantum well layers. In the method described here, however, barrier layers are grown with a significantly higher aluminum content of at least 60%, preferably at least 80%.

[0023] In AlGaInP-based μLEDs, the number of quantum well layers and barrier layers in the active region is usually limited to a maximum of 50. Nevertheless, the current injection into the active region takes place uniformly over the quantum well layers. If a mixing step is used, the design of the layers in the active region should be carefully selected. In order to avoid recombination centers for non-radiative recombination of charge carriers at the side walls of the μLED and thus also to avoid a reduction in efficiency, a typical blocking barrier is about 65 meV for a barrier with an aluminum fraction x of 50%. For a barrier layer with an aluminum fraction x of 85%, this value is 140 meV.

[0024] This applies to the same process time. That is, due to the higher aluminum content, the same process time leads to enhanced mixing and thus to improved efficiency of the manufactured semiconductor chip. In addition, in the manufacturing process of μLEDs, mixing is generally difficult, so that mixing in such μLEDs can generally be improved with the aid of the method described here. In addition, the mixing region produced with the aid of a barrier with a high aluminum content x has a band gap with indirect transitions. That is, radiative recombination and non-radiative recombination with mixing auxiliary materials in the mixing region can be significantly reduced, thereby improving the efficiency of the light-emitting diode manufactured.

[0025] Furthermore, the method described here makes it possible, in particular in the case of μLEDs, to influence the uniformity of the current injection into the quantum well layers by means of a configuration of the barrier layer that varies in the growth direction above the active region.

[0026] According to at least one embodiment, the mask layer is formed by a contact layer, in particular a p-type contact layer, of the semiconductor layer sequence. Alternatively, a separate mask layer is used, for example in the form of a correspondingly structured permanent passivation layer or in the form of a temporary layer such as a photoresist layer.

[0027] According to at least one embodiment, the contact layer, in particular the p-type contact layer, is completely penetrated by the opening in step B). That is, the contact layer is locally completely removed.

[0028] Here, the contact layer preferably comprises Al v Ga 1-v As or consists thereof. In particular, v≤0.35 or v≤0.1 is applicable. Alternatively or additionally, v≥0 is applicable, in particular v≥0.01 or v≥0.05. The contact layer can also be a combination formed by a GaAs layer and such an AlGaAs layer.

[0029] According to at least one embodiment, the mixing in step C) is carried out completely through the active region along the growth direction. That is, the mixing region penetrates the active region completely towards the growth substrate. Alternatively, although the mixing region extends through the active region, it does not extend to or only partially extends to the growth substrate.

[0030] According to at least one embodiment, the splitting in step D) is carried out only in at least one mixing region. This particularly applies when observed in a top view of the semiconductor layer sequence, in particular in a top view of the contact layer. The side surfaces of the semiconductor layer sequence generated during splitting are thus at least partially or also completely formed by at least one mixing region.

[0031] According to at least one embodiment, the quantum well layer is grown from [(Al a Ga 1-a ) b In 1-b c P 1-c in step A). Here, in particular, 0 < a ≤ 0.3 or 0.05 ≤ a ≤ 0.2 is applicable. Via the aluminum fraction in the quantum well layer, in particular the emission wavelength of the maximum intensity of the active region can be set. It is feasible that all quantum well layers are grown nominally identically, that is, there are no differences from each other within the manufacturing tolerances regarding their material composition and regarding their thickness. Alternatively, it is feasible to grow differently structured quantum well layers, such that, for example, a thickness profile or an aluminum content profile of the quantum well layers is achieved along the growth direction in the active region. Such quantum well layers with varying characteristics are also referred to as chirped MQW.

[0032] According to at least one embodiment, 0.47 ≤ y ≤ 0.53 and 0.47 ≤ z ≤ 0.53 and / or 0.47 ≤ b ≤ 0.53 and 0.47 ≤ c ≤ 0.53 or also 0.48 ≤ y ≤ 0.52 and 0.48 ≤ z ≤ 0.52 and / or 0.48 ≤ b ≤ 0.52 and 0.48 ≤ c ≤ 0.52 apply to [(Al a Ga 1-a ) b In1-b ] c P 1-c The quantum well layer composed of [(Al x Ga 1-x ) y In 1-y ] z P 1-z Furthermore, c<0.5 and z<0.5 and / or b>0.5 and y>0.5 are preferably applicable.

[0033] The above values ​​of b, c, y and z apply in particular in the case of lattice-matched or quasi-lattice-matched growth of the semiconductor layer sequence on a GaAs growth substrate. Alternatively, the active region can be grown in a targeted tensioned manner so that values ​​of y, z and / or b, c that differ from the above regions are taken into account in a targeted manner.

[0034] In accordance with at least one embodiment, step C) comprises a thermal treatment of the semiconductor layer sequence.

[0035] For example, the elevated temperature is present for a period of at least 0.2 hours or 0.5 hours and / or at most 10 hours or 2 hours. The elevated temperature is, for example, at least 400° C. or 500° C. and / or at most 700° C. or 600° C. In particular, the temperature is between 500° C. and 540° C., inclusive.

[0036] According to at least one embodiment, the active region is located between the first semiconductor region and the second semiconductor region. The first and / or second semiconductor region may each consist of one or more sublayers. In particular, the second semiconductor region comprises a plurality of sublayers. For example, the first semiconductor region is n-doped and the second semiconductor region is p-doped. In this case, the p-type contact layer may be the sublayer of the second semiconductor region that is farthest from the active region after step A).

[0037] According to at least one embodiment, the opening extends through the contact layer in the direction of the active area into the remaining second semiconductor region by at least 50 nm or at least 100 nm. Here, these openings terminate at a certain distance from the active area. The distance from the active area is preferably at least 150 nm or 250 nm or 300 nm. The total thickness of the second semiconductor region is in particular at least 0.3 μm or 0.4 μm. Alternatively or additionally, the total thickness can be, for example, at most 10 μm or 1 μm or 0.6 μm. Here, the p-type contact layer preferably has only a relatively small thickness, for example a thickness of at most 50 nm or 20 nm and / or at least 4 nm or 8 nm.

[0038] According to at least one embodiment, the subregions of the semiconductor layer sequence for the semiconductor chip produced in step D) have, when viewed in plan view, an average side length of at most 150 μm or 100 μm or 70 μm or 30 μm or 10 μm. The semiconductor chip produced is therefore a μLED. If the subregions are not square or rectangular when viewed in plan view, the average diameter of the subregions can be used instead of the average side length.

[0039] According to at least one embodiment, after step D), at least one intermixing region extends into the active region in a direction perpendicular to the growth direction by at least 0.1 μm or 0.2 μm. Alternatively or additionally, this value is at most 1.5 μm or 1 μm or 0.5 μm or 0.3 μm. That is, only a relatively small portion of the active region is intermixed when viewed in a top view. That is, when viewed in a top view, the intermixing region is relatively small relative to the active region and, again when viewed in a top view, is in particular at most 3% or 1% or 0.2% of the area of ​​the active region.

[0040] According to at least one embodiment, at least one intermixed region extends completely through the semiconductor layer sequence in a direction parallel to the growth direction. That is, the intermixed region can extend to the growth substrate or also into the growth substrate.

[0041] According to at least one embodiment, the active region comprises at least 2 or 3 or 4 quantum well layers after step A). ​​Alternatively or additionally, the number of quantum well layers is at most 50 or 30 or 20 or 10 or 5.

[0042] According to at least one embodiment, the quantum well layers each have a thickness of at least 2 nm or 4 nm. Alternatively or additionally, the thickness of the quantum well layers each is at most 15 nm or 10 nm or 7 nm or 4 nm.

[0043] According to at least one embodiment, the barrier layer has a thickness of at least 2 nm or 3 nm or 5 nm. Alternatively or additionally, the thickness of the barrier layer is at most 353 nm or 25 nm or 15 nm or 10 nm. In particular, the thickness of the barrier layer is 7 nm, for example with a tolerance of at most 1 nm or 2 nm.

[0044] According to at least one embodiment, the active region is configured to generate an emission wavelength of maximum intensity of at least 560 nm or 590 nm or 610 nm or 620 nm. Alternatively or additionally, the emission wavelength of maximum intensity is at most 670 nm or 655 nm or 635 nm. That is, the manufactured semiconductor chip is particularly configured to generate red light.

[0045] According to at least one embodiment, the barrier layers are grown such that some or all of the barrier layers have different aluminum contents after step A) and at least before step C). The blocks of barrier layers that follow one another can nominally be grown identically. It is possible that the barrier layers have different aluminum contents in pairs.

[0046] According to at least one embodiment, after step A) and before step C), the aluminum content in question is constant in the respective barrier layer. That is, the individual barrier layers subsequently grow without a gradient in the aluminum content, as viewed in the respective barrier layer in question. Alternatively, the individual barrier layers can already be overgrown with a certain aluminum gradient in step A).

[0047] According to at least one embodiment, after step A) and until at least before step C), the minimum and maximum aluminum content of the barrier layer in the active region differ by at least a factor of 1.05, 1.1 or 1.2. Alternatively or additionally, the content differs by a factor of at most 1.7, 1.6, 1.5 or 1.4.

[0048] According to at least one embodiment, some or all of the barrier layers have different thicknesses from one another. Here, barrier layers of the same thickness may be combined in blocks or all barrier layers may have different thicknesses from one another in pairs.

[0049] According to at least one embodiment, the minimum and maximum thickness of the barrier layer in the active region differ by at least 1.2 times or 1.5 times or 2 times or 2.5 times. Alternatively or additionally, the thickness differs by at most 8 times or 6 times or 4 times or 3 times.

[0050] According to at least one embodiment, the barrier layer in the active region is arranged asymmetrically with respect to the thickness variation and / or the aluminum content variation at least after step A) and before step C). That is, in terms of the design of the barrier layer, there is no symmetry plane oriented perpendicular to the growth direction in the active region. Alternatively, the barrier layer is distributed symmetrically so that such a symmetry plane exists in the active region with respect to the barrier layer.

[0051] According to at least one embodiment, the mixing aid is zinc. In step C), the zinc is applied in particular by means of vapor deposition, for example in the form of diethylzinc, DEZn for short, or as dimethylzinc, DMZn for short. As an alternative or in addition to zinc, magnesium can be used, for example by means of bis(cyclopentadienyl)magnesium, Cp2Mg for short.

[0052] According to at least one embodiment, after step D), in step E), at least one passivation layer is applied to the cut-out intermixed regions, i.e. to the side surfaces of the semiconductor layer sequence produced during the singulation. The passivation layer consists, for example, of an oxide such as silicon dioxide or a nitride such as silicon nitride. The thickness of the passivation layer is preferably relatively small and is, for example, at least 50 nm and / or at most 250 nm.

[0053] According to at least one embodiment, the growth substrate is removed only after step C), directly after step C) or also after a further intermediate step. In particular, a replacement carrier can be placed on the semiconductor layer sequence before the growth substrate is removed. Such a replacement carrier is preferably placed before the division in step D). Division, i.e. step D), can be performed before or after the growth substrate is removed, depending on when the optional replacement carrier is placed.

[0054] Furthermore, an optoelectronic semiconductor chip is provided. The semiconductor chip is preferably produced by means of a method described in conjunction with one or more of the above embodiments. Therefore, features of the semiconductor chip are also disclosed for the method, and vice versa.

[0055] In at least one embodiment, the optoelectronic semiconductor chip comprises an AlInGaAsP semiconductor layer sequence, wherein the semiconductor layer sequence comprises an active region for generating radiation and the active region consists of a plurality of quantum well layers and barrier layers alternating with each other. The semiconductor layer sequence comprises a structured mask layer, in particular a p-type contact layer. The quantum well layers and the barrier layers are locally mixed in the active region in a mixing region, and a mixing auxiliary material, in particular zinc, is present in the mixing region. When viewed in a top view, the mixing region preferably extends around the semiconductor layer sequence in a closed trajectory. The barrier layers are composed outside the mixing region of [(Al x Ga 1-x ) y In 1-y ] z P 1-z Composition, wherein x≥0.5 or x≥0.8 or x≥0.9 or x=1.

[0056] According to at least one embodiment, the semiconductor chip is a red-emitting diode chip having an average side length of at most 50 μm. In a direction perpendicular to the growth direction of the semiconductor layer sequence, the intermixed region extends at least 0.1 μm and / or at most 0.5 μm into the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The method described here and the optoelectronic semiconductor chip described here are explained in detail below based on exemplary embodiments with reference to the drawings. The same reference numerals indicate the same elements in the various figures. However, no proportional relationships are shown here, but rather individual elements may be shown exaggeratedly for a better understanding.

[0058] The accompanying drawings show:

[0059] Figures 1 to 5 Schematic sectional illustrations showing method steps of an exemplary embodiment of a method described herein for producing an optoelectronic semiconductor chip described herein;

[0060] Figure 6 and 7 Schematic sectional illustrations showing method steps of an exemplary embodiment of a method described herein for producing an optoelectronic semiconductor chip described herein;

[0061] Figure 8 Schematic sectional illustrations showing method steps of an exemplary embodiment of a method for producing an optoelectronic semiconductor chip described here;

[0062] Fig. 9 A schematic plan view showing method steps for an exemplary embodiment of a method for producing an optoelectronic semiconductor chip described here;

[0063] Fig.10 a schematic diagram showing the profile of the aluminum content in variants of a semiconductor chip; and

[0064] Figures 11 to 14 A schematic diagram shows an aluminum profile for an exemplary embodiment of an optoelectronic semiconductor chip described here. DETAILED DESCRIPTION

[0065] exist Figures 1 to 5 An exemplary embodiment of a method for producing an optoelectronic semiconductor chip 1 is illustrated in FIG. Figure 1 , a semiconductor layer sequence 3 is epitaxially grown along a growth direction G on a growth substrate 2 .

[0066] The semiconductor layer sequence 3 includes a first semiconductor region 31, for example an n-type doped region, directly on the growth substrate 2. In the figure, the first semiconductor region 31 is only shown as a layer. In contrast, the first semiconductor region 31 can be composed of a plurality of sublayers. In particular, the first semiconductor region 31 facing the growth substrate 2 has a buffer layer (not shown) and / or an n-type contact layer (not shown).

[0067] In the direction away from the growth substrate 2, the first semiconductor region 31 is followed by an active region 33 for generating radiation. The active region 33 includes a plurality of quantum well layers 61 and barrier layers 62 arranged alternately. In particular, orange or red light is generated in the active region 33 when the manufactured semiconductor chip 1 is operated.

[0068] Along the growth direction G, the active region 33 is followed by the second semiconductor region 32. For example, the second semiconductor region 32 is p-type doped. The second semiconductor region 32 includes a p-type contact layer 34 as the uppermost layer farthest from the growth substrate 2. Therefore, there is a remaining second semiconductor region 35 between the p-type contact layer 34 and the active region 33.

[0069] The semiconductor layer sequence 3 is based on the material system AlGaInAsP. In this case, the quantum well layers are preferably composed of [(Al a Ga 1-a ) b In 1-b ] c P 1-c The barrier layer is composed of [(Al x Ga 1-x ) y In 1-y ] z P 1-z , wherein x≥0.6, in particular x≥0.8. As a result, the barrier layer has a relatively high aluminum content x. The p-type contact layer 34 is in particular composed of Al v Ga 1-v As is constituted, wherein v≤0.2. For the parameters b, c, y and z, it is particularly suitable that these parameters are around 0.5, in particular 0.51 or 0.49. For example, the active region 33 includes between 5 and 15 quantum well layers 62, including the limit values.

[0070] exist Figure 2 In the method step of , a plurality of openings 50 are produced through the p-type contact layer 34. The openings 50 extend into the remaining second semiconductor region 35. The depth of the openings 50 is, for example, between 50 nm and 200 nm, inclusive. The spacing between the openings 50 and the active region 33 is preferably at least 300 nm. The remaining second semiconductor region 35 has, for example, a thickness between 300 nm and 600 nm, inclusive. The thickness of the p-type contact layer 34 is, for example, between 5 nm and 20 nm, inclusive.

[0071] Therefore, the p-type contact layer 34 simultaneously serves as a mask layer 5 for subsequent process steps, see Figure 3 Optionally, in Figure 2 and 3In the step of forming the p-type contact layer 34, a further mask layer (not shown), such as a photoresist layer, is placed next to the opening on the p-type contact layer 34. However, such a further mask layer can also be formed in the p-type contact layer 34. Figure 3 The method step of producing the opening 50 in the p-contact layer 34 by means of the further mask layer has already been removed previously.

[0072] exist Figure 3 , a gaseous precursor 56 is introduced to the semiconductor layer sequence 3. The precursor 56 is, for example, DMZn or DEZn. Zinc is thus provided as mixing aid material 55 via the precursor 56. As an alternative to providing from the gas phase, a solid layer for the mixing aid material 55, for example a zinc layer a few nanometers thick, can also be deposited.

[0073] The mixing aid material 55 preferably diffuses into the semiconductor layer sequence 3 at an elevated temperature, for example approximately 550° C. In this case, the AlGaAs p-type contact layer 34 is impermeable to the mixing aid material 55 .

[0074] Therefore, a mixing region 51 is formed at each opening 50, in which a mixing auxiliary material 55 is present. The material of the barrier layer 62 and the material of the quantum well layer 61 are mixed in the mixing region 51. This is described in conjunction with Figures 11 to 14 Shown.

[0075] For example, the mixed region 51 extends to at least 0.2 μm or 0.5 μm below the p-type contact layer 34. The same also applies to all other embodiments.

[0076] exist Figure 4 The method step illustrated in FIG. 1 shows that the semiconductor layer sequence 3 is divided into sub-regions 39 for the semiconductor chips 1 in the region of the openings 50. This division is performed, for example, by means of etching. Thus, dividing grooves 8 are formed between the sub-regions 39. Figure 4 Unlike the illustration in , the dividing trenches 8 can also extend into the growth substrate 2. The edge lengths of the partial regions 39, viewed in plan view, are preferably small and are less than 100 μm or 50 μm.

[0077] The dividing grooves 8 are each located in the region of the intermixed region 51. The dividing grooves 8 produce side walls of the semiconductor layer sequence 3 which are formed according to Figure 4 Each is only partially formed by the intermixed region 51. In the direction toward the growth substrate 2, the intermixed region 51 begins on the side of the p-type contact layer 34 facing the active region 33. The intermixed region 51 preferably extends below the p-type contact layer 34, as shown.

[0078] In addition, Figure 43 , the application of a plurality of second electrodes 42 onto the p-type contact layer 34 and the production of the passivation layer 7 are illustrated. Mask layers for producing the second electrodes 42 and / or for producing the passivation layer 7 are not shown.

[0079] exist Figure 5 , it is also shown as an option that the growth substrate is removed from the subregion. A first electrode 41 is arranged on the first semiconductor region 31. The passivation layer 7 is largely removed from the second electrode 42. The semiconductor chip 1 is therefore preferably a light-emitting diode chip for generating red light.

[0080] Electrodes 41 and 42 are Figure 5 The electrodes 41, 42 comprising at least one metal and / or transparent conductive oxide are designed, for example, as in Figure 3 As described in paragraphs 59 to 62 of document US2012 / 0248494 A1. The disclosure of this document, in particular Figure 3 and paragraphs 59 to 62, which are incorporated herein by reference.

[0081] exist Figure 6 and 7 Another production method is shown in FIG. 1 , in which only a few method steps are illustrated. The remaining method steps can be similar to Figures 1 to 5 conduct.

[0082] according to Figure 6 , a mixing aid material 55 is applied through the opening 50 and a mixing region 51 is produced. Here, a separate mask layer 5 is used, which is not a sublayer of the semiconductor layer sequence 3. For example, the mask layer 5 is a hard mask, for example composed of silicon nitride or silicon dioxide. As a result, the mixing region 51 can extend to the mask layer 5.

[0083] exist Figure 6 It is also shown in FIG. 5 that the intermixed region 51 completely penetrates the semiconductor layer sequence 3 and thus extends to the growth substrate 2. Figures 1 to 5 In the method, a corresponding configuration of the mixing area 51 is also possible.

[0084] according to Figure 7 , resulting in dividing trenches 8 which extend at least as far as the growth substrate 2 . Therefore, the side walls of the semiconductor layer sequence 3 and thus of the dividing trenches 8 can be completely formed by the mixed region 51 in the region below the mask layer 5 .

[0085] It is possible that the mask layer 5 can also be used as a mask for producing the dividing grooves 8. That is, in a top view, the dividing grooves 8 and the openings 50 can extend congruently with each other, and Figures 1 to 5 The corresponding dividing groove 8 can also be taken into account in the method as an alternative, such as in combination with Figures 1 to 5 Illustrated.

[0086] exist Figure 8 In the method illustrated in FIG. , the p-type contact layer 34 is used again as a mask layer 5. In this case, the dividing grooves 8 and the openings 50 are also arranged congruently when viewed in a plan view. However, it is not mandatory that the mixed region 51 relevant to the dividing still extends to the growth substrate 2 after dividing. For example, the mixed region 51 only extends to the region up to the growth substrate 2 and is subsequently removed by dividing. Figures 1 to 5 as well as Figure 6 and 7 In the method, the corresponding settings are also feasible.

[0087] exist Fig. 9 Schematically a plan view of the semiconductor layer sequence 3 after singulation is shown, in particular as shown in FIG. Figure 6 and 7 in the method and in Figure 8 That is, the dividing groove 8 and the opening 50 extend congruently. A corresponding structure having a dividing groove 8 narrower than the opening 50 can also be used.

[0088] The mixing region 51 surrounds the subregion 39 of the semiconductor layer sequence 3 in a closed trajectory on all sides. The subregions 39 for the semiconductor chip 1 are each approximately square or rectangular. The side length of the subregion 39 is less than 100 μm. The spacing between adjacent subregions 39 and thus the width of the openings 50 and the dividing grooves 8 is preferably relatively small and, for example, is at most 10% or 5% or 2% of the average side length of the subregion 39. In particular, the width of the openings 50 and / or the dividing grooves 8 is at most 5 μm or 3 μm or 1 μm and / or at least 0.5 μm or 1 μm. That is, the subregions 39 are arranged in a densely packed manner on the growth substrate 2, so that relatively little space is left for the diffusion of the mixing auxiliary material 55.

[0089] exist Fig.10 A variant 10 of a semiconductor chip is shown in FIG. Here, the ratio of the aluminum portion to the sum of the aluminum portion and the gallium portion is plotted in percentage terms with respect to the growth direction G. The left-hand part of the figure relates to the unmixed region 52 of the active region 33, while the right-hand part of the figure relates to the mixed region 51 of the active region 33. Figures 11 to 14 The same diagram is also used in .

[0090] The barrier layer 62 has a relatively low aluminum content. As a result, after mixing, a relatively flat variation curve of the aluminum content appears in the mixing region 51, resulting in a relatively small increase in the band gap compared to the quantum well layer 61. As a result, the recombination losses of the carriers at the side walls of the sub-region 39 and thus the semiconductor chip 1 can only be reduced relatively poorly. In conventional LEDs, such edge effects are almost meaningless, because the edge lines are only of secondary significance relative to the total area of ​​the active area. In the case of the μLED described here, due to the small side length of the sub-region 39, the corresponding effects at the side walls are potentially significant loss channels.

[0091] exist Fig.11 The variation of the aluminum content of an exemplary embodiment of a semiconductor chip 1 is shown in FIG. Fig.10 In the mixed region 51 , this results in a significantly higher band gap between the quantum well layer 61 in the unmixed region 52 and the mixed structure in the mixed region 51 .

[0092] according to Fig.11 , all quantum well layers 51 and barrier layers 62 grow identically, so that the growth direction G remains unchanged in the unmixed region 52. Figures 12 to 14 The barrier layers 62 each have at least one gradient in thickness and / or material composition.

[0093] Therefore, according to Fig.12 , the barrier layer 62 is configured to have a decreasing aluminum content along the growth direction G. Fig.13 , the aluminum content of the barrier layer 62 remains unchanged along the growth direction G, but the thickness of the barrier layer 62 decreases. Fig.14 yes Fig.12 and 13 The combination of the configurations in , results in a decrease in the aluminum content and a decrease in the thickness of the barrier layer along the growth direction G.

[0094] exist Figures 11 to 14 In the figures, only five quantum well layers 61 are shown in each case for the sake of simplifying the illustration. More or fewer quantum well layers than shown can be present in the active region 33 .

[0095] Figures 12 to 14 The barrier layers 62 are arranged asymmetrically in the active region 33, so that the active region 33 does not have a symmetry plane about which the barrier layers 62 are constructed mirror-symmetrically. Alternatively, a symmetrical order of the barrier layers 62 is also possible, so that, for example, similar to Fig.12 , the aluminum content of the barrier layer 62 first increases along the growth direction G and then decreases to the same extent. Fig.13 and 14 implementation method.

[0096] and Figures 12 to 14 It is also possible that the growth direction G does not extend from left to right, but from right to left. In addition, asymmetrical combinations of increasing and decreasing aluminum content and increasing and decreasing layer thicknesses and their corresponding combinations are possible. That is, when viewed along the growth direction G, there can be an asymmetrically distributed barrier layer 62 in which the aluminum content first increases and then decreases, or in which the aluminum content first decreases and then increases. The corresponding content applies with respect to thickness, see Fig.13 , or for combinations of thickness variation and aluminum content variation, see Fig.14 .

[0097] Unless otherwise stated, the components shown in the drawings preferably follow each other directly in the order given. Layers that are not in contact in the drawings are preferably spaced apart from each other. If the lines are drawn parallel to each other, the corresponding surfaces are preferably also oriented parallel to each other. Likewise, the relative positions of the components shown in the drawings are reproduced correctly in relation to each other, unless otherwise stated.

[0098] The invention described here is not limited to the description based on the exemplary embodiments. Rather, the invention includes any new features and any combination of features, which in particular includes any combination of features in the exemplary embodiments, even if the feature or the combination itself is not explicitly described in the exemplary embodiments.

[0099] This application claims the priority of German patent application 102019126506.1, the disclosure content of which is incorporated herein by reference.

[0100] Reference numerals list

[0101] 1 Optoelectronic semiconductor chips

[0102] 2 Growth substrate

[0103] 3 Semiconductor layer sequence

[0104] 31 First semiconductor region (n-type region)

[0105] 32 Second semiconductor region (p-type region)

[0106] 33 Active area

[0107] 34 p-type contact layer, especially Al v Ga 1-v As35 The rest of the second semiconductor region

[0108] 39 Subregion of the semiconductor layer sequence

[0109] 41 First electrode

[0110] 42 Second electrode

[0111] 5 Mask layer

[0112] 50 Open

[0113] 51 Mixing region of semiconductor layer sequence

[0114] 52 Unmixed regions of the semiconductor layer sequence

[0115] 55 Mixing auxiliary materials

[0116] 56 Precursor for mixing auxiliary materials 61 Quantum well layers, especially [(Al a Ga 1-a ) b In 1-b ] c P 1-c 62 Barrier layers, especially [(Al x Ga 1-x ) y In 1-y ] z P 1-z 7 Passivation layer

[0117] 8 split slots

[0118] 10 Variations of semiconductor chips

[0119] G Growth direction of the semiconductor layer sequence

Claims

1. A method for producing an optoelectronic semiconductor chip (1), comprising the following steps in the given order: A) growing an AlInGaAsP semiconductor layer sequence (3) along a growth direction (G) on a growth substrate (2), wherein the semiconductor layer sequence (3) comprises an active region (33) for generating radiation, and the active region (33) consists of a plurality of quantum well layers (61) and barrier layers (62) alternating with one another; B) generating a structured mask layer; C) locally mixing the quantum well layer (61) and the barrier layer (62) in at least one mixing region (51) by applying a mixing aid material (55) through an opening (50) in the mask layer into the active region (33); and D) dividing the semiconductor layer sequence (3) into sub-regions (39) for the semiconductor chips (1), The barrier layer (62) is composed of [(Al x Ga 1-x ) y In 1-y ] z P 1-z growth, wherein x≥0.5, and the quantum well layer (61) is formed in step A) by [(Al a Ga 1-a ) b In 1-b ] c P 1-c Growth, where 0<a≤0.2, where 0.47≤y≤0.53 and 0.47≤z≤0.53, and 0.47≤b≤0.53 and 0.47≤c≤0.

53.

2. The method according to claim 1, Where x ≥ 0.

6.

3. The method according to claim 1 or 2, in - the mask layer is formed by a p-type contact layer (34) of the semiconductor layer sequence (3), - the p-type contact layer (34) is completely penetrated by the opening (50) in step B), - The p-type contact layer (34) comprises Al v Ga 1-v As, where v≤0.35, - the mixing in step C) is carried out completely through the active area (33) along the growth direction (G), The segmentation in step D) is performed only in the at least one mixing region (51).

4. The method according to claim 3, wherein the active region (33) is located between the first semiconductor region (31) and the second semiconductor region (32), and the p-type contact layer (34) is the sublayer of the second semiconductor region (32) which is farthest from the active region (33) after step A), The opening (50) extends through the p-type contact layer (34) in the direction toward the active region (33) by at least 50 nm into the remaining second semiconductor region (35) and ends at a distance of at least 200 nm from the active region (33).

5. The method according to claim 1 or 2, The semiconductor chip (1) manufactured is a light emitting diode chip, In step D), the partial regions (39) for the semiconductor chip (1) each have an average edge length of at most 100 μm.

6. The method according to claim 1 or 2, Therein, after step D), the at least one intermixed region (51) extends into the active region (33) in a direction perpendicular to the growth direction (G) by at least 0.1 μm and at most 0.5 μm.

7. The method according to claim 1 or 2, The at least one intermixing region (51) extends completely through the semiconductor layer sequence (3) parallel to the growth direction (G).

8. The method according to claim 1 or 2, in - after step A), there are between 3 and 30 said quantum well layers (61), inclusive; - the quantum well layers (61) each have a thickness between 2 nm and 15 nm, inclusive; - the barrier layers (62) each have a thickness between 3 nm and 25 nm, inclusive; and The emission wavelength of the active region (33) with maximum intensity is between 590 nm and 655 nm, inclusive.

9. The method according to claim 1 or 2, wherein after step A) and before step C), at least some of the barrier layers (62) have different aluminum contents, wherein after step A) and before step C), within the respective barrier layer (62), the aluminum content is constant, and The minimum aluminum content and the maximum aluminum content of the barrier layer (62) in the active region (33) differ by at least 1.1 times and at most 1.7 times.

10. The method according to claim 1 or 2, wherein at least some of the barrier layers (62) have different thicknesses, The minimum thickness and the maximum thickness of the barrier layer (62) in the active region (33) differ by at least 1.5 times and at most 6 times.

11. The method according to claim 1 or 2, wherein the quantum well layer (61) is the same after step A) and before step C), The barrier layer (62) in the active region (33) is arranged asymmetrically with respect to the thickness variation and / or the aluminum content variation at least after step A) and before step C).

12. The method according to claim 1 or 2, The mixing auxiliary material (55) is zinc.

13. The method according to claim 12, In this case, the mixing aid ( 55 ) is applied in step C) by means of vapor deposition in the form of diethylzinc and / or dimethylzinc.

14. The method according to claim 1 or 2, Therein, after step D), in step E), a passivation layer ( 7 ) is applied to the cut-out mixed region ( 51 ).

15. The method according to claim 1 or 2, Therein, the growth substrate (2) is removed after step C).

16. An optoelectronic semiconductor chip (1) comprising an AlInGaAsP semiconductor layer sequence (3), wherein The semiconductor layer sequence (3) comprises an active region (33) for generating radiation, and the active region (33) consists of a plurality of quantum well layers (61) and barrier layers (62) which alternate with one another, The semiconductor layer sequence (3) comprises a structured mask layer, - the quantum well layer (61) and the barrier layer (62) are locally mixed into the active region (33) in the mixing region (51), and a mixing auxiliary material (55) is present in the mixing region (51), and - The barrier layer (62) is composed of [(Al x Ga 1-x ) y In 1-y ] z P 1-z wherein x≥0.5, and the quantum well layer (61) outside the mixed region (51) is composed of [(Al a Ga 1-a ) b In 1-b ] c P 1-c Composition, where 0<a≤0.2, where 0.47≤y≤0.53 and 0.47≤z≤0.53, and 0.47≤b≤0.53 and 0.47≤c≤0.

53.

17. The optoelectronic semiconductor chip (1) as claimed in claim 16, The optoelectronic semiconductor chip is a light-emitting diode chip having an emission wavelength of maximum intensity between 560 nm and 670 nm inclusive, having an average edge length of at most 50 μm, The intermixed region (51) extends at least 0.1 μm and at most 0.5 μm into the active region (33) in a direction perpendicular to the growth direction (G) of the semiconductor layer sequence (3).

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