Multi-bit registers, chips, and computing devices

Abstract

The present disclosure relates to a multi-bit register, a chip, and a computing device. A multi-bit register includes: a plurality of register cells, each for storing one bit of data, and the plurality of register cells are connected in parallel; and a clock buffer for providing a clock signal to the plurality of register cells, wherein the plurality of register cells are arranged in a register cell array, and the clock buffer is arranged in the middle of the register cell array.

Description

Technical Field

[0001] The present disclosure relates to semiconductor technology, and more particularly to a multi-bit register, and a chip and a computing device including the multi-bit register. Background Art

[0002] Registers are widely used in semiconductor technology for storing, shifting, and frequency dividing digital signals. Registers have data inputs, clock inputs, and a data output. Data can be written to a register via the data inputs and read from it via the data outputs. The clock input receives the clock signal that triggers the register. Common registers include D flip-flops and latches. D flip-flops are edge-triggered, while latches are level-triggered.

[0003] In some applications, a group of registers is needed to store multi-bit data. In other words, multiple registers need to operate synchronously. To achieve this, the data inputs and outputs of multiple registers can be connected in parallel to form a group of registers. A clock buffer can then be used to provide a clock signal to the group of registers, thereby forming a multi-bit register.

[0004] Figure 1 FIG2 shows a schematic diagram of a multi-bit register 100 according to the prior art. The multi-bit register 100 is used to store multi-bit data.

[0005] like Figure 1 As shown, the multi-bit register 100 includes a register group 110 and a clock buffer 120 .

[0006] Register bank 110 includes N register units 110-1, 110-2, ..., 110-N connected in parallel, configured to store N-bit multi-bit data. Each register unit 110-1, 110-2, ..., 110-N is configured to store one bit of data. For example, register unit 110-1 is configured to store the first bit of the multi-bit data, register unit 110-2 is configured to store the second bit of the multi-bit data, and so on. The data input terminals and data output terminals of the N register units 110-1, 110-2, ..., 110-N are connected in parallel, thereby synchronously storing each bit of the multi-bit data.

[0007] Clock buffer 120 is used to provide a clock signal to the N register units 110-1, 110-2, ..., 110-N of register group 110. Clock buffer 120 receives a clock signal from a clock signal terminal CK, buffers the clock signal, and then inputs the clock signal to the clock input terminals of the N register units 110-1, 110-2, ..., 110-N, thereby triggering register units 110-1, 110-2, ..., 110-N to latch or read data.

[0008] like Figure 1 As shown, in the prior art, N register units 110-1, 110-2, ..., 110-N are usually arranged in a row, and the clock buffer 120 is usually arranged at the periphery of the array formed by the N register units 110-1, 110-2, ..., 110-N. Figure 1 As shown, the clock buffer 120 is arranged at the uppermost or lowermost portion of the N register units 110 - 1 , 110 - 2 , . . . , 110 -N forming a column.

[0009] The speed of a multi-bit register is a very important performance indicator. It is necessary to further improve the speed of the multi-bit register 100 of the prior art. Therefore, there is a demand for new technologies. Summary of the Invention

[0010] One of the objects of the present disclosure is to provide an improved multi-bit register.

[0011] According to one aspect of the present disclosure, a multi-bit register is provided, comprising: a plurality of register units, each register unit being used to store one bit of data, and the plurality of register units being connected in parallel with each other; a clock buffer being used to provide a clock signal to the plurality of register units, wherein the plurality of register units are arranged into a register unit array, and the clock buffer is arranged at a middle position of the register unit array.

[0012] According to another aspect of the present disclosure, a chip is provided, which includes the multi-bit register as described above.

[0013] According to yet another aspect of the present disclosure, a computing device is provided, which includes the chip as described above.

[0014] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0017] Figure 1 FIG. 1 is a schematic diagram showing a multi-bit register according to the prior art.

[0018] Figure 2 A schematic diagram of a multi-bit register according to an exemplary embodiment of the present disclosure is shown.

[0019] Figure 3 A schematic diagram of a multi-bit register according to another exemplary embodiment of the present disclosure is shown.

[0020] Figure 4 A schematic diagram of a multi-bit register according to yet another exemplary embodiment of the present disclosure is shown.

[0021] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items, so once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0022] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not represent actual positions, sizes, and ranges, etc. Therefore, the present disclosure is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. DETAILED DESCRIPTION

[0023] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0024] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. In other words, the structures and methods herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that these are merely exemplary of the disclosure that may be implemented, and are not exhaustive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0025] Technologies, methods and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods and equipment should be considered part of the authorization specification.

[0026] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0027] Figure 2 FIG2 shows a schematic diagram of a multi-bit register 200 according to an exemplary embodiment of the present disclosure. The multi-bit register 200 is used to store multi-bit data.

[0028] like Figure 2 As shown, the multi-bit register 200 includes N register units 210 - 1 , 210 - 2 , . . . , 210 -N and a clock buffer 220 .

[0029] The N register units 210-1, 210-2, ..., 210-N are used to store N-bit multi-bit data. Each register unit 210-1, 210-2, ..., 210-N is used to store one bit of data. The data input terminals and data output terminals of the N register units 210-1, 210-2, ..., 210-N are connected in parallel, thereby synchronously storing each bit of the multi-bit data.

[0030] The clock buffer 220 is used to provide clock signals to the N register units 210-1, 210-2, ..., 210-N. The clock buffer 220 receives a clock signal from a clock signal terminal CK and buffers the clock signal before inputting it to the clock input terminals of the N register units 210-1, 210-2, ..., 210-N.

[0031] like Figure 2 As shown, the clock buffer 220 is arranged in the middle of the array of N register units 210-1, 210-2, ..., 210-N. That is, the clock buffer 220 is preceded by M register units 210-1, 210-2, ..., 210-M and followed by NM register units 210-M+1, ..., 210-N.

[0032] By arranging the clock buffer 220 in the middle position of the array of N register units 210-1, 210-2, ..., 210-N, the distance of the connection from the clock buffer 220 to the clock input terminal of the register unit 210-1, 210-2, ..., 210-N can be shortened, thereby reducing the parasitic resistance and parasitic capacitance of the metal connection, thereby increasing the speed of the multi-bit register 200.

[0033] exist Figure 2In the illustrated embodiment, N register cells 210-1, 210-2, ..., 210-N and a clock buffer 220 are arranged in a column. In a preferred embodiment, the clock buffer 220 is arranged substantially in the center of the column. That is, the clock buffer 220 is arranged after the M register cells 210-1, 210-2, ..., 210-M, where M is substantially equal to N / 2. This can further optimize the distance between the wiring from the clock buffer 220 and the clock input terminals of the register cells 210-1, 210-2, ..., 210-N, thereby reducing the parasitic resistance and parasitic capacitance of the metal wiring and increasing the speed of the multi-bit register 200.

[0034] It should be noted that "substantially equal" and similar expressions herein mean that the two are roughly equal within a certain error, but not necessarily strictly and precisely equal. For example, "substantially equal" means that the two are roughly equal within an error of 10%. Preferably, the two are roughly equal within an error of 5%. In some contexts, the error may be about 20%. Those skilled in the art will understand that this is in line with technical principles and engineering practices. For example, as described above, M is substantially equal to N / 2, which means that M is roughly equal to N / 2 within a certain error. For example, in an embodiment where N is an odd number, M may be equal to (N-1) / 2 or (N+1) / 2.

[0035] Figure 3 FIG2 shows a schematic diagram of a multi-bit register 300 according to another exemplary embodiment of the present disclosure. The multi-bit register 300 is used to store multi-bit data.

[0036] like Figure 3 As shown, the multi-bit register 300 includes a plurality of register units 310-1, 310-2, ... and a clock buffer 320. Each register unit is used to store one bit of data, and the data input terminals and data output terminals of the plurality of register units 310-1, 310-2, ... are (for clarity, not shown in FIG. Figure 3 (not shown) are connected in parallel to each other, thereby synchronously storing each bit of multi-bit data.

[0037] Figure 3 Schematically, 14 register units 310-1, 310-2, ..., 310-14 are shown. However, those skilled in the art will appreciate that the number of register units in the multi-bit register 300 is not limited thereto. The number of register units in the multi-bit register 300 may be determined as needed, and the number of register units in the multi-bit register 300 may be determined as needed. Figure 3 These register units are arranged in a schematically illustrated manner.

[0038] The clock buffer 320 is used to provide a clock signal to the plurality of register units 310-1, 310-2, .... A clock signal line is connected between the clock buffer 320 and the plurality of register units 310-1, 310-2, .... The clock buffer 320 receives a clock signal from a clock signal terminal CK (for clarity, the clock signal terminal CK is not shown in FIG. 1 ). Figure 3 (not shown) receives the clock signal, and buffers the clock signal and inputs it to the clock input end of each register unit respectively.

[0039] like Figure 3 As shown, the clock buffer 320 is arranged in the middle of the array of the plurality of register units 310-1, 310-2, .... Specifically, in Figure 3 In the illustrated embodiment, a plurality of register units 310 - 1 , 310 - 2 , . . . and a clock buffer 320 are arranged in a matrix structure, and the clock buffer 320 is arranged in the middle of the matrix structure.

[0040] exist Figure 3 In the preferred embodiment shown, the clock buffer 320 and the plurality of register units 310-1, 310-2, ... are arranged in a matrix structure. Figure 2 Compared with the embodiment shown, this can further shorten the distance of the connection from the clock buffer 320 to the clock input terminals of the register units 310-1, 310-2, ..., thereby reducing the parasitic resistance and parasitic capacitance of the metal connection, thereby increasing the speed of the multi-bit register 300.

[0041] In a preferred embodiment, the clock buffer 320 is arranged substantially in the center of the matrix structure. Figure 3 As schematically shown, the clock buffer 320 and the 14 register units 310 - 1 , 310 - 2 , . . . , 310 - 14 are arranged in a matrix of 5 rows and 3 columns, and the clock buffer 320 is arranged at the 3rd row and the 2nd column of the matrix.

[0042] However, those skilled in the art will appreciate that the number and arrangement of register cells in a multi-bit register are not limited thereto. In some embodiments, the clock buffer and the plurality of register cells may not be arranged in a neat matrix, but rather in a matrix-like structure similar to a matrix. For example, the clock buffer and the plurality of register cells may be arranged in a matrix shape, wherein at least one row may have fewer columns than other rows, or at least one column may have fewer rows than other columns.

[0043] The number of rows and columns of the matrix structure formed by the clock buffer and the plurality of register units can be determined based on the configuration of the register units, the configuration of the chip including the multi-bit registers, and the requirements of the semiconductor process. In a preferred embodiment, the ratio of the number of rows to the number of columns of the matrix structure can be set so that the connection distances from the clock buffer to the clock input terminals of the corresponding register units in the top row, bottom row, leftmost column, and rightmost column of the matrix structure (e.g., the register units closest to the clock buffer in the corresponding row or column) are substantially equal. In a preferred embodiment, the ratio of the number of rows to the number of columns of the matrix structure can be greater than or equal to 0.5 and less than or equal to 3.

[0044] On the other hand, in some embodiments, the clock buffer may not be arranged in the exact center of the matrix structure, but may be arranged approximately in the center of the matrix structure within a certain tolerance. For example, the matrix structure may have an even number of rows (or an even number of columns), and the clock buffer may be arranged in one of the two center rows (or one of the two center columns) of the matrix or matrix structure. Furthermore, the matrix structure may not be axisymmetric or centrosymmetric, and the clock buffer may be arranged approximately in the center of the matrix structure, so that the connection distances from the clock buffer to the clock input terminals of the register units at the outermost edges of the matrix structure are substantially equal.

[0045] exist Figure 3 In the illustrated embodiment, there is only one clock signal path between clock buffer 320 and each register unit 310-1, 310-2, .... In other words, the clock signal is provided from clock buffer 320 to each register unit 310-1, 310-2, ... via only one path. In other embodiments, more optimal routing schemes may be employed to further improve the speed of multi-bit registers.

[0046] Figure 4 FIG2 shows a schematic diagram of a multi-bit register 400 according to another exemplary embodiment of the present disclosure. The multi-bit register 400 is used to store multi-bit data.

[0047] like Figure 4 As shown, the multi-bit register 400 includes a plurality of register units 410-1, 410-2, ... and a clock buffer 420. Each register unit is used to store one bit of data, and the data input terminals and data output terminals of the plurality of register units 410-1, 410-2, ... are (for clarity, not shown in FIG. Figure 4 (not shown) are connected in parallel to each other, thereby synchronously storing each bit of multi-bit data.

[0048] Figure 4Schematically, 14 register units 410-1, 410-2, ..., 410-14 are shown. However, those skilled in the art will appreciate that the number of register units in the multi-bit register 400 is not limited thereto. Similarly, the number of register units in the multi-bit register 400 can be determined as needed, and the number of register units in the multi-bit register 400 can be determined as needed. Figure 4 These register units are arranged in a schematically illustrated manner.

[0049] The clock buffer 420 is used to provide a clock signal to the plurality of register units 410-1, 410-2, .... A clock signal line is connected between the clock buffer and the plurality of register units 410-1, 410-2, .... The clock buffer 420 receives a clock signal from a clock signal terminal CK (for clarity, the clock signal terminal CK is not shown in FIG. 1 ). Figure 4 (not shown) receives the clock signal, and buffers the clock signal before inputting it to the clock input terminal of each register unit.

[0050] exist Figure 4 In the preferred embodiment shown, the clock buffer 420 and the plurality of register units 410-1, 410-2, ... are arranged such that two or more clock signal paths exist between the clock buffer 420 and at least some of the register units (410-1, 410-4, 410-7, ...). In other words, the clock signal is provided from the clock buffer 420 to at least some of the register units (410-1, 410-4, 410-7, ...) via two or more paths.

[0051] In a further preferred embodiment, Figure 4 As shown, the clock buffer 420 and the plurality of register units 410-1, 410-2, ... are arranged so that any two adjacent ones of the clock buffer 420 and the plurality of register units 410-1, 410-2, ... are directly connected by a clock signal line. Figure 4 As shown, “adjacent” means adjacent in the row direction or column direction of the matrix structure formed by the clock buffer 420 and the plurality of register units 410 - 1 , 410 - 2 , . . . .

[0052] exist Figure 4 In the preferred embodiment shown, two or more clock signal paths are formed between the clock buffer 420 and at least a portion of the register units 410-1, 410-4, 410-7, ... Figure 3 Compared with the embodiment shown, this can further reduce the parasitic resistance of the metal connection between the clock buffer and the register unit. In particular, for semiconductor processes where parasitic resistance plays a dominant role relative to parasitic capacitance, this wiring method can further improve the speed of multi-bit registers.

[0053] It should be noted that Figure 3 and Figure 4 The register units are numbered for convenience only. It should be understood by those skilled in the art that Figure 3 and Figure 4 The numbers of the register units (310-1, 310-2, ...; 410-1, 410-2, ...) are not intended to limit the configuration, number or order of the register units in any way, nor are they intended to specify that a register unit is used to store a certain bit of multi-bit data.

[0054] The specific configuration and implementation of the register unit and clock buffer used in the present disclosure can be determined based on the chip including the multi-bit register and the requirements of the semiconductor process. For example, the register unit can be a D flip-flop or a latch, can have a positive output or a negative output, and can be a static register or a dynamic register.

[0055] The arithmetic circuit according to the present disclosure may be implemented in various appropriate ways, such as software, hardware, or a combination of software and hardware. In one implementation, a chip may include the multi-bit register described above, and the chip may also be included in a computing device.

[0056] The terms "front," "back," "top," "bottom," "over," "under," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0057] As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be bound by any expressed or implied theory presented in the preceding technical field, background, summary, or detailed description.

[0058] As used herein, the word "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The word "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0059] Additionally, the foregoing description may have referred to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature, whether electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element / node / feature can be mechanically, electrically, logically, or otherwise connected to another element / node / feature, either directly or indirectly, to allow interaction, even though the two features may not be directly connected. That is, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections utilizing one or more intermediate elements.

[0060] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0061] It should also be understood that when the term "include / comprises" is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0062] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0063] Those skilled in the art will appreciate that the boundaries between the above-mentioned operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of specific operations, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and replacements are also possible. Therefore, this specification and the accompanying drawings should be considered illustrative, not restrictive.

[0064] Although some specific embodiments of the present disclosure have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multi-bit register, characterized in that: The multi-bit register comprises: a plurality of register units, each register unit being configured to store one bit of data, and the plurality of register units being connected in parallel to one another; A clock buffer is used to provide a clock signal to the plurality of register units, wherein The plurality of register units and the clock buffer are arranged in a matrix structure, the matrix structure includes a plurality of rows and a plurality of columns, and the clock buffer is arranged in a middle position of the matrix structure, and In the matrix structure, a clock signal line is connected between the clock buffer and the multiple register units, so that a clock signal is provided from the clock buffer to each of the multiple register units through multiple corresponding paths, and the multiple corresponding paths are connected between the clock buffer and each of the multiple register units, and the multiple corresponding paths include paths passing through other register units in the multiple register units.

2. The multi-bit register according to claim 1, wherein: The clock buffer is arranged substantially in the center of the matrix structure.

3. The multi-bit register according to claim 1, wherein: In the matrix structure, a clock signal line is directly connected between any one of the multiple register units adjacent to the clock buffer and the clock buffer, and a clock signal line is directly connected between any two adjacent register units among the multiple register units.

4. The multi-bit register according to any one of claims 1 to 3, wherein: The ratio of the number of rows to the number of columns of the matrix structure is greater than or equal to 0.5 and less than or equal to 3.

5. A chip, characterized in that: The chip comprises a multi-bit register according to any one of claims 1-4.

6. A computing device, characterized in that: The computing device comprises the chip according to claim 5.

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