A method, device, electronic device and storage medium for matching a circuit schematic diagram

Abstract

The present application discloses a matching method for a circuit schematic diagram. The matching method includes: determining an IC chip, and querying an alternative CBB circuit corresponding to the IC chip in a standard CBB model library; obtaining the circuit schematic diagram of the circuit where the IC chip is located, and determining the pin connection information of the IC chip according to the circuit schematic diagram; determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram; and determining the difference information between the alternative CBB circuit and the target circuit according to the pin connection information. The present application can determine the differences between the actually designed circuit and the common circuit module, facilitating circuit designers to perform correctness verification on the circuit. The present application also discloses a matching device for a circuit schematic diagram, an electronic device, and a storage medium, which have the above beneficial effects.

Description

Technical Field

[0001] The present application relates to the technical field of circuit design, and particularly relates to a method and device for matching circuit schematics, an electronic device, and a storage medium. Background Art

[0002] A CBB (Common Building Block) circuit refers to a circuit module shared among different design platforms and projects. Currently, in the process of designing a circuit schematic, the schematic that has been designed is usually directly referred to, and the required CBB module is copied from it. However, since the application functions of the same chip vary for each product form, there will be multiple versions of the CBB circuit corresponding to each chip. Directly using the copied and already designed CBB circuit without actual project verification cannot guarantee the correctness of the circuit schematic.

[0003] Therefore, how to determine the differences between the actually designed circuit and the shared circuit module to facilitate circuit designers to verify the correctness of the circuit is a technical problem that those skilled in the art need to solve currently. Summary of the Invention

[0004] The purpose of the present application is to provide a method and device for matching circuit schematics, an electronic device, and a storage medium, which can determine the differences between the actually designed circuit and the shared circuit module to facilitate circuit designers to verify the correctness of the circuit.

[0005] To solve the above technical problem, the present application provides a method for matching circuit schematics, and the matching method includes:

[0006] Determine an IC chip, and query for an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;

[0007] Obtain the circuit schematic of the circuit where the IC chip is located, and determine the pin connection information of the IC chip according to the circuit schematic;

[0008] Determine a target circuit corresponding to the alternative CBB circuit in the circuit schematic according to the circuit connection relationship in the circuit schematic;

[0009] Determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information.

[0010] Optionally, determining the pin connection information of the IC chip according to the circuit schematic includes:

[0011] Generate a first tree diagram by traversing the connection status of the pins in the IC chip; wherein, the first tree diagram includes network names, device names, device reference designators, material codes of the devices, and package names;

[0012] Generate a second tree diagram by traversing the connection status of the pins in other circuit modules; wherein, the other circuit modules include circuit modules in the circuit schematic diagram that are not connected to the IC chip; the second tree diagram includes network names, device names, device reference designators, material codes of the devices, and package names;

[0013] Obtain a total tree diagram with the IC chip as the root node based on all the first tree diagrams and all the second tree diagrams, and use the total tree diagram as the pin connection information of the IC chip.

[0014] Optionally, the generating a total tree diagram with the IC chip as the root node based on all the first tree diagrams and all the second tree diagrams includes:

[0015] Add status markers to the topological endpoints in the first tree diagram and the second tree diagram; wherein, the status markers include network names, device names, and pin numbers;

[0016] Merge the topological endpoints with the same status markers in the first tree diagram and the second tree diagram into the same node to connect the first tree diagram and the second tree diagram, and obtain a total tree diagram with the IC chip as the root node.

[0017] Optionally, determining the difference information between the alternative CBB circuit and the target circuit based on the pin connection information includes:

[0018] Determine the target tree diagram corresponding to the alternative CBB circuit in the total tree diagram;

[0019] Compare the networks and devices in the alternative CBB circuit with the target tree diagram to obtain the difference information.

[0020] Optionally, comparing the networks and devices in the alternative CBB circuit with the target tree diagram to obtain the difference information includes:

[0021] Determine the current level elements in the alternative CBB circuit;

[0022] Judge whether the current level elements are the same as the same level elements in the target tree diagram;

[0023] If they are not the same, generate the difference information corresponding to the current level elements;

[0024] If they are the same, set the next level as the new current level element, and perform the operation of determining whether the current level element is the same as the element at the same level in the target tree diagram.

[0025] Optionally, if the current level element is a network, the determination of whether the current level element is the same as the element at the same level in the target tree diagram includes:

[0026] Determine whether the current level element and the element at the same level in the target tree diagram are assigned a non-default network name; wherein, the network name includes a default network name and a non-default network name, and the default network name is the network name automatically assigned to the element by the system;

[0027] If the current level element and / or the element at the same level in the target tree diagram is assigned a non-default network name, then determine whether the network name of the current level element is the same as the network name of the element at the same level in the target tree diagram; if they are the same, mark the status of the current level element as successfully matched; if they are not the same, mark the status of the current level element as failed to match;

[0028] If neither the current level element nor the element at the same level in the target tree diagram is assigned a non-default network name, mark the status of the current level element as pending;

[0029] If the status of all elements under the element marked as pending is marked as successfully matched, modify the status of the element marked as pending to successfully matched;

[0030] If the status of any element under the element marked as pending is marked as failed to match, modify the status of the element marked as pending to failed to match;

[0031] Add the element whose status is marked as failed to match to the information difference list; wherein, the difference information includes the information in the information difference list.

[0032] Optionally, if the current level element is a device, the determination of whether the current level element is the same as the element at the same level in the target tree diagram includes:

[0033] Determine whether the material code of the current level element is the same as the material code of the element at the same level in the target tree diagram;

[0034] If the material codes are the same, determine that the current level element is the same as the element at the same level in the target tree diagram;

[0035] If the material codes are not the same, determine whether the package name of the current level element is the same as the package name of the element at the same level in the target tree diagram;

[0036] If the package names are the same, add the current hierarchical element to the device attribute difference list;

[0037] If the package names are different, determine whether the pin parameters of the current hierarchical element are the same as those of the same hierarchical element in the target tree diagram; among them, the pin parameters include the number of pins and the pin numbers;

[0038] If the pin parameters are the same, add the current hierarchical element to the device attribute difference list;

[0039] If the pin parameters are different, add the current hierarchical element and other elements under the current hierarchical element to the information difference list; among them, the difference information includes the information in the device attribute difference list and / or the information difference list.

[0040] Optionally, after determining the difference information between the alternative CBB circuit and the target circuit according to the pin connection information, it further includes:

[0041] Determine the matching degree between the alternative CBB circuit and the circuit schematic diagram according to the difference information, and the elements with differences between the alternative CBB circuit and the circuit schematic diagram;

[0042] Display the alternative CBB circuit on the circuit schematic diagram editing interface, display the matching degree on the circuit schematic diagram editing interface, and increase the display brightness of the elements with differences.

[0043] The present application also provides a matching device for a circuit schematic diagram, and the correction device includes:

[0044] A CBB circuit query module, configured to determine an IC chip and query an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;

[0045] A connection information determination module, configured to obtain the circuit schematic diagram of the circuit where the IC chip is located, and determine the pin connection information of the IC chip according to the circuit schematic diagram;

[0046] A circuit determination module, configured to determine a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram;

[0047] A difference determination module, configured to determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information.

[0048] The present application also provides a storage medium, on which a computer program is stored, and when the computer program is executed, the steps performed by the above-mentioned matching method for a circuit schematic diagram are implemented.

[0049] The present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and when the processor calls the computer program in the memory, the steps executed by the above circuit schematic matching method are implemented.

[0050] The present invention provides a method for matching circuit schematics, including: determining an IC chip, and querying an alternative CBB circuit corresponding to the IC chip in a standard CBB model library; obtaining the circuit schematic of the circuit where the IC chip is located, and determining the pin connection information of the IC chip according to the circuit schematic; determining the target circuit corresponding to the alternative CBB circuit in the circuit schematic according to the circuit connection relationship in the circuit schematic; and determining the difference information between the alternative CBB circuit and the target circuit according to the pin connection information.

[0051] The present application queries the alternative CBB circuit corresponding to the IC chip in the CBB model library. The alternative CBB circuit is a CBB circuit pre-stored in the standard CBB model library for comparison with the CBB circuit in the circuit schematic of the circuit where the IC chip is located. The present application determines the pin connection information of the IC chip according to the circuit schematic of the circuit where the IC chip is located. If the alternative CBB circuit is applied to the circuit schematic, there is a certain circuit connection relationship between the alternative CBB circuit and the IC chip. The present application determines the target circuit corresponding to the alternative CBB circuit in the circuit schematic according to the actual circuit connection relationship in the circuit schematic, and then determines the difference information between the selected CBB circuit and the target circuit based on the pin connection information. The difference information is used for the difference between the circuit actually used in the circuit diagram and the CBB circuit pre-stored in the standard CBB model library. According to this difference information, circuit designers can verify the correctness of the circuit schematic. The present application can determine the difference between the actually designed circuit and the common circuit module, which is convenient for circuit designers to verify the correctness of the circuit. The present application also provides a circuit schematic matching device, an electronic device and a storage medium, which have the above beneficial effects and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 It is a flowchart of a method for matching circuit schematics provided by an embodiment of the present application;

[0054] Figure 2Flowchart of a method for determining pin connection information provided by an embodiment of the present application;

[0055] Figure 3 Tree diagram of a pin connection relationship provided by an embodiment of the present application;

[0056] Figure 4 Schematic diagram of the automatic matching principle of the CBB circuit in practical applications provided by an embodiment of the present application;

[0057] Figure 5 Schematic diagram of the structure of a matching device for a circuit schematic diagram provided by an embodiment of the present application. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0059] Please refer to the following Figure 1 , Figure 1 Flowchart of a method for matching a circuit schematic diagram provided by an embodiment of the present application.

[0060] The specific steps may include:

[0061] S101: Determine the IC chip and query the alternative CBB circuits corresponding to the IC chip in the standard CBB model library;

[0062] Among them, this embodiment is used to compare the differences between the circuits used in the circuit schematic diagram and the CBB circuits in the standard CBB model library. The IC (integrated circuit) chip determined in this step is the chip in the above circuit schematic diagram. Multiple pre-stored CBB circuits and the corresponding relationships between the IC chip and each pre-stored CBB circuit may be stored in the standard CBB model library. This step may query the alternative CBB circuits corresponding to the IC chip in the standard CBB model library based on the above corresponding relationships.

[0063] As a feasible implementation, each IC chip can have its corresponding material code, which is the unique identifier for each device in the circuit. After determining the code of the IC chip, the corresponding alternative CBB circuit can be queried in the standard CBB model library. The standard CBB model library stores multiple pre-stored CBB circuits, as well as the corresponding relationship between the material code of each CBB circuit and the material code of the IC chip. In this embodiment, the corresponding alternative CBB circuit for the IC chip can be determined according to this corresponding relationship. The alternative CBB circuit refers to the CBB circuit required by the circuit where the IC chip is located.

[0064] Before this step, there may also be an operation of constructing the standard CBB model library. After designing the CBB circuit, the circuit schematic diagram of the CBB circuit, the material code of the CBB circuit, and the material code of the IC chip included in the circuit schematic diagram where the CBB circuit is located can be stored in the standard CBB model library.

[0065] S102: Obtain the circuit schematic diagram of the circuit where the IC chip is located, and determine the pin connection information of the IC chip according to the circuit schematic diagram;

[0066] Among them, before this step, there may be an operation for the user to design the circuit schematic diagram of the circuit where the IC chip is located. As a feasible implementation, during the process of designing the circuit schematic diagram, the selected IC chip can be determined first, and the material code (i.e., the CODE code) of the IC chip can be obtained. Based on the material code of the IC chip, it is matched with the standard CBB model library to query the corresponding alternative CBB circuits for the IC chip, and these alternative CBB circuits are copied to the schematic diagram in the form of modules. Then the designer manually checks whether these CBB circuits are directly usable or can be modified based on one of them, so as to quickly help the designer to match the required CBB circuit. Due to the large number of CBB circuit archive libraries, in this embodiment, the alternative CBB circuits are matched by automatically querying the material codes, and subsequently each CBB archiving personnel archives based on the actual application design of the module. Through the above method, the reuse accuracy of the CBB circuit can be increased and the borrowing rate can be improved. The above method solves the problem of information intercommunication between different departments, and can make all CBB circuits become publicly available resources. The requirements for CBB circuit archiving in this embodiment can be changed to be based on actual application, with relatively high usability.

[0067] Specifically, the process of generating the circuit schematic diagram includes: displaying the alternative CBB circuit on the circuit schematic diagram editing interface; if an editing instruction is received, performing a corresponding editing operation on the alternative CBB circuit according to the editing instruction; if a displacement instruction is received, moving the alternative CBB circuit to the corresponding position according to the displacement instruction. The IC chip may include multiple pins, and in this embodiment, the pin connection information of all pins can be obtained. The pins can be connected to networks and devices, and the pin connection information is the information used to describe the pin connection status.

[0068] S103: Determine the target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram;

[0069] S104: Determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information.

[0070] Among them, there is a designed target circuit in the circuit schematic diagram. In this embodiment, the alternative CBB circuit pre-stored in the standard CBB model library is queried through the material code of the IC chip. If there is difference information between the target circuit and the alternative CBB circuit corresponding to the same circuit module, it may indicate that there is a design difference between the actually designed circuit and the pre-stored CBB circuit. By obtaining the difference information, it can help circuit designers perform correctness verification on the circuit schematic diagram, and can also reflect the difference points between the target circuit in the newly designed circuit schematic diagram and the CBB circuit in the standard CBB model library, which can be used as a reference for others to use the CBB circuit in the standard CBB model library later.

[0071] Specifically, in this embodiment, the pin connection information of the IC chip can be used to match with the alternative CBB circuit, and the difference information between the alternative CBB circuit and the target circuit in the circuit schematic diagram can be determined according to the matching result. If the difference information is empty, it means that the target circuit in the circuit schematic diagram is designed the same as the alternative CBB circuit in the standard CBB model library. If the difference information is not empty, it means that the target circuit is different from the alternative CBB circuit in the standard CBB model library. At this time, there may be a design error in the circuit schematic diagram, and the circuit schematic diagram can be corrected according to the difference information.

[0072] In this embodiment, an alternative CBB circuit corresponding to the IC chip is queried in the CBB model library. The alternative CBB circuit is a CBB circuit pre-stored in the standard CBB model library for comparison with the CBB circuit in the circuit schematic diagram of the circuit where the IC chip is located. This embodiment determines the pin connection information of the IC chip according to the circuit schematic diagram of the circuit where the IC chip is located. When the alternative CBB circuit is applied to the circuit schematic diagram, there is a certain circuit connection relationship between the alternative CBB circuit and the IC chip. This embodiment determines the target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the actual circuit connection relationship in the circuit schematic diagram, and then determines the difference information between the selected CBB circuit and the target circuit based on the pin connection information. The difference information is used for the difference between the circuit actually used in the circuit diagram and the CBB circuit pre-stored in the standard CBB model library. According to this difference information, circuit designers can verify the correctness of the circuit schematic diagram. This embodiment can determine the difference between the actually designed circuit and the common circuit module, which is convenient for circuit designers to verify the correctness of the circuit.

[0073] As a further introduction to Figure 1 the corresponding embodiment, this embodiment can determine the matching degree between the alternative CBB circuit and the circuit schematic diagram, as well as the elements with differences between the alternative CBB circuit and the circuit schematic diagram; display the alternative CBB circuit on the circuit schematic diagram editing interface, display the matching degree on the circuit schematic diagram editing interface, and increase the display brightness of the elements with differences. The method for calculating the matching degree between the alternative CBB circuit and the circuit schematic diagram can be: taking the ratio of the number of matched elements to the total number of matched elements as the matching degree; where the number of matched elements is the number of networks in the alternative CBB circuit that match the circuit schematic diagram, and the total number of matched elements is the sum of the number of devices and the number of networks in the CBB circuit. This embodiment can automatically import the CBB into the schematic diagram software and highlight the difference points, quickly compare the difference points between the design module and the CBB circuit, so as to quickly confirm the difference points and focus on checking the differences. Through the above method, it is possible to compare the correctness of the design module based on the CBB standard and ensure the quality of the circuit schematic diagram.

[0074] Please refer to Figure 2 , Figure 2 which is a flowchart of a method for determining pin connection information provided by an embodiment of the present application. This embodiment is a further introduction to Figure 1 S102 in the corresponding embodiment. This embodiment can be combined with the Figure 1 corresponding embodiment to obtain a further implementation manner. This embodiment may include the following steps:

[0075] S201: Generate a first tree diagram by traversing the connection status of pins in the IC chip;

[0076] Among them, the first tree diagram includes network name, device name, device reference designator, material code of the device, and package name;

[0077] S202: Generate a second tree diagram by traversing the connection status of pins in other circuit modules;

[0078] Among them, the other circuit modules include the circuit modules in the circuit schematic diagram that are not connected to the IC chip; the second tree diagram includes network name, device name, device reference designator, material code of the device, and package name;

[0079] S203: Obtain a total tree diagram with the IC chip as the root node based on all the first tree diagrams and all the second tree diagrams, and use the total tree diagram as the pin connection information of the IC chip.

[0080] In this embodiment, the circuit module circuit drawing pages (such as pages 1 to 5) designed in the circuit schematic diagram can be selected, and the alternative CBB circuit can be obtained by matching the specified IC chip in the designed CBB circuit. Specifically, this embodiment can cyclically traverse the pin topology to obtain the connection status of the pins in the IC chip in the actual circuit. The other circuit modules are the circuit modules in the circuit schematic diagram except the IC chip. This embodiment can cyclically traverse the pin topology to obtain the connection status of the pins in the other circuit modules. Please refer to Figure 3 , Figure 3 This is a tree diagram of the pin connection relationship provided by the embodiment of the present application. This embodiment can generate a first tree diagram and a second tree diagram according to the connection status of the pins.

[0081] Furthermore, the extraction and topology expansion method for other circuit modules that are not directly connected to the IC chip and circuit modules on other pages are as follows: Since other modules are not directly connected to the IC module, the external connection network of a certain module is obtained. This network satisfies that one end is floating or is a ground network. The extracted external network is marked, and the marking format is: network and network name label (i.e., non-default network name), device name, extracted device reference designator, material code, package name value. These marks are extracted into a list and sorted, and this list is compared with the network mark list of the above IC module. The network mark list of the IC module includes the network and network name label (i.e., non-default network name), device name, extracted device reference designator, material code, package name value of the IC chip. During the comparison process, the first successfully matched mark is found, and this is used as the network benchmark extracted for this module. The topology expansion starts with this network.

[0082] The idea of ​​generating a tree diagram is: start traversing from the pin, and determine whether there is a branch at the location each time you search forward one step; when there is a branch, use each branch as the sub-root value of the tree diagram, and then loop each branch separately to extract the pin connection information. The pin connection information includes: network and network name label (that is, non-default network name), device name, extracted device position number, material code, package name value. These pin connection information can be stored in the sub-root of the parent root. The same method can be used to extract all IC pins and corresponding topologies into the tree diagram. In the process of extracting pin connection information, if there is no network name label, extract the network UID (that is, the default network name).

[0083] The external connection of the IC chip pin is a topology, which includes networks, resistors, capacitors, inductors or other functional chips and network connections extending outward from these devices, etc., until the topological end point of the first tree diagram or the second tree diagram. The topological end point includes the following two situations: the first is that the topological expansion extends to the pin of the IC chip, which is the end point of the topology; the other is that the end point is a network, one end of which is suspended or grounded, which is the topological end point. This end point is also the end point connected to other modules. Therefore, a status mark should be added to each such end point, with the format of: network name + device name (ie DEVICE) + pin number, and all the status marks of external connections are extracted into a list.

[0084] As for Figure 2 Further introduction to the corresponding embodiment, the operation of generating a total tree diagram in S203 may include the following process: adding status marks to the topological endpoints in the first tree diagram and the second tree diagram; wherein the status marks include network names, device names and pin numbers; merging the topological endpoints with the same status marks in the first tree diagram and the second tree diagram into the same node, so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram with the IC chip as the root node.

[0085] Then, the expanded module topology is placed at the matching mark point in the IC module as the topological extension of the IC module. Similarly, all the scattered modules in the circuit are expanded and hung under the IC module. Usually, all modules exist and can be expanded and hung on a certain external network of the IC module. If the external network of the module does not match the external network of the IC module, it is compared with the external network of the expanded module. If the match is successful, it is hung under the module. If all the expanded modules fail to match, the module is first put into a temporary list and waits for other modules to be generated before matching.

[0086] If you will Figure 1 andFigure 2 When combined with the corresponding embodiments, the process of determining the difference information in S103 includes: determining the target tree diagram corresponding to the alternative CBB circuit in the total tree diagram; comparing the networks and devices in the alternative CBB circuit with the target tree diagram to obtain the difference information.

[0087] Specifically, comparing the networks and devices in the alternative CBB circuit with the target tree diagram to obtain the difference information includes:

[0088] Step A1: Determine the current-level elements in the alternative CBB circuit;

[0089] Step A2: Determine whether the current-level elements are the same as the same-level elements in the target tree diagram; if so, proceed to Step A4; if not, proceed to Step A3;

[0090] Step A3: Generate the difference information corresponding to the current-level elements;

[0091] Step A4: Set the next level as the new current-level elements and enter the operation process corresponding to Step A2.

[0092] In the above embodiments, the process of comparing the tree diagrams level by level is described. After the elements at the current level are the same, it is determined whether the elements at the next level are the same; if it is detected that the elements at the current level are different, the corresponding difference information can be directly generated. In this embodiment, all alternative CBB circuits containing qualified ones in the extracted standard CBB model library are matched. The specific process is as follows: Loop through all qualified CBB circuits, then loop through the IC pins in each CBB, select any IC pin in the CBB to traverse and match with the tree diagram generated in the design module circuit. When the match is successful, record the number of layers the CBB module has advanced and the number of layers advanced in the tree diagram. These two must match, that is, the overall comparison information is at the same position in the two modules. For example, if the layer where a certain position in the CBB circuit is located is 3, then all branches of the third layer are also traversed in the module's tree diagram. When comparing at a certain layer, the algorithm is as follows: If the current layers are the same, match the information with this layer. If the match is successful, continue to the next layer and record the progress mark as a successful match. If the match is unsuccessful, then mark this position as a failed match, and the progress direction is to retreat upward and compare with other information in this layer and mark. If the match cannot be determined, this situation occurs when comparing networks. Since the network does not have a network name label and the network UID is randomly generated, the network UIDs may be different. At this time, the status of this position needs to be recorded as pending, and continue to match the next layer. If the match is successful, the pending mark at the above position is changed to a successful match, otherwise it is changed to a failed match until all information has been compared.

[0093] Since the elements to be compared in the circuit schematic diagram include networks and devices, the elements to be compared each time are divided into two types: networks and devices. If the element to be compared is a network and the element being compared is also a network, then it is necessary to distinguish whether there is a network name, that is, the label of the network. If there is no label of the network name, then this step is marked as pending, and continue to compare downward to determine the correctness of the network path. If both have the label of the network name, or one has the label of the network name and the other does not, then when the matching values are different, this path terminates, and all the information on the path after this position is extracted into the corresponding array, and this array is added to the information difference list.

[0094] Specifically, if the current-level element is a network, the process of determining whether the current-level element is the same as the element at the same level in the target tree diagram includes the following: determining whether the current-level element and the element at the same level in the target tree diagram are assigned non-default network names; where the network name includes a default network name and a non-default network name, and the default network name is the network name automatically assigned by the system to the element; if the current-level element and / or the element at the same level in the target tree diagram is assigned a non-default network name, then determine whether the network name of the current-level element is the same as the network name of the element at the same level in the target tree diagram; if they are the same, then mark the status of the current-level element as successfully matched; if they are different, then mark the status of the current-level element as failed to match; if neither the current-level element nor the element at the same level in the target tree diagram is assigned a non-default network name, then mark the status of the current-level element as pending; if the status of all elements under the element marked as pending is marked as successfully matched, then modify the status of the element marked as pending to successfully matched; if the status of any element under the element marked as pending is marked as failed to match, then modify the status of the element marked as pending to failed to match; add the element whose status is marked as failed to match to the information difference list; where the difference information includes the information in the information difference list.

[0095] If the comparison element and the compared element are devices, then the material codes of the two devices are compared to see if they are the same. If they are the same, continue to traverse the connectivity of the pins on the device and the corresponding pins of the compared device. If the material codes are different and the package names are the same, record the device information in the array separately as a list of different device attribute information. If the package names are different, then continue to match the number of pins and pin numbers to see if they are the same. If they are different, put the device information at that position of the two modules and all the elements on the subsequent path into the array as a list of differences in devices and subsequent information. If the pins are the same, then put the device into the list of different device attribute information, continue to match the information behind the corresponding pins of the device to see if they are the same. Finally, all the differences between the two modules will be found and put into the corresponding array. According to the above method, all the matching CBB circuits and the designed module circuits are finally checked and recorded for matching.

[0096] Specifically, if the current level element is a device, the determination of whether the current level element is the same as the same level element in the target tree diagram includes the following process: determining whether the material code of the current level element is the same as the material code of the same level element in the target tree diagram; if the material codes are the same, determining that the current level element is the same as the same level element in the target tree diagram; if the material codes are different, determining whether the package name of the current level element is the same as the package name of the same level element in the target tree diagram; if the package names are the same, adding the current level element to the device attribute difference list; if the package names are different, determining whether the pin parameters of the current level element are the same as the pin parameters of the same level element in the target tree diagram; wherein the pin parameters include the number of pins and the pin sequence number; if the pin parameters are the same, adding the current level element to the device attribute difference list; if the pin parameters are different, adding the current level element and other elements under the current level element to the information difference list; wherein the difference information includes information in the device attribute difference list and / or the information difference list. Through the above method, the circuit schematic can be quickly matched with the alternative CBB circuit in the standard CBB model library, so as to find the problems existing in the circuit schematic design and ensure the correctness of the circuit schematic design.

[0097] The following is an example of an actual application to illustrate the process described in the above embodiment. Figure 4 , Figure 4 A schematic diagram of the automatic matching principle of a CBB circuit in a practical application provided in an embodiment of the present application.

[0098] During the process of designing the circuit schematic diagram, the CBB circuit corresponding to the IC chip can be queried. Since there can be multiple circuit modules in the circuit schematic diagram, after detecting that the user has selected a circuit module, it can be determined whether the selected circuit module is an IC device. If the selected CBB circuit is an IC device, the standard CBB model library is queried according to the IC information (i.e., the material code). After extracting all the CBB circuits that meet the requirements from the standard CBB model library, all the CBB circuits extracted from the standard CBB model library can be opened in the circuit schematic diagram, so as to select the CBB circuits that meet the design requirements for use and delete the redundant CBB circuits.

[0099] During the circuit schematic diagram matching process, the information of the design modules in the circuit schematic diagram can be extracted first, and the CBB circuits in the standard CBB model library are queried based on the material code of the IC chip. The CBB circuits extracted from the standard CBB model library are copied to the circuit schematic diagram, the relevant information of each CBB circuit is extracted respectively, and the relevant information is matched with the modules in the circuit schematic diagram to obtain the difference points and matching degrees between the circuit schematic diagram and the corresponding CBB circuits in the standard CBB model library, and then the difference comparison result is output.

[0100] Please refer to Figure 5 , Figure 5 which is the structural schematic diagram of a circuit schematic diagram matching device provided by an embodiment of the present application;

[0101] The device may include:

[0102] A CBB circuit query module 100, configured to determine an IC chip and query alternative CBB circuits corresponding to the IC chip in the standard CBB model library;

[0103] A connection information determination module 200, configured to obtain the circuit schematic diagram of the circuit where the IC chip is located and determine the pin connection information of the IC chip according to the circuit schematic diagram;

[0104] A circuit determination module 300, configured to determine the target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram;

[0105] A difference determination module 400, configured to determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information.

[0106] In this embodiment, the alternative CBB circuit corresponding to the IC chip is queried in the CBB model library. The alternative CBB circuit is the CBB circuit pre-stored in the standard CBB model library for comparison with the CBB circuit in the circuit schematic diagram of the circuit where the IC chip is located. This embodiment determines the pin connection information of the IC chip according to the circuit schematic diagram of the circuit where the IC chip is located. When the alternative CBB circuit is applied to the circuit schematic diagram, there is a certain circuit connection relationship between the alternative CBB circuit and the IC chip. This embodiment determines the target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the actual circuit connection relationship in the circuit schematic diagram, and then determines the difference information between the selected CBB circuit and the target circuit based on the pin connection information. The difference information is used for the difference between the circuit actually used in the circuit diagram and the CBB circuit pre-stored in the standard CBB model library. According to this difference information, circuit designers can verify the correctness of the circuit schematic diagram. This embodiment can determine the difference between the actually designed circuit and the common circuit module, which is convenient for circuit designers to verify the correctness of the circuit.

[0107] Further, the connection information determination module 200 includes:

[0108] The first tree diagram generation unit is used to generate a first tree diagram by traversing the connection conditions of the pins in the IC chip; wherein, the first tree diagram includes network name, device name, device reference number, material code of the device, and package name;

[0109] The second tree diagram generation unit is used to generate a second tree diagram by traversing the connection conditions of the pins in other circuit modules; wherein, the other circuit modules include the circuit modules in the circuit schematic diagram that are not connected to the IC chip; the second tree diagram includes network name, device name, device reference number, material code of the device, and package name;

[0110] The total tree diagram generation unit is used to obtain a total tree diagram with the IC chip as the root node according to all the first tree diagrams and all the second tree diagrams, and use the total tree diagram as the pin connection information of the IC chip.

[0111] Further, the total tree diagram generation unit is used to add status marks to the topological endpoints in the first tree diagram and the second tree diagram; wherein, the status marks include network name, device name, and pin number; and is also used to merge the topological endpoints with the same status marks in the first tree diagram and the second tree diagram into the same node to connect the first tree diagram and the second tree diagram to obtain a total tree diagram with the IC chip as the root node.

[0112] Further, the difference determination module 400 includes:

[0113] A target tree diagram determination unit for determining a target tree diagram corresponding to a target circuit in the total tree diagram;

[0114] A difference comparison unit for comparing the networks and devices in the alternative CBB circuit with the target tree diagram to obtain difference information.

[0115] Further, the difference comparison unit includes:

[0116] A level determination subunit for determining the current level elements in the alternative CBB circuit;

[0117] A judgment subunit for judging whether the current level elements are the same as the elements at the same level in the target tree diagram; if not, generating difference information corresponding to the current level elements; if so, setting the next level as the new current level elements and starting the workflow corresponding to the level determination subunit.

[0118] Further, if the current level element is a network, the judgment subunit is used to judge whether the current level element and the element at the same level in the target tree diagram are assigned non-default network names; wherein, the network name includes a default network name and a non-default network name, and the default network name is the network name automatically assigned by the system to the element; for if the current level element and / or the element at the same level in the target tree diagram are assigned non-default network names, judging whether the network name of the current level element is the same as the network name of the element at the same level in the target tree diagram; if so, marking the status of the current level element as successfully matched; if not, marking the status of the current level element as failed to match; for if neither the current level element nor the element at the same level in the target tree diagram is assigned a non-default network name, marking the status of the current level element as pending; for if the status of all elements under the element marked as pending is marked as successfully matched, modifying the status of the element marked as pending to successfully matched; for if the status of any element under the element marked as pending is marked as failed to match, modifying the status of the element marked as pending to failed to match; for adding the element whose status is marked as failed to match to the information difference list; wherein, the difference information includes the information in the information difference list.

[0119] Further, if the current level element is a device, the judgment subunit is used to judge whether the material code of the current level element is the same as the material code of the same level element in the target tree diagram; if the material codes are the same, then determine that the current level element is the same as the same level element in the target tree diagram; if the material codes are different, then judge whether the package name of the current level element is the same as the package name of the same level element in the target tree diagram; if the package names are the same, then add the current level element to the device attribute difference list; if the package names are different, then judge whether the pin parameters of the current level element are the same as the pin parameters of the same level element in the target tree diagram; wherein the pin parameters include the number of pins and the pin sequence number; if the pin parameters are the same, then add the current level element to the device attribute difference list; if the pin parameters are different, then add the current level element and other elements under the current level element to the information difference list; wherein the difference information includes information in the device attribute difference list and / or the information difference list.

[0120] Furthermore, it also includes:

[0121] a difference information processing module, configured to determine, after determining difference information between the candidate CBB circuit and a corresponding module in the circuit schematic according to the pin connection information, a matching degree between the candidate CBB circuit and the circuit schematic, and elements that differ between the candidate CBB circuit and the circuit schematic according to the difference information;

[0122] The difference marking module is used to display the candidate CBB circuit on the circuit schematic editing interface, display the matching degree in the circuit schematic editing interface and increase the display brightness of the elements with differences.

[0123] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, which will not be repeated here.

[0124] The present application also provides a storage medium on which a computer program is stored, and when the computer program is executed, the steps provided in the above embodiment can be implemented. The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0125] The present application also provides an electronic device, which may include a memory and a processor. A computer program is stored in the memory. When the processor calls the computer program in the memory, the steps provided in the above embodiments can be implemented. Of course, the electronic device may further include various network interfaces, power supplies and other components.

[0126] The various embodiments in the specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part. It should be noted that for those of ordinary skill in the art in the technical field of the present application, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0127] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

Claims

1. A method for matching a circuit schematic diagram, characterized in that, Including: Determine the IC chip, and query the alternative CBB circuit corresponding to the IC chip in the standard CBB model library; Obtain the circuit schematic diagram of the circuit where the IC chip is located, and determine the pin connection information of the IC chip according to the circuit schematic diagram; Determine the target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram; Determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information; Among them, determining the pin connection information of the IC chip according to the circuit schematic diagram includes: Generate a first tree diagram by traversing the connection status of the pins in the IC chip; wherein, the first tree diagram includes network name, device name, device reference number, material code of the device, and package name; Generate a second tree diagram by traversing the connection status of the pins in other circuit modules; wherein, the other circuit modules include the circuit modules in the circuit schematic diagram that are not connected to the IC chip; the second tree diagram includes network name, device name, device reference number, material code of the device, and package name; Obtain a total tree diagram with the IC chip as the root node according to all the first tree diagrams and all the second tree diagrams, and use the total tree diagram as the pin connection information of the IC chip.

2. The matching method of the circuit schematic diagram according to claim 1, characterized in that Generating a total tree diagram with the IC chip as the root node according to all the first tree diagrams and all the second tree diagrams includes: Add status marks to the topological endpoints in the first tree diagram and the second tree diagram; wherein, the status marks include network name, device name, and pin number; Merge the topological endpoints with the same status marks in the first tree diagram and the second tree diagram into the same node, so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram with the IC chip as the root node.

3. The matching method of the circuit schematic diagram according to claim 1, characterized in that Determining the difference information between the alternative CBB circuit and the target circuit according to the pin connection information includes: Determine the target tree diagram corresponding to the target circuit in the total tree diagram; Compare the networks and devices in the alternative CBB circuit with the target tree diagram to obtain difference information.

4. The matching method of the circuit schematic diagram according to claim 3, characterized in that Comparing the networks and devices in the alternative CBB circuit with the target tree diagram to obtain difference information includes: Determine the current level element in the alternative CBB circuit; Judge whether the current level element is the same as the same level element in the target tree diagram; If they are not the same, generate difference information corresponding to the current level element; If they are the same, set the next level as the new current level element, and perform the operation of judging whether the current level element is the same as the same level element in the target tree diagram.

5. The matching method of the circuit schematic diagram according to claim 4, characterized in that, If the current level element is a network, judging whether the current level element is the same as the same level element in the target tree diagram includes: Judge whether the current level element and the same level element in the target tree diagram are assigned non-default network names; wherein, the network name includes default network name and non-default network name, and the default network name is the network name automatically assigned by the system to the element; If the current - level element and / or the same - level elements in the target tree diagram are assigned non - default network names, determine whether the network name of the current - level element is the same as the network name of the same - level elements in the target tree diagram; if they are the same, mark the status of the current - level element as successfully matched; if they are different, mark the status of the current - level element as failed to match. If neither the current - level element nor the same - level elements in the target tree diagram are assigned non - default network names, mark the status of the current - level element as pending. If the status of all elements under the element marked as pending is marked as successfully matched, modify the status of the element marked as pending to successfully matched. If the status of any element under the element marked as pending is marked as failed to match, modify the status of the element marked as pending to failed to match. Add the element whose status is marked as failed to match to the information difference list; among them, the difference information includes the information in the information difference list.

6. The matching method of the circuit schematic diagram according to claim 4, characterized in that If the current - level element is a device, the determination of whether the current - level element is the same as the same - level element in the target tree diagram includes: Determine whether the material code of the current - level element is the same as the material code of the same - level element in the target tree diagram. If the material codes are the same, determine that the current - level element is the same as the same - level element in the target tree diagram. If the material codes are different, determine whether the package name of the current - level element is the same as the package name of the same - level element in the target tree diagram. If the package names are the same, add the current - level element to the device attribute difference list. If the package names are different, determine whether the pin parameters of the current - level element are the same as the pin parameters of the same - level element in the target tree diagram; among them, the pin parameters include the number of pins and the pin numbers. If the pin parameters are the same, add the current - level element to the device attribute difference list. If the pin parameters are different, add the current - level element and other elements under the current - level element to the information difference list; among them, the difference information includes the information in the device attribute difference list and / or the information difference list.

7. The matching method of the circuit schematic diagram according to any one of claims 1 to 6, characterized in that After determining the difference information between the alternative CBB circuit and the target circuit according to the pin connection information, it further includes: Determine the matching degree between the alternative CBB circuit and the circuit schematic diagram according to the difference information, and the elements with differences between the alternative CBB circuit and the circuit schematic diagram. Display the alternative CBB circuit on the circuit schematic diagram editing interface, display the matching degree on the circuit schematic diagram editing interface, and increase the display brightness of the elements with differences.

8. A matching device for a circuit schematic diagram, characterized in that, It includes: A CBB circuit query module, which is used to determine the IC chip and query the alternative CBB circuit corresponding to the IC chip in the standard CBB model library. A connection information determination module, which is used to obtain the circuit schematic diagram of the circuit where the IC chip is located and determine the pin connection information of the IC chip according to the circuit schematic diagram. A circuit determination module, configured to determine a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relationship in the circuit schematic diagram; A difference determination module, configured to determine the difference information between the alternative CBB circuit and the target circuit according to the pin connection information; Wherein, the connection information determination module includes: A first tree diagram generation unit, configured to generate a first tree diagram by traversing the connection conditions of the pins in the IC chip; wherein, the first tree diagram includes a network name, a device name, a device part number, a material code of the device, and a package name; A second tree diagram generation unit, configured to generate a second tree diagram by traversing the connection conditions of the pins in other circuit modules; wherein, the other circuit modules include circuit modules in the circuit schematic diagram that are not connected to the IC chip; the second tree diagram includes a network name, a device name, a device part number, a material code of the device, and a package name; A total tree diagram generation unit, configured to obtain a total tree diagram with the IC chip as the root node according to all the first tree diagrams and all the second tree diagrams, and use the total tree diagram as the pin connection information of the IC chip.

9. An electronic device, characterized in that, It includes a memory and a processor, and a computer program is stored in the memory. When the processor calls the computer program in the memory, the steps of the circuit schematic diagram matching method according to any one of claims 1 to 7 are implemented.

10. A storage medium, characterized in that, Computer-executable instructions are stored in the storage medium. When the computer-executable instructions are loaded and executed by a processor, the steps of the circuit schematic diagram matching method according to any one of claims 1 to 7 above are implemented.

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