A competitive neural network chip and its use method

Abstract

The present invention discloses a competitive neural network chip. By using a reconfigurable field effect transistor and a discharge capacitor to form a synapse, the weight value of the neural network is burned through the programmable gate of the reconfigurable field effect transistor; when an input signal is input, a control voltage is input through the control gate of the reconfigurable field effect transistor, which can generate a charging current to charge the discharge capacitor, complete the multiplication and accumulation operation, and finally output the maximum output voltage of each neuron through the side inhibition unit array, so as to realize a winner-takes-all competitive neural network chip. With the flexibility of the reconfigurable field effect transistor, the competitive neural network chip can have the advantages of small area, low power consumption, high speed, high precision, etc. The present invention also provides a method of use, which also has the above-mentioned beneficial effects.

Description

Technical Field

[0001] The present invention relates to the technical field of neural network chips, and in particular to a competitive neural network chip and a method for using the competitive neural network chip. Background Art

[0002] With the rapid development of Internet of Things technology, massive amounts of data need to be transmitted and processed in real time. In the traditional von Neumann architecture, storage and computing are separated, and a large amount of data needs to be repeatedly moved between the central processing unit and the memory, resulting in huge energy consumption and low throughput. In response to the bottleneck of the storage wall, an architecture that integrates storage and computing, storage and computing integration, was proposed. Data is calculated while being stored, which can greatly improve the energy efficiency of the system. Competitive neural networks, as one of the most successful algorithms currently used for pattern recognition in the field of artificial intelligence, have been widely deployed in edge devices. In the face of the growing system throughput requirements, it is of great significance to develop a highly energy-efficient competitive neural network circuit architecture based on storage and computing integration.

[0003] Reconfigurable field effect transistors (RFETs) control the polarity of carriers in the channel through different voltage configurations to achieve N-type and P-type devices. With the flexibility of RFETs, more complex circuits can be realized with fewer devices based on traditional electronic information processing methods. Therefore, how to provide a winner-takes-all competitive neural network chip based on reconfigurable field effect transistors is an urgent problem that technicians in this field need to solve. Summary of the invention

[0004] The purpose of the present invention is to provide a competitive neural network chip, and to provide a winner-takes-all competitive neural network chip based on a reconfigurable field effect transistor; another purpose of the present invention is to provide a method for using a competitive neural network chip, and to provide a winner-takes-all competitive neural network based on a reconfigurable field effect transistor.

[0005] In order to solve the above technical problems, the present invention provides a competitive neural network chip, comprising a neuron array, a weight decoder, an input decoder and a lateral inhibition unit array;

[0006] The neuron array includes neurons arranged in a transverse direction, and the neurons include synapses arranged in a longitudinal direction; the synapses include reconfigurable field effect transistors and discharge capacitors electrically connected to each other; the programmable gates of the reconfigurable field effect transistors in the neurons are electrically connected to the weight decoder, and the control gates of the reconfigurable field effect transistors in each row of synapses in the neuron array are electrically connected to the input decoder; the output ends of the neurons in the neuron array are connected to the lateral inhibition unit array;

[0007] The weight decoder is used to burn the weight value into the reconfigurable field effect transistor through the programmable gate, and the input decoder is used to input the control voltage into the reconfigurable field effect transistor through the control gate to generate a charging current to charge the discharge capacitor and complete the multiplication and addition operation; the lateral inhibition unit array is used to compare the output voltages of the neurons and output the maximum output voltage.

[0008] Optionally, the lateral inhibition unit array includes competition units arranged in an array; the number of lateral competition units and the number of vertical competition units in the lateral inhibition unit array are the same as the number of neurons; the competition unit includes a reconfigurable field effect transistor, and the source and drain of the reconfigurable field effect transistor distributed along a preset diagonal are connected to the same input signal line.

[0009] Optionally, the control gate of the reconfigurable field effect transistor in the side suppression unit array is electrically connected to the processing circuit as the output end of the side suppression unit array.

[0010] Optionally, the processing circuit includes a sense amplifier and an output buffer.

[0011] Optionally, the discharge capacitor is a MOM capacitor.

[0012] Optionally, the reconfigurable field effect transistor and the MOM capacitor in a single synapse are stacked on each other.

[0013] Optionally, the weight input decoder is electrically connected to the neuron array via a digital-to-analog converter.

[0014] Optionally, the weight decoder is electrically connected to the neuron array through a programming module.

[0015] Optionally, a charge pump is further included, wherein the charge pump is electrically connected to the programming module to transmit a voltage used for programming to the programming module.

[0016] The present invention also provides a method for using the competitive neural network chip, comprising:

[0017] Get the weight value of the neural network model after training;

[0018] The weight value is burned into each synapse of the neuron array through a weight decoder; the competitive neural network chip includes a neuron array, a weight decoder, an input decoder and a lateral inhibition unit array; the neuron array includes neurons arranged in a horizontal direction, and the neurons include synapses arranged in a vertical direction; the synapses include reconfigurable field effect transistors and discharge capacitors electrically connected to each other; the programmable gate of the reconfigurable field effect transistor in the neuron is electrically connected to the weight decoder, and the control gate of the reconfigurable field effect transistor of each row of synapses in the neuron array is electrically connected to the input decoder; the output end of each neuron in the neuron array is connected to the lateral inhibition unit array;

[0019] Inputting a control voltage to the control gate through the input decoder to generate a charging current to charge the discharge capacitor and complete a multiplication and accumulation operation;

[0020] The output voltages of the neurons are compared by the lateral inhibition unit array, and the maximum output voltage is output.

[0021] A competitive neural network chip provided by the present invention is characterized in that it includes a neuron array, a weight decoder, an input decoder and a lateral inhibition unit array; the neuron array includes neurons arranged in a horizontal direction, and the neurons include synapses arranged in a vertical direction; the synapses include reconfigurable field effect transistors and discharge capacitors electrically connected to each other; the programmable gate of the reconfigurable field effect transistor in the neuron is electrically connected to the weight decoder, and the control gate of the reconfigurable field effect transistor in each row of synapses in the neuron array is electrically connected to the input decoder; the output end of each neuron in the neuron array is connected to the lateral inhibition unit array; the weight decoder is used to burn the weight value into the reconfigurable field effect transistor through the programmable gate, and the input decoder is used to input the control voltage into the reconfigurable field effect transistor through the control gate to generate a charging current to charge the discharge capacitor and complete the multiplication and addition operation; the lateral inhibition unit array is used to compare the output voltages of the neurons and output the maximum output voltage.

[0022] By using reconfigurable field effect transistors to form synapses with discharge capacitors, the weight values ​​of the neural network are burned through the programmable gate of the reconfigurable field effect transistor; when the input signal is input, the control voltage is input through the control gate of the reconfigurable field effect transistor, which can generate a charging current to charge the discharge capacitor, complete the multiplication and accumulation operation, and finally output the maximum output voltage of each neuron through the side inhibition unit array, realizing a winner-takes-all competitive neural network chip. The competitive neural network chip is prepared using reconfigurable field effect transistors. Since the reconfigurable field effect transistor controls the carrier polarity in the channel through different voltage configurations, N-type and P-type devices are realized. With the flexibility of the reconfigurable field effect transistor, the competitive neural network chip can have the advantages of small area, low power consumption, high speed, and high precision.

[0023] The present invention also provides a method for using a competitive neural network chip, which also has the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic diagram of the architecture of a competitive neural network chip provided by an embodiment of the present invention;

[0026] Figure 2 for Figure 1 Schematic diagram of the structure of the neuron array in the middle;

[0027] Figure 3 for Figure 1 Schematic diagram of the structure of the medial-lateral inhibition unit array;

[0028] Figure 4 It is a schematic diagram of the structure of a reconfigurable field effect transistor;

[0029] Figure 5 is a schematic diagram of the structure of the discharge capacitor;

[0030] Figure 6 A flowchart of a method for using a competitive neural network chip provided in an embodiment of the present invention.

[0031] In the figure: 1. Neuron array, 11. Neuron, 12. Synapse, 13. Reconfigurable field effect transistor, 14. Discharge capacitor, 2. Weight decoder, 3. Input decoder, 4. Lateral inhibition unit array, 41. Competition unit. DETAILED DESCRIPTION

[0032] The core of the present invention is to provide a competitive neural network chip. In the prior art, how to provide a winner-takes-all competitive neural network chip based on reconfigurable field effect transistors is a problem that those skilled in the art need to solve urgently.

[0033] The competitive neural network chip provided by the present invention forms a synapse with a reconfigurable field effect transistor and a discharge capacitor. When burning the weight value of the neural network, it is burned through the programmable gate of the reconfigurable field effect transistor; when inputting the input signal, the control voltage is input through the control gate of the reconfigurable field effect transistor, which can generate a charging current to charge the discharge capacitor, complete the multiplication and accumulation operation, and finally output the maximum output voltage of each neuron through the side inhibition unit array, so as to realize a winner-takes-all competitive neural network chip. The competitive neural network chip is prepared using a reconfigurable field effect transistor. Since the reconfigurable field effect transistor controls the carrier polarity in the channel through different voltage configurations, N-type and P-type devices are realized. With the flexibility of the reconfigurable field effect transistor, the competitive neural network chip can have the advantages of small area, low power consumption, high speed, and high precision.

[0034] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of the architecture of a competitive neural network chip provided by an embodiment of the present invention; Figure 2 for Figure 1 Schematic diagram of the structure of the neuron array.

[0036] See also Figure 1In an embodiment of the present invention, a competitive neural network chip includes a neuron array 1, a weight decoder 2, an input decoder 3 and a lateral inhibition unit array 4; the neuron array 1 includes neurons 11 arranged in a horizontal direction, and the neurons 11 include synapses 12 arranged in a vertical direction; the synapses 12 include reconfigurable field effect transistors 13 and discharge capacitors 14 electrically connected to each other; the programmable gate of the reconfigurable field effect transistor 13 in the neuron 11 is electrically connected to the weight decoder 2, and the control gate of the reconfigurable field effect transistor 13 in each row of synapses 12 in the neuron array 1 is electrically connected to the control gate of the reconfigurable field effect transistor 13 in each row of synapses 12 in the neuron array 1 The input decoder 3 is electrically connected; the output end of each neuron 11 in the neuron array 1 is connected to the side inhibition unit array 4; the weight decoder 2 is used to burn the weight value to the reconfigurable field effect transistor 13 through the programmable gate, and the input decoder 3 is used to input the control voltage to the reconfigurable field effect transistor 13 through the control gate to generate a charging current to charge the discharge capacitor 14 and complete the multiplication and addition operation; the side inhibition unit array 4 is used to compare the output voltages of the neurons 11 and output the maximum output voltage.

[0037] See also Figure 2 The neuron array 1 is a structure in a competitive neural network chip that is mainly used to realize its multiplication and accumulation operation function. In an embodiment of the present invention, the neuron array 1 includes a plurality of neurons 11, and each neuron 11 includes a plurality of synapses 12. Specifically, the synapses 12 are arranged in a column direction to form neurons 11, and the neurons 11 are arranged in a horizontal direction to form a neuron array 1. At this time, the synapses 12 in the neuron array 1 are arranged in a matrix.

[0038] Each of the above-mentioned protrusions includes a reconfigurable field effect transistor 13 and a discharge capacitor 14 that are electrically connected to each other, wherein one end of the discharge capacitor 14 usually needs to be electrically connected to one electrode of the reconfigurable field effect transistor 13, so that the reconfigurable field effect transistor 13 can charge the discharge capacitor 14, and finally output the output voltage of each neuron 11 through the discharge capacitor 14. The above-mentioned reconfigurable field effect transistor 13 usually includes a source, a drain, a control gate and a programmable gate. Specifically, by adjusting the voltage magnitude and polarity of the programmable gate (VPG) and the control gate (VC), the current flowing through the drain source can be bidirectionally controlled.

[0039] Specifically, for a single synapse 12, one of its source and drain needs to be connected to the discharge capacitor 14, and the other needs to be grounded, and one end of the discharge capacitor 14 needs to be grounded. In the column direction, for neurons 11, the programmable gate of each synapse 12 needs to be electrically connected to the weight decoder 2 through a signal line, and multiple neurons 11 need to be electrically connected to the weight decoder 2 through multiple signal lines. Specifically, in an embodiment of the present invention, the weight decoder 2 needs to be electrically connected to the neuron array 1 through a programming module, and specifically needs to be electrically connected to each neuron 11 through a programming module. Typically, in an embodiment of the present invention, the competitive neural network chip may also include a charge pump, which needs to be electrically connected to the programming module to transmit a voltage for programming to the programming module.

[0040] In the row direction, the control gate of each synapse 12 needs to be electrically connected to the input decoder 3 through a signal line, and multiple rows of synapses 12 need to be electrically connected to the input decoder 3 through multiple signal lines. Specifically, in an embodiment of the present invention, the weighted input decoder 3 is electrically connected to the neuron array 1 through a digital-to-analog converter. The above decoder will generate an input signal corresponding to each synapse 12, and the input signal can be a digital signal with a practical application scenario, such as a pixel of an image. Afterwards, each input signal can be converted into a corresponding analog signal through a digital-to-analog converter and input into each synapse 12, specifically acting on the control gate of each reconfigurable field effect transistor 13, and finally generating a charging current to charge the discharge capacitor 14. At this time, the output voltage finally generated by a column of neurons 11 is the output voltage generated after the multiplication and addition operation is completed.

[0041] In the embodiment of the present invention, the output end of each of the neurons 11 in the neuron array 1 is connected to the lateral inhibition unit array 4; that is, the output voltage generated by each of the neurons 11 will be output to the lateral inhibition unit array 4. In the embodiment of the present invention, the lateral inhibition unit array 4 is used to compare the output voltages of the neurons 11 and output the maximum output voltage. The specific structure of the lateral inhibition unit array 4 will be described in detail in the following invention embodiments and will not be repeated here.

[0042] A competitive neural network chip provided by an embodiment of the present invention uses a reconfigurable field effect transistor 13 and a discharge capacitor 14 to form a synapse 12. When burning the weight value of the neural network, the programmable gate of the reconfigurable field effect transistor 13 is used for burning; when inputting an input signal, a control voltage is input through the control gate of the reconfigurable field effect transistor 13, which can generate a charging current to charge the discharge capacitor 14, complete the multiplication and accumulation operation, and finally output the maximum output voltage of each neuron 11 through the side inhibition unit array 4, so as to realize a winner-takes-all competitive neural network chip. The competitive neural network chip is prepared using a reconfigurable field effect transistor 13. Since the reconfigurable field effect transistor 13 controls the carrier polarity in the channel through different voltage configurations, N-type and P-type devices are realized. With the flexibility of the reconfigurable field effect transistor 13, the competitive neural network chip can have the advantages of small area, low power consumption, high speed, and high precision.

[0043] The specific structure of a competitive neural network chip provided by the present invention will be described in detail in the following invention embodiments.

[0044] Please refer to Figures 3 to 5 , Figure 3 for Figure 1 Schematic diagram of the structure of the medial-lateral inhibition unit array;

[0045] Figure 4 It is a schematic diagram of the structure of a reconfigurable field effect transistor; Figure 5 It is a schematic diagram of the structure of the discharge capacitor.

[0046] Different from the above-mentioned invention embodiment, the embodiment of the present invention further limits the structure of the competitive neural network chip, specifically the contralateral inhibition unit array 4, on the basis of the above-mentioned invention embodiment. The remaining contents have been introduced in detail in the above-mentioned invention embodiment and will not be repeated here.

[0047] See also Figure 3 In an embodiment of the present invention, the lateral inhibition unit array 4 includes competition units 41 arranged in an array; the number of horizontal competition units 41 and the number of vertical competition units 41 in the lateral inhibition unit array 4 are the same as the number of neurons 11; the competition unit 41 includes a reconfigurable field effect transistor 13, and the source and drain of the reconfigurable field effect transistor 13 distributed along a preset diagonal are connected to the same input signal line.

[0048] That is, in the embodiment of the present invention, the entire side inhibition unit array 4 specifically includes reconfigurable field effect transistors 13 distributed in a matrix, and each reconfigurable field effect transistor 13 forms a competition unit 41. The above-mentioned side inhibition unit array 4 is specifically distributed in an n×n matrix. It should be noted that the number of the above-mentioned competition units 41 in each row needs to be the same as the number of the above-mentioned neurons 11, that is, the output voltage finally output by each neuron 11 will be transmitted to a column of competition units 41 in the side inhibition unit array 4 through the signal line.

[0049] In addition to the reconfigurable field effect transistors 13 distributed along the preset diagonal line, the side suppression unit array 4 also includes the following: Figure 2 Except for the reconfigurable field effect transistors 13 distributed along the diagonal from the upper left to the lower right, one of the source and drain of the remaining reconfigurable field effect transistors 13 will be connected to the output signal line extending from the above-mentioned neuron 11, and the other will be grounded; and the source and drain of the reconfigurable field effect transistors 13 distributed along the preset diagonal are both connected to the output signal line extending from the above-mentioned neuron 11, and the output signal line will be connected to the signal line corresponding to the control gate in the reconfigurable field effect transistors 13 distributed along the preset diagonal, and at the same time, the programmable gate of the above-mentioned reconfigurable field effect transistor 13 is connected to the enabling circuit, so as to output the maximum output voltage among the output voltages output by the above-mentioned neuron 11.

[0050] The above-mentioned side inhibition unit array 4 is equivalent to an NMOS tube. If the output voltage of any of the above-mentioned neurons 11 after calculation is high, the conduction current of the corresponding NMOS tube will be larger, so that the control gate of the NMOS tube will be pulled to the ground. At this time, the outputs of other neurons 11 are invalid, and the neuron 11 wins the competition, thereby achieving a winner-takes-all situation.

[0051] Specifically, in the embodiment of the present invention, the control gate of the reconfigurable field effect transistor 13 in the side suppression unit array 4 is electrically connected to the processing circuit as the output end of the side suppression unit array 4. The above-mentioned processing circuit usually specifically includes a sensitive amplifier and an output buffer. Of course, other functional circuits can also be set in the embodiment of the present invention as long as the signal output by the side suppression unit array 4 can be pre-processed.

[0052] Typically, an interface circuit and a timing control circuit are also provided in the embodiments of the present invention, and their specific contents can refer to the prior art and will not be described in detail here. In the embodiments of the present invention, the weight decoder 2 inputs signals VPG[0] to VPG[n-1] related to the weight value to each neuron 11, corresponding to n neurons 11; the input decoder 3 writes signals VC[0] to VC[m-1] related to the input data to each synapse 12, corresponding to m rows of synapses 12; at this time, the neuron array 1 outputs n output voltages VBL[0] to VBL[n-1] to the lateral inhibition unit array 4, and the maximum output voltage among the above output voltages VBL[0] to VBL[n-1] is output through the lateral inhibition unit array 4.

[0053] See also Figure 4 as well as Figure 5 Specifically, in an embodiment of the present invention, the discharge capacitor 14 is a MOM capacitor. The MOM capacitor is a metal-oxide-metal capacitor. Usually, the reconfigurable field effect transistor 13 and the MOM capacitor are stacked on each other in the single synapse 12. Specifically, the reconfigurable field effect transistor 13 is usually arranged at the bottom layer, and the MOM capacitor is arranged directly above it.

[0054] A competitive neural network chip provided by an embodiment of the present invention specifically introduces the structure of the side inhibition unit array 4, which can realize a winner-takes-all competitive neural network chip.

[0055] The following is an introduction to a method for using a competitive neural network chip provided in an embodiment of the present invention. The method for using described below can be referenced to the competitive neural network chip described above.

[0056] Please refer to Figure 6 , Figure 6 A flowchart of a method for using a competitive neural network chip provided in an embodiment of the present invention.

[0057] See also Figure 6 In an embodiment of the present invention, the method for using the competitive neural network chip includes:

[0058] S101: Obtain the weight value of the trained neural network model.

[0059] In this step, the neural network model needs to be trained by software first to obtain the weight value of the model. Usually, the number of bits of each weight value is k.

[0060] S102: Burn the weight value into each synapse of the neuron array through the weight decoder.

[0061] In the embodiment of the present invention, the competitive neural network chip includes a neuron array 1, a weight decoder 2, an input decoder 3 and a lateral inhibition unit array 4; the neuron array 1 includes neurons 11 arranged in a horizontal direction, and the neurons 11 include synapses 12 arranged in a vertical direction; the synapses 12 include reconfigurable field effect transistors 13 and discharge capacitors 14 electrically connected to each other; the programmable gate of the reconfigurable field effect transistor 13 in the neuron 11 is electrically connected to the weight decoder 2, and the control gate of the reconfigurable field effect transistor 13 in each row of synapses 12 in the neuron array 1 is electrically connected to the input decoder 3; the output end of each neuron 11 in the neuron array 1 is connected to the lateral inhibition unit array 4. The specific structure of the competitive neural network chip has been described in detail in the above-mentioned invention embodiment, and will not be repeated here.

[0062] In this step, it is usually necessary to cooperate with the weight decoder 2 and the input decoder 3 to burn the weight value into each synapse 12 of the neuron array 1. Specifically, in this step, the weight decoder 2 and the programming module can be used to convert the k-bit weight value into a continuous pulse signal, which is applied to the programmable gate VPG of each column of neurons 11, and the voltage polarity of the control gate VC is changed to determine which row of synapses 12 to program. For example, if VC[0] is positive and the others are negative, then only the synapses 12 in the first row are programmed. In this step, the control gate can be opened row by row, and finally the weight value writing of the entire neuron array 1 is completed.

[0063] S103: Input a control voltage to the control gate through the input decoder to generate a charging current to charge the discharge capacitor 14, thereby completing the multiplication and accumulation operation.

[0064] In this step, the q-bit input signal corresponding to each synapse 12 first needs to be decoded by the input decoder 3, and then converted into an analog voltage by a digital-to-analog converter, which acts on the control gate VC, and finally generates a charging current to charge the discharge capacitor 14, and finally completes the multiplication and accumulation operation. Due to different weight values, the final output voltage VBL of each neuron 11 will also be different.

[0065] S104: Compare the output voltages of the neurons through the lateral inhibition unit array and output the maximum output voltage.

[0066] In this step, the lateral inhibition unit is used to compare the magnitude of the final output voltage VBL of each neuron 11, and finally the maximum value is output, which is the winner of the competition. The final recognition result is output through the processing circuit.

[0067] A method for using a competitive neural network chip provided by an embodiment of the present invention uses a reconfigurable field effect transistor 13 and a discharge capacitor 14 to form a synapse 12, and burns the weight value of the neural network through the programmable gate of the reconfigurable field effect transistor 13; when inputting an input signal, a control voltage is input through the control gate of the reconfigurable field effect transistor 13, which can generate a charging current to charge the discharge capacitor 14, complete the multiplication and accumulation operation, and finally output the maximum output voltage of each neuron 11 through the side inhibition unit array 4, so as to realize a winner-takes-all competitive neural network chip. The competitive neural network chip is prepared using a reconfigurable field effect transistor 13, because the reconfigurable field effect transistor 13 controls the carrier polarity in the channel through different voltage configurations, and realizes N-type and P-type devices. With the flexibility of the reconfigurable field effect transistor 13, the competitive neural network chip can have the advantages of small area, low power consumption, high speed, and high precision.

[0068] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0069] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0070] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0071] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0072] The above is a detailed introduction to a competitive neural network chip and a method for using a competitive neural network chip provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A competitive neural network chip, characterized in that: It includes a neuron array, a weight decoder, an input decoder and a lateral inhibition unit array; The neuron array includes neurons arranged in a transverse direction, and the neurons include synapses arranged in a longitudinal direction; the synapses include reconfigurable field effect transistors and discharge capacitors electrically connected to each other; the programmable gates of the reconfigurable field effect transistors in the neurons are electrically connected to the weight decoder, and the control gates of the reconfigurable field effect transistors in each row of synapses in the neuron array are electrically connected to the input decoder; the output ends of the neurons in the neuron array are connected to the lateral inhibition unit array; The weight decoder is used to burn the weight value into the reconfigurable field effect transistor through the programmable gate, and the input decoder is used to input the control voltage into the reconfigurable field effect transistor through the control gate to generate a charging current to charge the discharge capacitor and complete the multiplication and accumulation operation; the lateral inhibition unit array is used to compare the output voltages of the neurons and output the maximum output voltage; Among them, the lateral inhibition unit array includes competition units arranged in an array; the number of horizontal competition units and the number of vertical competition units in the lateral inhibition unit array are the same as the number of neurons; the competition unit includes a reconfigurable field effect transistor, and the source and drain of the reconfigurable field effect transistor distributed along a preset diagonal are connected to the same input signal line.

2. The competitive neural network chip according to claim 1, characterized in that: The control gate of the reconfigurable field effect transistor in the side suppression unit array is electrically connected to the processing circuit as the output end of the side suppression unit array.

3. The competitive neural network chip according to claim 2, characterized in that: The processing circuit includes a sense amplifier and an output buffer.

4. The competitive neural network chip according to claim 1, characterized in that: The discharge capacitor is a MOM capacitor.

5. The competitive neural network chip according to claim 1, characterized in that: The reconfigurable field effect transistor and the MOM capacitor in a single synapse are stacked on each other.

6. The competitive neural network chip according to claim 1, characterized in that: The input decoder is electrically connected to the neuron array via a digital-to-analog converter.

7. The competitive neural network chip according to claim 1, characterized in that: The weight decoder is electrically connected to the neuron array through a programming module.

8. The competitive neural network chip according to claim 7, characterized in that: A charge pump is also included, and the charge pump is electrically connected to the programming module to transmit a voltage used for programming to the programming module.

9. A method for using a competitive neural network chip, characterized in that: include: Get the weight value of the neural network model after training; The weight value is burned into each synapse of the neuron array through the weight decoder; the competitive neural network chip includes a neuron array, a weight decoder, an input decoder and a lateral inhibition unit array; the neuron array includes neurons arranged in a horizontal direction, and the neurons include synapses arranged in a vertical direction; the synapses include reconfigurable field effect transistors and discharge capacitors electrically connected to each other; the programmable gate of the reconfigurable field effect transistor in the neuron is electrically connected to the weight decoder, and the control gate of the reconfigurable field effect transistor of each row of synapses in the neuron array is electrically connected to the input decoder; the output end of each neuron in the neuron array is connected to the lateral inhibition unit array; the lateral inhibition unit array includes competition units arranged in an array; the number of horizontal competition units and the number of vertical competition units in the lateral inhibition unit array are the same as the number of neurons; the competition unit includes a reconfigurable field effect transistor, and the source and drain of the reconfigurable field effect transistor distributed along a preset diagonal are connected to the same input signal line; Inputting a control voltage to the control gate through the input decoder to generate a charging current to charge the discharge capacitor and complete a multiplication and accumulation operation; The output voltages of the neurons are compared by the lateral inhibition unit array, and the maximum output voltage is output.

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