Non-volatile memory device and method for manufacturing the same

Abstract

The present invention discloses a non-volatile memory element and a manufacturing method thereof, wherein the manufacturing method of the non-volatile memory element includes forming an element isolation structure in a substrate, forming a floating gate, an inner dielectric layer and a floating gate contact window on the substrate, and forming an inner connection structure on the inner dielectric layer. The inner connection structure includes multiple metal layers and multiple intermetallic dielectric (IMD) layers stacked alternately and multiple dielectric windows connecting the upper and lower metal layers. In the method, after forming the inner dielectric layer, a first comb-shaped contact window as a floating gate extension and a second comb-shaped contact window as a control gate are simultaneously formed in at least one of the inner dielectric layer and the intermetallic dielectric layer above the element isolation structure. During the formation of the inner connection structure, a structure electrically connecting the floating gate extension to the floating gate contact window is simultaneously formed.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory technology, and in particular to a non-volatile memory element and a manufacturing method thereof. Background Art

[0002] Non-volatile memory devices can perform multiple operations such as data storage, reading and erasing, and have advantages such as the data stored will not disappear when the power supply is interrupted, short data access time and low power consumption, so they have become widely used in various electronic products. Multi-time programmable (MTP) memory devices have become one of the current research focuses because they can change their access status multiple times.

[0003] In order to meet the miniaturization of device size, several new types of MTP memory devices have been developed. For example, the voltage coupling ratio between the floating gate and the control gate is increased according to device design, so that the programming / erasing efficiency of the memory device is improved.

[0004] However, since the way to increase the voltage coupling rate between the floating gate and the control gate is mostly to increase the coupling area between the floating gate and the control gate, a large-area plasma etching process is often required to produce the required circuit pattern. The plasma itself has high-energy particles and charged ions and electrons, which affects the reliability of the memory element. For example, in a memory element with a metal-oxide-metal (MOM) capacitor structure, there is a large area of ​​metal wiring connected to the floating gate. Therefore, during the plasma etching of the metal wiring, a large amount of charge will accumulate on the floating gate, causing the so-called antenna effect and damaging the gate oxide layer, resulting in reduced product yield and reliability degradation. As the size of the element and the thickness of the gate oxide layer become smaller and smaller, the above problems will become more serious. Summary of the invention

[0005] The invention provides a method for manufacturing a non-volatile memory element, which can solve the problems of reduced product yield and reduced reliability caused by antenna effect.

[0006] The present invention also provides a non-volatile memory element, which has a high voltage coupling rate between a floating gate and a control gate and can improve product yield and element reliability.

[0007] The manufacturing method of the non-volatile memory device of the present invention comprises forming a device isolation structure defining an active region in a substrate; forming a floating gate on the substrate in the active region; forming an inner layer dielectric (ILD) layer on the substrate to cover the floating gate and the device isolation structure; forming a floating gate contact window in the inner layer dielectric layer to contact the floating gate; and forming an interconnection structure on the inner layer dielectric (ILD) layer, wherein the interconnection structure comprises a plurality of metal layers and a plurality of intermetal dielectric (IMD) layers stacked alternately and a plurality of dielectric windows connecting the upper and lower metal layers. The manufacturing method is characterized in that: after forming the inner layer dielectric layer, a first comb-shaped contact window as a floating gate extension and a second comb-shaped contact window as a control gate are simultaneously formed in at least one of the inner layer dielectric layer and the intermetal dielectric layer above the device isolation structure; and during the formation of the interconnection structure, a structure electrically connecting the floating gate extension to the floating gate contact window is simultaneously formed.

[0008] In one embodiment of the present invention, the first comb-shaped contact window and the second comb-shaped contact window are formed simultaneously with the floating gate contact window.

[0009] In one embodiment of the present invention, the first comb-shaped contact window and the second comb-shaped contact window are formed simultaneously with at least one of the plurality of vias.

[0010] In one embodiment of the present invention, the above-mentioned manufacturing method may also include forming a first comb-shaped metal structure and a second comb-shaped metal structure in at least one layer of the metal interlayer dielectric layer, and during the formation of the internal connection structure, forming an electrical connection between the above-mentioned floating gate extension and the above-mentioned first comb-shaped metal structure, and forming an electrical connection between the above-mentioned control gate and the above-mentioned second comb-shaped metal structure.

[0011] In one embodiment of the present invention, the step of forming the above-mentioned floating gate may also include: forming a selection gate arranged in parallel with the above-mentioned floating gate in the active region, and the selection gate is an N-type or P-type metal oxide semiconductor transistor, which is only used to select the gate of the auxiliary transistor of the storage unit to be erased, read or programmed in the memory circuit.

[0012] The non-volatile memory device of the present invention comprises a substrate, a floating gate, an inner dielectric layer, a floating gate contact window, an inner connection structure, a first comb-shaped contact window and a second comb-shaped contact window. The substrate has an element isolation structure defining an active region, the floating gate is formed on the substrate in the active region, and the inner dielectric layer is formed on the substrate and covers the floating gate and the element isolation structure. The floating gate contact window is formed in the inner dielectric layer and contacts the floating gate, and the inner connection structure is formed on the inner dielectric layer, wherein the inner connection structure comprises a plurality of metal layers and a plurality of intermetallic dielectric (IMD) layers stacked alternately and a plurality of dielectric windows connecting the upper and lower metal layers. The first comb-shaped contact window is formed as a floating gate extension in at least one of the inner dielectric layer and the intermetallic dielectric layer above the element isolation structure, and the floating gate extension is connected to the floating gate contact window through the inner connection structure. The second comb-shaped contact window is formed as a control gate and is formed in the same layer (the at least one layer) above the element isolation structure in an alternating manner with the first comb-shaped contact window.

[0013] In another embodiment of the present invention, the floating gate contact window comprises a single-layer structure or a multi-layer structure.

[0014] In another embodiment of the present invention, the non-volatile memory device may further include a first comb-shaped metal structure and a second comb-shaped metal structure. The first comb-shaped metal structure is formed in at least one layer of the multi-layer intermetallic dielectric layer, and the first comb-shaped metal structure is connected to the first comb-shaped contact window through an internal connection structure. The second comb-shaped metal structure and the first comb-shaped metal structure are alternately formed in the same layer (the at least one layer) of the multi-layer intermetallic dielectric layer.

[0015] In another embodiment of the present invention, the second comb-shaped metal structure is electrically connected to the second comb-shaped contact window, and the first comb-shaped metal structure is electrically connected to the first metal contact window.

[0016] In another embodiment of the present invention, the first comb-shaped metal structure is formed above the device isolation structure.

[0017] In another embodiment of the present invention, the height of the first comb-shaped contact window is greater than the height of the floating gate.

[0018] In another embodiment of the present invention, the non-volatile memory device may further include a selection gate formed in the active region and arranged in parallel with the floating gate.

[0019] Based on the above, the present invention uses a comb-shaped contact window as a floating gate extension and another comb-shaped contact window as a control gate, so that the voltage coupling rate between the floating gate and the control gate can be greatly improved, thereby improving the programming / erasing efficiency of the device. Moreover, in the process of manufacturing the comb-shaped contact window, because the comb-shaped contact window is located above the device isolation structure and is electrically connected to the floating gate through a metal layer higher than the first comb-shaped contact window and the first comb-shaped contact window, the gate insulation layer under the floating gate will not be damaged due to the antenna effect, thereby improving the yield and reliability of subsequent products.

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1E is a schematic diagram of a manufacturing process of a non-volatile memory element according to a first embodiment of the present invention;

[0022] FIG. 2A to FIG. 2B is a schematic diagram of an alternative example of the manufacturing process of the first embodiment;

[0023] Figure 2C is a schematic diagram of another alternative example of the manufacturing process of the first embodiment;

[0024] Figure 3 is a schematic diagram of a non-volatile memory element according to a second embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of a non-volatile memory element according to a third embodiment of the present invention;

[0026] FIG. 5A to FIG. 5B It is a schematic diagram of a manufacturing process of a non-volatile memory element according to a fourth embodiment of the present invention.

[0027] Explanation of symbols

[0028] 100: Base

[0029] 102: Active area

[0030] 104: Component isolation structure

[0031] 106: floating gate

[0032] 108: Select gate

[0033] 110: Gate insulation layer

[0034] 112: Inner dielectric layer

[0035] 114: floating gate contact window

[0036] 116, 306: first comb-shaped contact window

[0037] 118, 308: second comb-shaped contact window

[0038] 120a, 120b, 120c, 202a, 202b, 202c, 310a, 310b, 310c: metal lines

[0039] 122, 200, 204, 300, 302, 304, 500, 506: intermetallic dielectric layer

[0040] 206: Dielectric layer

[0041] 208a, 208b, 208c: contact window

[0042] 502: First comb-shaped metal structure

[0043] 504: Second comb-shaped metal structure

[0044] h1, h2: height

[0045] M1, M2, M3, M4, M5: metal layer

[0046] V1, V2, V3, V4: Interlayer Window DETAILED DESCRIPTION

[0047] Figures 1A to 1E It is a schematic diagram of a manufacturing process of a non-volatile memory device according to a first embodiment of the present invention.

[0048] Please refer to Figure 1A , a device isolation structure 104 defining an active region 102 is formed in the substrate 100. Then, a floating gate 106 is formed on the substrate 100 in the active region 102. The manufacturing process thereof is, for example, to first deposit a polysilicon layer (not shown) on the surface of the substrate 100, and then pattern the polysilicon layer by photolithography and etching to obtain the floating gate 106. Moreover, while forming the floating gate 106, a select gate 108 arranged in parallel with the floating gate 106 can be formed in the active region 102 according to the device design. The manufacturing process thereof is the same as that of the floating gate 106. The select gate 108 is a metal oxide semiconductor transistor (which can be N-type or P-type). This transistor is only used as the gate of the auxiliary transistor of the memory cell to be read, erased or programmed in the memory circuit. In addition, a gate insulating layer 110 is usually formed before forming the floating gate 106 / select gate 108.

[0049] Next, please refer to Figure 1B, an inner layer dielectric (ILD) layer 112 is formed on the substrate 100 to cover the floating gate 106 / select gate 108 and the device isolation structure 104 .

[0050] Then, please refer to Figure 1C A floating gate contact window 114 is formed in the inner dielectric layer 112 to contact the floating gate 106, and a first comb-type contact window 116 and a second comb-type contact window 118 are simultaneously formed in the inner dielectric layer 112 above the device isolation structure 104, so that the second comb-type contact window 118 and the first comb-type contact window 116 are staggeredly formed in the same layer (the inner dielectric layer 112) above the device isolation structure 104. In the present embodiment, the floating gate contact window 114 is a single-layer structure, and the manufacturing process of the floating gate contact window 114 and the first comb-shaped contact window 116 and the second comb-shaped contact window 118 is, for example, to first form a photoresist (not shown) on the surface of the inner dielectric layer 112, and then pattern this layer of photoresist to expose a portion of the inner dielectric layer 112 (i.e., the location where the floating gate contact window 114, the first and second comb-shaped contact windows 116 and 118 are predetermined to be formed), and then the exposed inner dielectric layer 112 is removed by etching to form an opening, and then the floating gate contact window 114, the first and second comb-shaped contact windows 116 and 118 are formed in the opening. A comb-shaped contact window 116 and a second comb-shaped contact window 118 can be used in conjunction with a contact window planarization process, wherein the aforementioned contacts (114, 116 and 118) are, for example, Ti / TiN / W structures or structures of other materials, and the height h1 of the first comb-shaped contact window 116 is approximately greater than the height h2 of the floating gate 106. Therefore, compared with the conventional device using a polysilicon layer as the floating gate or its extension, the space in the direction perpendicular to the substrate 100 can be fully utilized to greatly improve the capacitive coupling rate of the first comb-shaped contact window 116 and the second comb-shaped contact window 118. In addition, because the first comb-shaped contact window 116 and the second comb-shaped contact window 118 are formed above the device isolation structure 104 and are electrically connected to the floating gate 106 using a higher metal layer, the non-conventional structure has completed the electrical connection between the floating gate and its extension when etching the floating gate and its extension, so the gate insulation layer 110 under the floating gate 106 / select gate 108 will not be damaged by the plasma manufacturing process, thereby affecting the yield and reliability of subsequent products.

[0051] Then, please refer to Figure 1D , an internal connection structure is formed on the inner dielectric layer 112, for example, a first metal layer M1 is first formed. The manufacturing process can first deposit a metal material (not shown) on the surface of the inner dielectric layer 112, and then pattern the above-mentioned metal material (such as aluminum) by photolithography and etching to obtain metal lines 120a, 120b and 120c respectively connecting the floating gate contact window 114, the first comb-shaped contact window 116 and the second comb-shaped contact window 118.

[0052] Afterwards, please refer to Figure 1E , a first intermetallic dielectric (IMD) layer 122 is formed on the inner dielectric layer 112, and a first via V1 is formed in the first IMD layer 122, wherein one first via V1 contacts the metal line 120a, and another first via V1 contacts the metal line 120b. Afterwards, a second metal layer M2 connected to the first via V1 is formed on the first IMD layer 122. The manufacturing process and structure of the first via V1 can refer to the relevant content of the floating gate contact 114, and the manufacturing process of the second metal layer M2 can refer to the relevant content of the first metal layer M1, which will not be repeated.

[0053] In the first embodiment, the first comb-shaped contact window 116 and the second comb-shaped contact window 118 are formed in the inner dielectric layer 112, but the present invention is not limited to this. In other embodiments, the first comb-shaped contact window 116 and the second comb-shaped contact window 118 can be formed in the first IMD layer 122 or the IMD layer subsequently formed thereon, or can be formed in the inner dielectric layer 112 and the IMD layer at the same time. Moreover, if the first comb-shaped contact window 116 and the second comb-shaped contact window 118 are regarded as a pair of complementary conductive structures, their number can also be increased according to needs and set in several layers of IMD layers. The first comb-shaped contact window 116 serves as a floating gate extension, and the second comb-shaped contact window 118 serves as a control gate, so the floating gate extension (116) can be electrically connected to the floating gate contact window 114 through the internal connection structure (metal line 120b, first layer of vias V1, second metal layer M2, first layer of vias V1, metal line 120a). Similarly, Figure 1E Although the connection path of the second comb-shaped contact window 118 is not shown, it should be known that a first via window and a second metal layer connected to the metal line 120c can be formed at this stage to connect to the peripheral area.

[0054] FIG. 2A to FIG. 2B is a schematic diagram of an alternative example of the manufacturing process of the first embodiment, which shows Figure 1C The next steps.

[0055] exist Figure 2A In the process, a first intermetallic dielectric (IMD) layer 200 is first deposited, and then a groove for forming the first metal layer M1 is etched out, and then a layer of metal material (such as copper) is deposited into the groove by physical vapor deposition (PVD) or electrochemical deposition (ECD), and then the metal material is planarized by a metal chemical mechanical polishing (CMP) process to form a Figure 2A The metal lines 202a, 202b, 202c in.

[0056] Then, in Figure 2B The figure shows an internal connection formed by a dual damascene process, that is, first depositing a second IMD layer 204, then etching an opening for forming a first via V1 therein, and then etching a groove for forming a second metal layer M2 in the second IMD layer 204, wherein the groove is located above the opening. Next, a layer of metal material (such as copper) is deposited by PVD or ECD to fill the groove and opening, and then the metal material is planarized by a metal CMP process to simultaneously form the first via V1 and the second metal layer M2.

[0057] therefore, Figure 2B The internal connection structure and Figure 1E Similarly, the floating gate extension 116 can be electrically connected to the floating gate contact window 114 through the interconnect structure (metal line 202b, first layer via window V1, second metal layer M2, first layer via window V1, metal line 202a). Figure 2B Although the connection path of the second comb-shaped contact window 118 is not shown, it should be known that a first via window and a second metal layer connected to the metal line 202c can be formed at this stage to connect to the peripheral area.

[0058] Figure 2C is a schematic diagram of another alternative example of the manufacturing process of the first embodiment, which shows Figure 1C The next steps.

[0059] exist Figure 2C In the embodiment, the floating gate contact window 114 can be regarded as a multi-layer structure, that is, after the floating gate contact window 114 is formed, a dielectric layer 206 is first deposited on the floating gate contact window 114 and then a contact window 208a for local wiring is formed. While the contact window 208a is formed, contact windows 208b and 208c can be formed on the first comb-shaped contact window 116 and the second comb-shaped contact window 118. The manufacturing process and structure of the aforementioned contact windows 208a, 208b and 208c can refer to the relevant content of the floating gate contact window 114, and will not be repeated here. The subsequent manufacturing process is as follows: Figure 1D to Figure 1E shown.

[0060] Figure 3 1 is a schematic diagram of a non-volatile memory device according to a second embodiment of the present invention, wherein the element symbols of the first embodiment are used to represent the same or similar components, and the description of the same components can refer to the above-mentioned related content, which will not be repeated here.

[0061] Please refer to Figure 3The interconnect structure in the non-volatile memory device of the second embodiment includes a plurality of alternately stacked metal layers M1, M2, M3, M4, M5 and a plurality of inter-metal dielectric (IMD) layers 122, 300, 302, 304 and a plurality of vias V1, V2, V3, V4 connecting the upper and lower metal layers. In this embodiment, the first comb-type contact 306 and the second comb-type contact 308 are formed in the IMD layer 302, and are connected to the second comb-type contact 308 via a metal line 310c in the metal layer M4. The first comb-type contact 306 is electrically connected to the floating gate contact 114 through the interconnect structure (metal line 310b, via V4, metal layer M5, via V4, metal line 310a, via V3, metal layer M3, via V2, metal layer M2, via V1, metal layer M1).

[0062] Figure 4 1 is a schematic diagram of a non-volatile memory device according to a third embodiment of the present invention, wherein the element symbols of the first and second embodiments are used to represent the same or similar components, and the description of the same components can refer to the above-mentioned related content, which will not be repeated here.

[0063] Please refer to Figure 4 The non-volatile memory device of the third embodiment has two first comb-shaped contact windows 116 and 306 as floating gate extensions and two second comb-shaped contact windows 118 and 308 as control gates. The floating gate extensions 116 and 306 are electrically connected to the floating gate contact window 114 through an internal wiring structure. Similarly, Figure 4 Although the connection paths of the second comb-shaped contact windows 118 and 308 are not shown, it should be known that a structure connecting the metal lines 120c and 310c can be formed in the interconnect structure.

[0064] FIG. 5A to FIG. 5B 1 is a schematic diagram of a manufacturing process of a non-volatile memory device according to a fourth embodiment of the present invention, wherein the element symbols of the first embodiment are used to represent the same or similar components, and the description of the same components can refer to the above-mentioned related contents, which will not be repeated here.

[0065] first, Figure 5A Displayed Figure 1EThe following steps. Then, a second IMD layer 500 is formed on the first IMD layer 122, and a second via V2 is formed in the second IMD layer 500, wherein the second via V2 is in contact with the second metal layer M2. The manufacturing process of the second via V2 can refer to the relevant content of the floating gate contact window 114, and will not be repeated here. Next, a third metal layer M3 is formed on the second IMD layer 500, and a first comb-type metal structure 502 and a second comb-type metal structure 504 are formed at the same time. The manufacturing process thereof is, for example, first depositing a metal material (not shown) on the surface of the second IMD layer 500, and then patterning the above metal material by photolithography and etching to obtain the metal layer M3, the first comb-type metal structure 502 and the second comb-type metal structure 504 which are not connected to each other. Since the first comb-shaped metal structure 502 is electrically connected to the floating gate extension 116 through an upper conductive line, the antenna effect in the etching process can be avoided from damaging the structure of the gate insulating layer 110 , thereby improving the yield and reliability of the product.

[0066] Next, please refer to Figure 5B , a third IMD layer 506 is formed on the second IMD layer 500, and a third via V3 is formed in the third IMD layer 506, wherein one via V3 is in contact with the third metal layer M3, and the other via V3 is in contact with the first comb-shaped metal structure 502. Afterwards, a fourth metal layer M4 is formed on the third IMD layer 506 to connect the two vias V3. Therefore, the first comb-shaped metal structure 502 can be electrically connected to the floating gate extension (116) and / or the floating gate 106 through the interconnect structure. Similarly, Figure 5B Although the connection path of the second comb-shaped metal structure 504 is not shown, it should be known that a structure connecting the second comb-shaped metal structure 504 and the second comb-shaped contact window 118 can be formed in the interconnect structure. In addition, the manufacturing process and structure of the aforementioned via window V3 can refer to the relevant content of the floating gate contact window 114, and will not be repeated here.

[0067] In this embodiment, the first comb-shaped metal structure 502 and the second comb-shaped metal structure 504 are formed in the third IMD layer 506 , but the present invention is not limited thereto. The first and second comb-shaped metal structures may also be formed in other IMD layers, and their number may be increased as required.

[0068] In summary, in the process of manufacturing the first and second comb-shaped contact windows of the present invention, because the large-area first and second comb-shaped contact windows are electrically isolated from the floating gate, the gate insulation layer under the floating gate will not be damaged by the plasma manufacturing process, and the first comb-shaped contact window can be connected to the floating gate through the upper layer interconnect manufacturing process without additional steps. Moreover, because the height of the comb-shaped contact window is much greater than the thickness of the floating gate, the element with the first comb-shaped contact window as the floating gate extension and the other comb-shaped contact window as the control gate can greatly improve the voltage coupling rate between the floating gate and the control gate, thereby improving the programming / erasing efficiency of the element.

[0069] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. A method for manufacturing a non-volatile memory element, comprising: forming a device isolation structure defining an active region in the substrate; forming a floating gate on the substrate in the active region; forming an inner layer dielectric (ILD) layer on the substrate to cover the floating gate and the device isolation structure; forming a floating gate contact window in the inter-layer dielectric layer to contact the floating gate; as well as An internal connection structure is formed on the inner dielectric layer, wherein the internal connection structure includes multiple metal layers and multiple intermetallic dielectric (IMD) layers stacked alternately and multiple vias connecting the upper and lower metal layers. The manufacturing method is characterized in that: After forming the inner dielectric layer, simultaneously forming a first comb-shaped contact window as a floating gate extension and a second comb-shaped contact window as a control gate in at least one of the inner dielectric layer and the intermetallic dielectric layer above the device isolation structure; as well as During the formation of the interconnect structure, a structure electrically connecting the floating gate extension to the floating gate contact window is simultaneously formed. 2 . The method for manufacturing a non-volatile memory device as claimed in claim 1 , wherein the first comb-shaped contact window and the second comb-shaped contact window are formed simultaneously with the floating gate contact window. 3 . The method for manufacturing a non-volatile memory device as claimed in claim 1 , wherein the first comb-shaped contact window and the second comb-shaped contact window are formed simultaneously with at least one of the plurality of vias.

4. The method for manufacturing a non-volatile memory device as claimed in claim 1, further comprising: forming a first comb-shaped metal structure and a second comb-shaped metal structure in at least one layer of the multi-layer intermetallic dielectric layer; as well as During the formation of the interconnect structure, an electrical connection is formed between the floating gate extension and the first comb-shaped metal structure, and an electrical connection is formed between the control gate and the second comb-shaped metal structure.

5. The method for manufacturing a non-volatile memory device as claimed in claim 1 , wherein the step of forming the floating gate further comprises: A selection gate is formed in the active region and arranged in parallel with the floating gate. The selection gate is an N-type or P-type metal oxide semiconductor transistor for selecting a designated memory address in the memory array when performing reading, erasing or programming.

6. A non-volatile memory device, characterized in that: include: A substrate having a component isolation structure defining an active region; a floating gate formed on the substrate in the active region; An inner dielectric layer formed on the substrate and covering the floating gate and the element isolation structure; A floating gate contact window formed in the inner dielectric layer and contacting the floating gate; An internal connection structure formed on the inner dielectric layer, wherein the internal connection structure includes multiple metal layers and multiple inter-metal dielectric (IMD) layers stacked alternately and a plurality of vias connecting upper and lower metal layers; A first comb-shaped contact window is formed as a floating gate extension in at least one of the inner dielectric layer and the intermetallic dielectric layer above the device isolation structure and below at least one metal layer of the interconnect structure, and the floating gate extension is connected to the floating gate contact window through the interconnect structure; as well as The second comb-shaped contact window is used as a control gate and is formed in the at least one layer above the element isolation structure in an alternating manner with the first comb-shaped contact window. 7 . The non-volatile memory device as claimed in claim 6 , wherein the floating gate contact comprises a single-layer structure or a multi-layer structure.

8. The non-volatile memory device of claim 6, further comprising: A first comb-shaped metal structure is formed in at least one layer of the multi-layer intermetallic dielectric layer, and the first comb-shaped metal structure is connected to the first comb-shaped contact window through the inner connection structure; as well as The second comb-shaped metal structure is formed in the at least one layer of the multi-layer intermetallic dielectric layer in an alternating manner with the first comb-shaped metal structure. 9 . The non-volatile memory device as claimed in claim 8 , wherein the second comb-type metal structure is electrically connected to the second comb-type contact window.

10. The non-volatile memory device as claimed in claim 8, wherein the first comb-type metal structure is formed above the device isolation structure.

11. The non-volatile memory device as claimed in claim 6, wherein a height of the first comb-shaped contact window is greater than a height of the floating gate.

12. The non-volatile memory device of claim 6, further comprising: A select gate is formed in the active region and arranged in parallel with the floating gate.

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